[deliverable/linux.git] / arch / arm / mach-shmobile / setup-r8a7791.c

/*
 * r8a7791 processor support
 *
 * Copyright (C) 2013  Renesas Electronics Corporation
 * Copyright (C) 2013  Renesas Solutions Corp.
 * Copyright (C) 2013  Magnus Damm
 *
 * This program is free software; you can redistribute it and/or modify
 * it under the terms of the GNU General Public License as published by
 * the Free Software Foundation; version 2 of the License.
 *
 * This program is distributed in the hope that it will be useful,
 * but WITHOUT ANY WARRANTY; without even the implied warranty of
 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
 * GNU General Public License for more details.
 *
 * You should have received a copy of the GNU General Public License
 * along with this program; if not, write to the Free Software
 * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA  02110-1301  USA
 */

#include <linux/irq.h>
#include <linux/kernel.h>
#include <linux/of_platform.h>
#include <linux/platform_data/gpio-rcar.h>
#include <linux/platform_data/irq-renesas-irqc.h>
#include <linux/serial_sci.h>
#include <linux/sh_timer.h>
#include <mach/common.h>
#include <mach/irqs.h>
#include <mach/r8a7791.h>
#include <mach/rcar-gen2.h>
#include <asm/mach/arch.h>

static const struct resource pfc_resources[] __initconst = {
	DEFINE_RES_MEM(0xe6060000, 0x250),
};

#define r8a7791_register_pfc()						\
	platform_device_register_simple("pfc-r8a7791", -1, pfc_resources, \
					ARRAY_SIZE(pfc_resources))

#define R8A7791_GPIO(idx, base, nr)					\
static const struct resource r8a7791_gpio##idx##_resources[] __initconst = { \
	DEFINE_RES_MEM((base), 0x50),					\
	DEFINE_RES_IRQ(gic_spi(4 + (idx))),				\
};									\
									\
static const struct gpio_rcar_config					\
r8a7791_gpio##idx##_platform_data __initconst = {			\
	.gpio_base	= 32 * (idx),					\
	.irq_base	= 0,						\
	.number_of_pins	= (nr),						\
	.pctl_name	= "pfc-r8a7791",				\
	.has_both_edge_trigger = 1,					\
};									\

R8A7791_GPIO(0, 0xe6050000, 32);
R8A7791_GPIO(1, 0xe6051000, 32);
R8A7791_GPIO(2, 0xe6052000, 32);
R8A7791_GPIO(3, 0xe6053000, 32);
R8A7791_GPIO(4, 0xe6054000, 32);
R8A7791_GPIO(5, 0xe6055000, 32);
R8A7791_GPIO(6, 0xe6055400, 32);
R8A7791_GPIO(7, 0xe6055800, 26);

#define r8a7791_register_gpio(idx)					\
	platform_device_register_resndata(&platform_bus, "gpio_rcar", idx, \
		r8a7791_gpio##idx##_resources,				\
		ARRAY_SIZE(r8a7791_gpio##idx##_resources),		\
		&r8a7791_gpio##idx##_platform_data,			\
		sizeof(r8a7791_gpio##idx##_platform_data))

void __init r8a7791_pinmux_init(void)
{
	r8a7791_register_pfc();
	r8a7791_register_gpio(0);
	r8a7791_register_gpio(1);
	r8a7791_register_gpio(2);
	r8a7791_register_gpio(3);
	r8a7791_register_gpio(4);
	r8a7791_register_gpio(5);
	r8a7791_register_gpio(6);
	r8a7791_register_gpio(7);
}

#define SCIF_COMMON(scif_type, baseaddr, irq)			\
	.type		= scif_type,				\
	.mapbase	= baseaddr,				\
	.flags		= UPF_BOOT_AUTOCONF | UPF_IOREMAP,	\
	.irqs		= SCIx_IRQ_MUXED(irq)

#define SCIFA_DATA(index, baseaddr, irq)		\
[index] = {						\
	SCIF_COMMON(PORT_SCIFA, baseaddr, irq),		\
	.scbrr_algo_id	= SCBRR_ALGO_4,			\
	.scscr = SCSCR_RE | SCSCR_TE,	\
}

#define SCIFB_DATA(index, baseaddr, irq)	\
[index] = {					\
	SCIF_COMMON(PORT_SCIFB, baseaddr, irq),	\
	.scbrr_algo_id	= SCBRR_ALGO_4,		\
	.scscr = SCSCR_RE | SCSCR_TE,		\
}

#define SCIF_DATA(index, baseaddr, irq)		\
[index] = {						\
	SCIF_COMMON(PORT_SCIF, baseaddr, irq),		\
	.scbrr_algo_id	= SCBRR_ALGO_2,			\
	.scscr = SCSCR_RE | SCSCR_TE,	\
}

#define HSCIF_DATA(index, baseaddr, irq)		\
[index] = {						\
	SCIF_COMMON(PORT_HSCIF, baseaddr, irq),		\
	.scbrr_algo_id	= SCBRR_ALGO_6,			\
	.scscr = SCSCR_RE | SCSCR_TE,	\
}

enum { SCIFA0, SCIFA1, SCIFB0, SCIFB1, SCIFB2, SCIFA2, SCIF0, SCIF1,
	SCIF2, SCIF3, SCIF4, SCIF5, SCIFA3, SCIFA4, SCIFA5 };

static const struct plat_sci_port scif[] __initconst = {
	SCIFA_DATA(SCIFA0, 0xe6c40000, gic_spi(144)), /* SCIFA0 */
	SCIFA_DATA(SCIFA1, 0xe6c50000, gic_spi(145)), /* SCIFA1 */
	SCIFB_DATA(SCIFB0, 0xe6c20000, gic_spi(148)), /* SCIFB0 */
	SCIFB_DATA(SCIFB1, 0xe6c30000, gic_spi(149)), /* SCIFB1 */
	SCIFB_DATA(SCIFB2, 0xe6ce0000, gic_spi(150)), /* SCIFB2 */
	SCIFA_DATA(SCIFA2, 0xe6c60000, gic_spi(151)), /* SCIFA2 */
	SCIF_DATA(SCIF0, 0xe6e60000, gic_spi(152)), /* SCIF0 */
	SCIF_DATA(SCIF1, 0xe6e68000, gic_spi(153)), /* SCIF1 */
	SCIF_DATA(SCIF2, 0xe6e58000, gic_spi(22)), /* SCIF2 */
	SCIF_DATA(SCIF3, 0xe6ea8000, gic_spi(23)), /* SCIF3 */
	SCIF_DATA(SCIF4, 0xe6ee0000, gic_spi(24)), /* SCIF4 */
	SCIF_DATA(SCIF5, 0xe6ee8000, gic_spi(25)), /* SCIF5 */
	SCIFA_DATA(SCIFA3, 0xe6c70000, gic_spi(29)), /* SCIFA3 */
	SCIFA_DATA(SCIFA4, 0xe6c78000, gic_spi(30)), /* SCIFA4 */
	SCIFA_DATA(SCIFA5, 0xe6c80000, gic_spi(31)), /* SCIFA5 */
};

static inline void r8a7791_register_scif(int idx)
{
	platform_device_register_data(&platform_bus, "sh-sci", idx, &scif[idx],
				      sizeof(struct plat_sci_port));
}

static const struct sh_timer_config cmt00_platform_data __initconst = {
	.name = "CMT00",
	.timer_bit = 0,
	.clockevent_rating = 80,
};

static const struct resource cmt00_resources[] __initconst = {
	DEFINE_RES_MEM(0xffca0510, 0x0c),
	DEFINE_RES_MEM(0xffca0500, 0x04),
	DEFINE_RES_IRQ(gic_spi(142)), /* CMT0_0 */
};

#define r8a7791_register_cmt(idx)					\
	platform_device_register_resndata(&platform_bus, "sh_cmt",	\
					  idx, cmt##idx##_resources,	\
					  ARRAY_SIZE(cmt##idx##_resources), \
					  &cmt##idx##_platform_data,	\
					  sizeof(struct sh_timer_config))

static struct renesas_irqc_config irqc0_data = {
	.irq_base = irq_pin(0), /* IRQ0 -> IRQ9 */
};

static struct resource irqc0_resources[] = {
	DEFINE_RES_MEM(0xe61c0000, 0x200), /* IRQC Event Detector Block_0 */
	DEFINE_RES_IRQ(gic_spi(0)), /* IRQ0 */
	DEFINE_RES_IRQ(gic_spi(1)), /* IRQ1 */
	DEFINE_RES_IRQ(gic_spi(2)), /* IRQ2 */
	DEFINE_RES_IRQ(gic_spi(3)), /* IRQ3 */
	DEFINE_RES_IRQ(gic_spi(12)), /* IRQ4 */
	DEFINE_RES_IRQ(gic_spi(13)), /* IRQ5 */
	DEFINE_RES_IRQ(gic_spi(14)), /* IRQ6 */
	DEFINE_RES_IRQ(gic_spi(15)), /* IRQ7 */
	DEFINE_RES_IRQ(gic_spi(16)), /* IRQ8 */
	DEFINE_RES_IRQ(gic_spi(17)), /* IRQ9 */
};

#define r8a7791_register_irqc(idx)					\
	platform_device_register_resndata(&platform_bus, "renesas_irqc", \
					  idx, irqc##idx##_resources,	\
					  ARRAY_SIZE(irqc##idx##_resources), \
					  &irqc##idx##_data,		\
					  sizeof(struct renesas_irqc_config))

static const struct resource thermal_resources[] __initconst = {
	DEFINE_RES_MEM(0xe61f0000, 0x14),
	DEFINE_RES_MEM(0xe61f0100, 0x38),
	DEFINE_RES_IRQ(gic_spi(69)),
};

#define r8a7791_register_thermal()					\
	platform_device_register_simple("rcar_thermal", -1,		\
					thermal_resources,		\
					ARRAY_SIZE(thermal_resources))

void __init r8a7791_add_dt_devices(void)
{
	r8a7791_register_scif(SCIFA0);
	r8a7791_register_scif(SCIFA1);
	r8a7791_register_scif(SCIFB0);
	r8a7791_register_scif(SCIFB1);
	r8a7791_register_scif(SCIFB2);
	r8a7791_register_scif(SCIFA2);
	r8a7791_register_scif(SCIF0);
	r8a7791_register_scif(SCIF1);
	r8a7791_register_scif(SCIF2);
	r8a7791_register_scif(SCIF3);
	r8a7791_register_scif(SCIF4);
	r8a7791_register_scif(SCIF5);
	r8a7791_register_scif(SCIFA3);
	r8a7791_register_scif(SCIFA4);
	r8a7791_register_scif(SCIFA5);
	r8a7791_register_cmt(00);
}

void __init r8a7791_add_standard_devices(void)
{
	r8a7791_add_dt_devices();
	r8a7791_register_irqc(0);
	r8a7791_register_thermal();
}

void __init r8a7791_init_early(void)
{
#ifndef CONFIG_ARM_ARCH_TIMER
	shmobile_setup_delay(1300, 2, 4); /* Cortex-A15 @ 1300MHz */
#endif
}

#ifdef CONFIG_USE_OF
static const char *r8a7791_boards_compat_dt[] __initdata = {
	"renesas,r8a7791",
	NULL,
};

DT_MACHINE_START(R8A7791_DT, "Generic R8A7791 (Flattened Device Tree)")
	.smp		= smp_ops(r8a7791_smp_ops),
	.init_early	= r8a7791_init_early,
	.init_time	= rcar_gen2_timer_init,
	.dt_compat	= r8a7791_boards_compat_dt,
MACHINE_END
#endif /* CONFIG_USE_OF */
Commit	Line	Data
0d0771ab HN	1	/*
	2	* r8a7791 processor support
	3	*
	4	* Copyright (C) 2013 Renesas Electronics Corporation
	5	* Copyright (C) 2013 Renesas Solutions Corp.
	6	* Copyright (C) 2013 Magnus Damm
	7	*
	8	* This program is free software; you can redistribute it and/or modify
	9	* it under the terms of the GNU General Public License as published by
	10	* the Free Software Foundation; version 2 of the License.
	11	*
	12	* This program is distributed in the hope that it will be useful,
	13	* but WITHOUT ANY WARRANTY; without even the implied warranty of
	14	* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
	15	* GNU General Public License for more details.
	16	*
	17	* You should have received a copy of the GNU General Public License
	18	* along with this program; if not, write to the Free Software
	19	* Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
	20	*/
	21
	22	#include <linux/irq.h>
	23	#include <linux/kernel.h>
	24	#include <linux/of_platform.h>
93ff9163	25	#include <linux/platform_data/gpio-rcar.h>
454d320c	26	#include <linux/platform_data/irq-renesas-irqc.h>
e6491d08	27	#include <linux/serial_sci.h>
1bebd72a	28	#include <linux/sh_timer.h>
0d0771ab	29	#include <mach/common.h>
e6491d08	30	#include <mach/irqs.h>
0d0771ab	31	#include <mach/r8a7791.h>
cd8344f4	32	#include <mach/rcar-gen2.h>
0d0771ab HN	33	#include <asm/mach/arch.h>
0d0771ab HN	34
35040127 MD	35	static const struct resource pfc_resources[] __initconst = {
	36	DEFINE_RES_MEM(0xe6060000, 0x250),
	37	};
	38
	39	#define r8a7791_register_pfc() \
	40	platform_device_register_simple("pfc-r8a7791", -1, pfc_resources, \
	41	ARRAY_SIZE(pfc_resources))
	42
93ff9163 MD	43	#define R8A7791_GPIO(idx, base, nr) \
	44	static const struct resource r8a7791_gpio##idx##_resources[] __initconst = { \
	45	DEFINE_RES_MEM((base), 0x50), \
	46	DEFINE_RES_IRQ(gic_spi(4 + (idx))), \
	47	}; \
	48	\
	49	static const struct gpio_rcar_config \
	50	r8a7791_gpio##idx##_platform_data __initconst = { \
	51	.gpio_base = 32 * (idx), \
	52	.irq_base = 0, \
	53	.number_of_pins = (nr), \
	54	.pctl_name = "pfc-r8a7791", \
	55	.has_both_edge_trigger = 1, \
	56	}; \
	57
	58	R8A7791_GPIO(0, 0xe6050000, 32);
	59	R8A7791_GPIO(1, 0xe6051000, 32);
	60	R8A7791_GPIO(2, 0xe6052000, 32);
	61	R8A7791_GPIO(3, 0xe6053000, 32);
	62	R8A7791_GPIO(4, 0xe6054000, 32);
	63	R8A7791_GPIO(5, 0xe6055000, 32);
	64	R8A7791_GPIO(6, 0xe6055400, 32);
	65	R8A7791_GPIO(7, 0xe6055800, 26);
	66
	67	#define r8a7791_register_gpio(idx) \
	68	platform_device_register_resndata(&platform_bus, "gpio_rcar", idx, \
	69	r8a7791_gpio##idx##_resources, \
	70	ARRAY_SIZE(r8a7791_gpio##idx##_resources), \
	71	&r8a7791_gpio##idx##_platform_data, \
	72	sizeof(r8a7791_gpio##idx##_platform_data))
	73
35040127 MD	74	void __init r8a7791_pinmux_init(void)
	75	{
	76	r8a7791_register_pfc();
93ff9163 MD	77	r8a7791_register_gpio(0);
	78	r8a7791_register_gpio(1);
	79	r8a7791_register_gpio(2);
	80	r8a7791_register_gpio(3);
	81	r8a7791_register_gpio(4);
	82	r8a7791_register_gpio(5);
	83	r8a7791_register_gpio(6);
	84	r8a7791_register_gpio(7);
35040127 MD	85	}
35040127 MD	86
e6491d08 YF	87	#define SCIF_COMMON(scif_type, baseaddr, irq) \
	88	.type = scif_type, \
	89	.mapbase = baseaddr, \
	90	.flags = UPF_BOOT_AUTOCONF \| UPF_IOREMAP, \
	91	.irqs = SCIx_IRQ_MUXED(irq)
	92
	93	#define SCIFA_DATA(index, baseaddr, irq) \
	94	[index] = { \
	95	SCIF_COMMON(PORT_SCIFA, baseaddr, irq), \
	96	.scbrr_algo_id = SCBRR_ALGO_4, \
	97	.scscr = SCSCR_RE \| SCSCR_TE, \
	98	}
	99
	100	#define SCIFB_DATA(index, baseaddr, irq) \
	101	[index] = { \
	102	SCIF_COMMON(PORT_SCIFB, baseaddr, irq), \
	103	.scbrr_algo_id = SCBRR_ALGO_4, \
	104	.scscr = SCSCR_RE \| SCSCR_TE, \
	105	}
	106
	107	#define SCIF_DATA(index, baseaddr, irq) \
	108	[index] = { \
	109	SCIF_COMMON(PORT_SCIF, baseaddr, irq), \
	110	.scbrr_algo_id = SCBRR_ALGO_2, \
	111	.scscr = SCSCR_RE \| SCSCR_TE, \
	112	}
	113
	114	#define HSCIF_DATA(index, baseaddr, irq) \
	115	[index] = { \
	116	SCIF_COMMON(PORT_HSCIF, baseaddr, irq), \
	117	.scbrr_algo_id = SCBRR_ALGO_6, \
	118	.scscr = SCSCR_RE \| SCSCR_TE, \
	119	}
	120
	121	enum { SCIFA0, SCIFA1, SCIFB0, SCIFB1, SCIFB2, SCIFA2, SCIF0, SCIF1,
	122	SCIF2, SCIF3, SCIF4, SCIF5, SCIFA3, SCIFA4, SCIFA5 };
	123
	124	static const struct plat_sci_port scif[] __initconst = {
	125	SCIFA_DATA(SCIFA0, 0xe6c40000, gic_spi(144)), /* SCIFA0 */
	126	SCIFA_DATA(SCIFA1, 0xe6c50000, gic_spi(145)), /* SCIFA1 */
	127	SCIFB_DATA(SCIFB0, 0xe6c20000, gic_spi(148)), /* SCIFB0 */
	128	SCIFB_DATA(SCIFB1, 0xe6c30000, gic_spi(149)), /* SCIFB1 */
	129	SCIFB_DATA(SCIFB2, 0xe6ce0000, gic_spi(150)), /* SCIFB2 */
	130	SCIFA_DATA(SCIFA2, 0xe6c60000, gic_spi(151)), /* SCIFA2 */
	131	SCIF_DATA(SCIF0, 0xe6e60000, gic_spi(152)), /* SCIF0 */
	132	SCIF_DATA(SCIF1, 0xe6e68000, gic_spi(153)), /* SCIF1 */
	133	SCIF_DATA(SCIF2, 0xe6e58000, gic_spi(22)), /* SCIF2 */
	134	SCIF_DATA(SCIF3, 0xe6ea8000, gic_spi(23)), /* SCIF3 */
	135	SCIF_DATA(SCIF4, 0xe6ee0000, gic_spi(24)), /* SCIF4 */
	136	SCIF_DATA(SCIF5, 0xe6ee8000, gic_spi(25)), /* SCIF5 */
	137	SCIFA_DATA(SCIFA3, 0xe6c70000, gic_spi(29)), /* SCIFA3 */
	138	SCIFA_DATA(SCIFA4, 0xe6c78000, gic_spi(30)), /* SCIFA4 */
	139	SCIFA_DATA(SCIFA5, 0xe6c80000, gic_spi(31)), /* SCIFA5 */
	140	};
	141
	142	static inline void r8a7791_register_scif(int idx)
	143	{
	144	platform_device_register_data(&platform_bus, "sh-sci", idx, &scif[idx],
	145	sizeof(struct plat_sci_port));
	146	}
	147
1bebd72a MD	148	static const struct sh_timer_config cmt00_platform_data __initconst = {
	149	.name = "CMT00",
	150	.timer_bit = 0,
	151	.clockevent_rating = 80,
	152	};
	153
	154	static const struct resource cmt00_resources[] __initconst = {
	155	DEFINE_RES_MEM(0xffca0510, 0x0c),
	156	DEFINE_RES_MEM(0xffca0500, 0x04),
	157	DEFINE_RES_IRQ(gic_spi(142)), /* CMT0_0 */
	158	};
	159
	160	#define r8a7791_register_cmt(idx) \
	161	platform_device_register_resndata(&platform_bus, "sh_cmt", \
	162	idx, cmt##idx##_resources, \
	163	ARRAY_SIZE(cmt##idx##_resources), \
	164	&cmt##idx##_platform_data, \
	165	sizeof(struct sh_timer_config))
	166
454d320c MD	167	static struct renesas_irqc_config irqc0_data = {
	168	.irq_base = irq_pin(0), /* IRQ0 -> IRQ9 */
	169	};
	170
	171	static struct resource irqc0_resources[] = {
	172	DEFINE_RES_MEM(0xe61c0000, 0x200), /* IRQC Event Detector Block_0 */
	173	DEFINE_RES_IRQ(gic_spi(0)), /* IRQ0 */
	174	DEFINE_RES_IRQ(gic_spi(1)), /* IRQ1 */
	175	DEFINE_RES_IRQ(gic_spi(2)), /* IRQ2 */
	176	DEFINE_RES_IRQ(gic_spi(3)), /* IRQ3 */
	177	DEFINE_RES_IRQ(gic_spi(12)), /* IRQ4 */
	178	DEFINE_RES_IRQ(gic_spi(13)), /* IRQ5 */
	179	DEFINE_RES_IRQ(gic_spi(14)), /* IRQ6 */
	180	DEFINE_RES_IRQ(gic_spi(15)), /* IRQ7 */
	181	DEFINE_RES_IRQ(gic_spi(16)), /* IRQ8 */
	182	DEFINE_RES_IRQ(gic_spi(17)), /* IRQ9 */
	183	};
	184
	185	#define r8a7791_register_irqc(idx) \
	186	platform_device_register_resndata(&platform_bus, "renesas_irqc", \
	187	idx, irqc##idx##_resources, \
	188	ARRAY_SIZE(irqc##idx##_resources), \
	189	&irqc##idx##_data, \
	190	sizeof(struct renesas_irqc_config))
	191
887e8407 MD	192	static const struct resource thermal_resources[] __initconst = {
	193	DEFINE_RES_MEM(0xe61f0000, 0x14),
	194	DEFINE_RES_MEM(0xe61f0100, 0x38),
	195	DEFINE_RES_IRQ(gic_spi(69)),
	196	};
	197
	198	#define r8a7791_register_thermal() \
	199	platform_device_register_simple("rcar_thermal", -1, \
	200	thermal_resources, \
	201	ARRAY_SIZE(thermal_resources))
	202
e6491d08 YF	203	void __init r8a7791_add_dt_devices(void)
	204	{
	205	r8a7791_register_scif(SCIFA0);
	206	r8a7791_register_scif(SCIFA1);
	207	r8a7791_register_scif(SCIFB0);
	208	r8a7791_register_scif(SCIFB1);
	209	r8a7791_register_scif(SCIFB2);
	210	r8a7791_register_scif(SCIFA2);
	211	r8a7791_register_scif(SCIF0);
	212	r8a7791_register_scif(SCIF1);
	213	r8a7791_register_scif(SCIF2);
	214	r8a7791_register_scif(SCIF3);
	215	r8a7791_register_scif(SCIF4);
	216	r8a7791_register_scif(SCIF5);
	217	r8a7791_register_scif(SCIFA3);
	218	r8a7791_register_scif(SCIFA4);
	219	r8a7791_register_scif(SCIFA5);
1bebd72a MD	220	r8a7791_register_cmt(00);
	221	}
	222
4275881f MD	223	void __init r8a7791_add_standard_devices(void)
	224	{
	225	r8a7791_add_dt_devices();
454d320c	226	r8a7791_register_irqc(0);
887e8407	227	r8a7791_register_thermal();
4275881f MD	228	}
4275881f MD	229
1bebd72a MD	230	void __init r8a7791_init_early(void)
	231	{
	232	#ifndef CONFIG_ARM_ARCH_TIMER
	233	shmobile_setup_delay(1300, 2, 4); /* Cortex-A15 @ 1300MHz */
	234	#endif
e6491d08 YF	235	}
e6491d08 YF	236
0d0771ab HN	237	#ifdef CONFIG_USE_OF
	238	static const char *r8a7791_boards_compat_dt[] __initdata = {
	239	"renesas,r8a7791",
	240	NULL,
	241	};
	242
	243	DT_MACHINE_START(R8A7791_DT, "Generic R8A7791 (Flattened Device Tree)")
687c27b0	244	.smp = smp_ops(r8a7791_smp_ops),
1bebd72a	245	.init_early = r8a7791_init_early,
cd8344f4	246	.init_time = rcar_gen2_timer_init,
0d0771ab HN	247	.dt_compat = r8a7791_boards_compat_dt,
	248	MACHINE_END
	249	#endif /* CONFIG_USE_OF */