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Merge branch 'for-3.11-fixes' of git://git.kernel.org/pub/scm/linux/kernel/git/tj...
[deliverable/linux.git] / arch / arm / mach-shmobile / setup-sh7372.c
CommitLineData
2b7eda63
MD		 1/*
2 * sh7372 processor support
3 *
4 * Copyright (C) 2010 Magnus Damm
5 * Copyright (C) 2008 Yoshihiro Shimoda
6 *
7 * This program is free software; you can redistribute it and/or modify
8 * it under the terms of the GNU General Public License as published by
9 * the Free Software Foundation; version 2 of the License.
10 *
11 * This program is distributed in the hope that it will be useful,
12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
14 * GNU General Public License for more details.
15 *
16 * You should have received a copy of the GNU General Public License
17 * along with this program; if not, write to the Free Software
18 * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
19 */
20#include <linux/kernel.h>
21#include <linux/init.h>
22#include <linux/interrupt.h>
23#include <linux/irq.h>
24#include <linux/platform_device.h>
3b7b7055 25#include <linux/of_platform.h>
6822471e 26#include <linux/uio_driver.h>
2b7eda63
MD		 27#include <linux/delay.h>
28#include <linux/input.h>
29#include <linux/io.h>
30#include <linux/serial_sci.h>
69bf6f45 31#include <linux/sh_dma.h>
2b7eda63
MD		 32#include <linux/sh_intc.h>
33#include <linux/sh_timer.h>
111058c3 34#include <linux/pm_domain.h>
426f1af9 35#include <linux/dma-mapping.h>
3cfb8439 36#include <linux/platform_data/sh_ipmmu.h>
c317fc59 37#include <mach/dma-register.h>
2b7eda63 38#include <mach/hardware.h>
250a2723 39#include <mach/irqs.h>
69bf6f45 40#include <mach/sh7372.h>
5d7220ec
MD		 41#include <mach/common.h>
42#include <asm/mach/map.h>
2b7eda63
MD		 43#include <asm/mach-types.h>
44#include <asm/mach/arch.h>
17254bff 45#include <asm/mach/time.h>
2b7eda63 46
5d7220ec
MD		 47static struct map_desc sh7372_io_desc[] __initdata = {
48 /* create a 1:1 entity map for 0xe6xxxxxx
49 * used by CPGA, INTC and PFC.
50 */
51 {
52 .virtual = 0xe6000000,
53 .pfn = __phys_to_pfn(0xe6000000),
54 .length = 256 << 20,
55 .type = MT_DEVICE_NONSHARED
56 },
57};
58
59void __init sh7372_map_io(void)
60{
61 iotable_init(sh7372_io_desc, ARRAY_SIZE(sh7372_io_desc));
62}
2b7eda63 63
5967fe09
LP		 64/* PFC */
65static struct resource sh7372_pfc_resources[] = {
66 [0] = {
67 .start = 0xe6050000,
68 .end = 0xe6057fff,
69 .flags = IORESOURCE_MEM,
70 },
71 [1] = {
72 .start = 0xe605800c,
73 .end = 0xe6058027,
74 .flags = IORESOURCE_MEM,
75 }
76};
77
78static struct platform_device sh7372_pfc_device = {
79 .name = "pfc-sh7372",
80 .id = -1,
81 .resource = sh7372_pfc_resources,
82 .num_resources = ARRAY_SIZE(sh7372_pfc_resources),
83};
84
85void __init sh7372_pinmux_init(void)
86{
87 platform_device_register(&sh7372_pfc_device);
88}
89
33c9607a 90/* SCIFA0 */
2b7eda63
MD		 91static struct plat_sci_port scif0_platform_data = {
92 .mapbase = 0xe6c40000,
93 .flags = UPF_BOOT_AUTOCONF,
f43dc23d
PM		 94 .scscr = SCSCR_RE | SCSCR_TE,
95 .scbrr_algo_id = SCBRR_ALGO_4,
eb6e8605 96 .type = PORT_SCIFA,
33c9607a
MD		 97 .irqs = { evt2irq(0x0c00), evt2irq(0x0c00),
98 evt2irq(0x0c00), evt2irq(0x0c00) },
2b7eda63
MD		 99};
100
101static struct platform_device scif0_device = {
102 .name = "sh-sci",
103 .id = 0,
104 .dev = {
105 .platform_data = &scif0_platform_data,
106 },
107};
108
33c9607a 109/* SCIFA1 */
2b7eda63
MD		 110static struct plat_sci_port scif1_platform_data = {
111 .mapbase = 0xe6c50000,
112 .flags = UPF_BOOT_AUTOCONF,
f43dc23d
PM		 113 .scscr = SCSCR_RE | SCSCR_TE,
114 .scbrr_algo_id = SCBRR_ALGO_4,
eb6e8605 115 .type = PORT_SCIFA,
33c9607a
MD		 116 .irqs = { evt2irq(0x0c20), evt2irq(0x0c20),
117 evt2irq(0x0c20), evt2irq(0x0c20) },
2b7eda63
MD		 118};
119
120static struct platform_device scif1_device = {
121 .name = "sh-sci",
122 .id = 1,
123 .dev = {
124 .platform_data = &scif1_platform_data,
125 },
126};
127
33c9607a 128/* SCIFA2 */
2b7eda63
MD		 129static struct plat_sci_port scif2_platform_data = {
130 .mapbase = 0xe6c60000,
131 .flags = UPF_BOOT_AUTOCONF,
f43dc23d
PM		 132 .scscr = SCSCR_RE | SCSCR_TE,
133 .scbrr_algo_id = SCBRR_ALGO_4,
eb6e8605 134 .type = PORT_SCIFA,
33c9607a
MD		 135 .irqs = { evt2irq(0x0c40), evt2irq(0x0c40),
136 evt2irq(0x0c40), evt2irq(0x0c40) },
2b7eda63
MD		 137};
138
139static struct platform_device scif2_device = {
140 .name = "sh-sci",
141 .id = 2,
142 .dev = {
143 .platform_data = &scif2_platform_data,
144 },
145};
146
33c9607a 147/* SCIFA3 */
2b7eda63
MD		 148static struct plat_sci_port scif3_platform_data = {
149 .mapbase = 0xe6c70000,
150 .flags = UPF_BOOT_AUTOCONF,
f43dc23d
PM		 151 .scscr = SCSCR_RE | SCSCR_TE,
152 .scbrr_algo_id = SCBRR_ALGO_4,
eb6e8605 153 .type = PORT_SCIFA,
33c9607a
MD		 154 .irqs = { evt2irq(0x0c60), evt2irq(0x0c60),
155 evt2irq(0x0c60), evt2irq(0x0c60) },
2b7eda63
MD		 156};
157
158static struct platform_device scif3_device = {
159 .name = "sh-sci",
160 .id = 3,
161 .dev = {
162 .platform_data = &scif3_platform_data,
163 },
164};
165
33c9607a 166/* SCIFA4 */
2b7eda63
MD		 167static struct plat_sci_port scif4_platform_data = {
168 .mapbase = 0xe6c80000,
169 .flags = UPF_BOOT_AUTOCONF,
f43dc23d
PM		 170 .scscr = SCSCR_RE | SCSCR_TE,
171 .scbrr_algo_id = SCBRR_ALGO_4,
eb6e8605 172 .type = PORT_SCIFA,
33c9607a
MD		 173 .irqs = { evt2irq(0x0d20), evt2irq(0x0d20),
174 evt2irq(0x0d20), evt2irq(0x0d20) },
2b7eda63
MD		 175};
176
177static struct platform_device scif4_device = {
178 .name = "sh-sci",
179 .id = 4,
180 .dev = {
181 .platform_data = &scif4_platform_data,
182 },
183};
184
33c9607a 185/* SCIFA5 */
2b7eda63
MD		 186static struct plat_sci_port scif5_platform_data = {
187 .mapbase = 0xe6cb0000,
188 .flags = UPF_BOOT_AUTOCONF,
f43dc23d
PM		 189 .scscr = SCSCR_RE | SCSCR_TE,
190 .scbrr_algo_id = SCBRR_ALGO_4,
eb6e8605 191 .type = PORT_SCIFA,
33c9607a
MD		 192 .irqs = { evt2irq(0x0d40), evt2irq(0x0d40),
193 evt2irq(0x0d40), evt2irq(0x0d40) },
2b7eda63
MD		 194};
195
196static struct platform_device scif5_device = {
197 .name = "sh-sci",
198 .id = 5,
199 .dev = {
200 .platform_data = &scif5_platform_data,
201 },
202};
203
33c9607a 204/* SCIFB */
2b7eda63
MD		 205static struct plat_sci_port scif6_platform_data = {
206 .mapbase = 0xe6c30000,
207 .flags = UPF_BOOT_AUTOCONF,
f43dc23d
PM		 208 .scscr = SCSCR_RE | SCSCR_TE,
209 .scbrr_algo_id = SCBRR_ALGO_4,
eb6e8605 210 .type = PORT_SCIFB,
33c9607a
MD		 211 .irqs = { evt2irq(0x0d60), evt2irq(0x0d60),
212 evt2irq(0x0d60), evt2irq(0x0d60) },
2b7eda63
MD		 213};
214
215static struct platform_device scif6_device = {
216 .name = "sh-sci",
217 .id = 6,
218 .dev = {
219 .platform_data = &scif6_platform_data,
220 },
221};
222
c1909cc1 223/* CMT */
0ed61fc9
MD		 224static struct sh_timer_config cmt2_platform_data = {
225 .name = "CMT2",
226 .channel_offset = 0x40,
227 .timer_bit = 5,
2b7eda63
MD		 228 .clockevent_rating = 125,
229 .clocksource_rating = 125,
230};
231
0ed61fc9 232static struct resource cmt2_resources[] = {
2b7eda63 233 [0] = {
0ed61fc9
MD		 234 .name = "CMT2",
235 .start = 0xe6130040,
236 .end = 0xe613004b,
2b7eda63
MD		 237 .flags = IORESOURCE_MEM,
238 },
239 [1] = {
0ed61fc9 240 .start = evt2irq(0x0b80), /* CMT2 */
2b7eda63
MD		 241 .flags = IORESOURCE_IRQ,
242 },
243};
244
0ed61fc9 245static struct platform_device cmt2_device = {
2b7eda63 246 .name = "sh_cmt",
0ed61fc9 247 .id = 2,
2b7eda63 248 .dev = {
0ed61fc9 249 .platform_data = &cmt2_platform_data,
2b7eda63 250 },
0ed61fc9
MD		 251 .resource = cmt2_resources,
252 .num_resources = ARRAY_SIZE(cmt2_resources),
2b7eda63
MD		 253};
254
c6c049ec
MD		 255/* TMU */
256static struct sh_timer_config tmu00_platform_data = {
257 .name = "TMU00",
258 .channel_offset = 0x4,
259 .timer_bit = 0,
260 .clockevent_rating = 200,
261};
262
263static struct resource tmu00_resources[] = {
264 [0] = {
265 .name = "TMU00",
266 .start = 0xfff60008,
267 .end = 0xfff60013,
268 .flags = IORESOURCE_MEM,
269 },
270 [1] = {
271 .start = intcs_evt2irq(0xe80), /* TMU_TUNI0 */
272 .flags = IORESOURCE_IRQ,
273 },
274};
275
276static struct platform_device tmu00_device = {
277 .name = "sh_tmu",
278 .id = 0,
279 .dev = {
280 .platform_data = &tmu00_platform_data,
281 },
282 .resource = tmu00_resources,
283 .num_resources = ARRAY_SIZE(tmu00_resources),
284};
285
286static struct sh_timer_config tmu01_platform_data = {
287 .name = "TMU01",
288 .channel_offset = 0x10,
289 .timer_bit = 1,
290 .clocksource_rating = 200,
291};
292
293static struct resource tmu01_resources[] = {
294 [0] = {
295 .name = "TMU01",
296 .start = 0xfff60014,
297 .end = 0xfff6001f,
298 .flags = IORESOURCE_MEM,
299 },
300 [1] = {
301 .start = intcs_evt2irq(0xea0), /* TMU_TUNI1 */
302 .flags = IORESOURCE_IRQ,
303 },
304};
305
306static struct platform_device tmu01_device = {
307 .name = "sh_tmu",
308 .id = 1,
309 .dev = {
310 .platform_data = &tmu01_platform_data,
311 },
312 .resource = tmu01_resources,
313 .num_resources = ARRAY_SIZE(tmu01_resources),
314};
315
c1909cc1
KM		 316/* I2C */
317static struct resource iic0_resources[] = {
318 [0] = {
319 .name = "IIC0",
320 .start = 0xFFF20000,
321 .end = 0xFFF20425 - 1,
322 .flags = IORESOURCE_MEM,
323 },
324 [1] = {
33c9607a
MD		 325 .start = intcs_evt2irq(0xe00), /* IIC0_ALI0 */
326 .end = intcs_evt2irq(0xe60), /* IIC0_DTEI0 */
c1909cc1
KM		 327 .flags = IORESOURCE_IRQ,
328 },
329};
330
331static struct platform_device iic0_device = {
332 .name = "i2c-sh_mobile",
333 .id = 0, /* "i2c0" clock */
334 .num_resources = ARRAY_SIZE(iic0_resources),
335 .resource = iic0_resources,
336};
337
338static struct resource iic1_resources[] = {
339 [0] = {
340 .name = "IIC1",
341 .start = 0xE6C20000,
342 .end = 0xE6C20425 - 1,
343 .flags = IORESOURCE_MEM,
344 },
345 [1] = {
33c9607a
MD		 346 .start = evt2irq(0x780), /* IIC1_ALI1 */
347 .end = evt2irq(0x7e0), /* IIC1_DTEI1 */
c1909cc1
KM		 348 .flags = IORESOURCE_IRQ,
349 },
350};
351
352static struct platform_device iic1_device = {
353 .name = "i2c-sh_mobile",
354 .id = 1, /* "i2c1" clock */
355 .num_resources = ARRAY_SIZE(iic1_resources),
356 .resource = iic1_resources,
357};
358
69bf6f45 359/* DMA */
69bf6f45
GL		 360static const struct sh_dmae_slave_config sh7372_dmae_slaves[] = {
361 {
8d3e17ba
GL		 362 .slave_id = SHDMA_SLAVE_SCIF0_TX,
363 .addr = 0xe6c40020,
c317fc59 364 .chcr = CHCR_TX(XMIT_SZ_8BIT),
8d3e17ba
GL		 365 .mid_rid = 0x21,
366 }, {
367 .slave_id = SHDMA_SLAVE_SCIF0_RX,
368 .addr = 0xe6c40024,
c317fc59 369 .chcr = CHCR_RX(XMIT_SZ_8BIT),
8d3e17ba
GL		 370 .mid_rid = 0x22,
371 }, {
372 .slave_id = SHDMA_SLAVE_SCIF1_TX,
373 .addr = 0xe6c50020,
c317fc59 374 .chcr = CHCR_TX(XMIT_SZ_8BIT),
8d3e17ba
GL		 375 .mid_rid = 0x25,
376 }, {
377 .slave_id = SHDMA_SLAVE_SCIF1_RX,
378 .addr = 0xe6c50024,
c317fc59 379 .chcr = CHCR_RX(XMIT_SZ_8BIT),
8d3e17ba
GL		 380 .mid_rid = 0x26,
381 }, {
382 .slave_id = SHDMA_SLAVE_SCIF2_TX,
383 .addr = 0xe6c60020,
c317fc59 384 .chcr = CHCR_TX(XMIT_SZ_8BIT),
8d3e17ba
GL		 385 .mid_rid = 0x29,
386 }, {
387 .slave_id = SHDMA_SLAVE_SCIF2_RX,
388 .addr = 0xe6c60024,
c317fc59 389 .chcr = CHCR_RX(XMIT_SZ_8BIT),
8d3e17ba
GL		 390 .mid_rid = 0x2a,
391 }, {
392 .slave_id = SHDMA_SLAVE_SCIF3_TX,
393 .addr = 0xe6c70020,
c317fc59 394 .chcr = CHCR_TX(XMIT_SZ_8BIT),
8d3e17ba
GL		 395 .mid_rid = 0x2d,
396 }, {
397 .slave_id = SHDMA_SLAVE_SCIF3_RX,
398 .addr = 0xe6c70024,
c317fc59 399 .chcr = CHCR_RX(XMIT_SZ_8BIT),
8d3e17ba
GL		 400 .mid_rid = 0x2e,
401 }, {
402 .slave_id = SHDMA_SLAVE_SCIF4_TX,
403 .addr = 0xe6c80020,
c317fc59 404 .chcr = CHCR_TX(XMIT_SZ_8BIT),
8d3e17ba
GL		 405 .mid_rid = 0x39,
406 }, {
407 .slave_id = SHDMA_SLAVE_SCIF4_RX,
408 .addr = 0xe6c80024,
c317fc59 409 .chcr = CHCR_RX(XMIT_SZ_8BIT),
8d3e17ba
GL		 410 .mid_rid = 0x3a,
411 }, {
412 .slave_id = SHDMA_SLAVE_SCIF5_TX,
413 .addr = 0xe6cb0020,
c317fc59 414 .chcr = CHCR_TX(XMIT_SZ_8BIT),
8d3e17ba
GL		 415 .mid_rid = 0x35,
416 }, {
417 .slave_id = SHDMA_SLAVE_SCIF5_RX,
418 .addr = 0xe6cb0024,
c317fc59 419 .chcr = CHCR_RX(XMIT_SZ_8BIT),
8d3e17ba
GL		 420 .mid_rid = 0x36,
421 }, {
422 .slave_id = SHDMA_SLAVE_SCIF6_TX,
423 .addr = 0xe6c30040,
c317fc59 424 .chcr = CHCR_TX(XMIT_SZ_8BIT),
8d3e17ba
GL		 425 .mid_rid = 0x3d,
426 }, {
427 .slave_id = SHDMA_SLAVE_SCIF6_RX,
428 .addr = 0xe6c30060,
c317fc59 429 .chcr = CHCR_RX(XMIT_SZ_8BIT),
8d3e17ba 430 .mid_rid = 0x3e,
40eaed7f
BH		 431 }, {
432 .slave_id = SHDMA_SLAVE_FLCTL0_TX,
433 .addr = 0xe6a30050,
434 .chcr = CHCR_TX(XMIT_SZ_32BIT),
435 .mid_rid = 0x83,
436 }, {
437 .slave_id = SHDMA_SLAVE_FLCTL0_RX,
438 .addr = 0xe6a30050,
439 .chcr = CHCR_RX(XMIT_SZ_32BIT),
440 .mid_rid = 0x83,
441 }, {
442 .slave_id = SHDMA_SLAVE_FLCTL1_TX,
443 .addr = 0xe6a30060,
444 .chcr = CHCR_TX(XMIT_SZ_32BIT),
445 .mid_rid = 0x87,
446 }, {
447 .slave_id = SHDMA_SLAVE_FLCTL1_RX,
448 .addr = 0xe6a30060,
449 .chcr = CHCR_RX(XMIT_SZ_32BIT),
450 .mid_rid = 0x87,
8d3e17ba 451 }, {
69bf6f45
GL		 452 .slave_id = SHDMA_SLAVE_SDHI0_TX,
453 .addr = 0xe6850030,
c317fc59 454 .chcr = CHCR_TX(XMIT_SZ_16BIT),
69bf6f45
GL		 455 .mid_rid = 0xc1,
456 }, {
457 .slave_id = SHDMA_SLAVE_SDHI0_RX,
458 .addr = 0xe6850030,
c317fc59 459 .chcr = CHCR_RX(XMIT_SZ_16BIT),
69bf6f45
GL		 460 .mid_rid = 0xc2,
461 }, {
462 .slave_id = SHDMA_SLAVE_SDHI1_TX,
463 .addr = 0xe6860030,
c317fc59 464 .chcr = CHCR_TX(XMIT_SZ_16BIT),
69bf6f45
GL		 465 .mid_rid = 0xc9,
466 }, {
467 .slave_id = SHDMA_SLAVE_SDHI1_RX,
468 .addr = 0xe6860030,
c317fc59 469 .chcr = CHCR_RX(XMIT_SZ_16BIT),
69bf6f45
GL		 470 .mid_rid = 0xca,
471 }, {
472 .slave_id = SHDMA_SLAVE_SDHI2_TX,
473 .addr = 0xe6870030,
c317fc59 474 .chcr = CHCR_TX(XMIT_SZ_16BIT),
69bf6f45
GL		 475 .mid_rid = 0xcd,
476 }, {
477 .slave_id = SHDMA_SLAVE_SDHI2_RX,
478 .addr = 0xe6870030,
c317fc59 479 .chcr = CHCR_RX(XMIT_SZ_16BIT),
69bf6f45 480 .mid_rid = 0xce,
880452b6
KM		 481 }, {
482 .slave_id = SHDMA_SLAVE_FSIA_TX,
483 .addr = 0xfe1f0024,
c317fc59 484 .chcr = CHCR_TX(XMIT_SZ_32BIT),
880452b6
KM		 485 .mid_rid = 0xb1,
486 }, {
487 .slave_id = SHDMA_SLAVE_FSIA_RX,
488 .addr = 0xfe1f0020,
c317fc59 489 .chcr = CHCR_RX(XMIT_SZ_32BIT),
880452b6 490 .mid_rid = 0xb2,
6d11dc14
GL		 491 }, {
492 .slave_id = SHDMA_SLAVE_MMCIF_TX,
493 .addr = 0xe6bd0034,
c317fc59 494 .chcr = CHCR_TX(XMIT_SZ_32BIT),
6d11dc14
GL		 495 .mid_rid = 0xd1,
496 }, {
497 .slave_id = SHDMA_SLAVE_MMCIF_RX,
498 .addr = 0xe6bd0034,
c317fc59 499 .chcr = CHCR_RX(XMIT_SZ_32BIT),
6d11dc14 500 .mid_rid = 0xd2,
69bf6f45
GL		 501 },
502};
503
4d6344f3 504#define SH7372_CHCLR (0x220 - 0x20)
e08b881a 505
69bf6f45
GL		 506static const struct sh_dmae_channel sh7372_dmae_channels[] = {
507 {
508 .offset = 0,
509 .dmars = 0,
510 .dmars_bit = 0,
e08b881a 511 .chclr_offset = SH7372_CHCLR + 0,
69bf6f45
GL		 512 }, {
513 .offset = 0x10,
514 .dmars = 0,
515 .dmars_bit = 8,
e08b881a 516 .chclr_offset = SH7372_CHCLR + 0x10,
69bf6f45
GL		 517 }, {
518 .offset = 0x20,
519 .dmars = 4,
520 .dmars_bit = 0,
e08b881a 521 .chclr_offset = SH7372_CHCLR + 0x20,
69bf6f45
GL		 522 }, {
523 .offset = 0x30,
524 .dmars = 4,
525 .dmars_bit = 8,
e08b881a 526 .chclr_offset = SH7372_CHCLR + 0x30,
69bf6f45
GL		 527 }, {
528 .offset = 0x50,
529 .dmars = 8,
530 .dmars_bit = 0,
e08b881a 531 .chclr_offset = SH7372_CHCLR + 0x50,
69bf6f45
GL		 532 }, {
533 .offset = 0x60,
534 .dmars = 8,
535 .dmars_bit = 8,
e08b881a 536 .chclr_offset = SH7372_CHCLR + 0x60,
69bf6f45
GL		 537 }
538};
539
69bf6f45
GL		 540static struct sh_dmae_pdata dma_platform_data = {
541 .slave = sh7372_dmae_slaves,
542 .slave_num = ARRAY_SIZE(sh7372_dmae_slaves),
543 .channel = sh7372_dmae_channels,
544 .channel_num = ARRAY_SIZE(sh7372_dmae_channels),
c317fc59
KM		 545 .ts_low_shift = TS_LOW_SHIFT,
546 .ts_low_mask = TS_LOW_BIT << TS_LOW_SHIFT,
547 .ts_high_shift = TS_HI_SHIFT,
548 .ts_high_mask = TS_HI_BIT << TS_HI_SHIFT,
549 .ts_shift = dma_ts_shift,
550 .ts_shift_num = ARRAY_SIZE(dma_ts_shift),
69bf6f45 551 .dmaor_init = DMAOR_DME,
e08b881a 552 .chclr_present = 1,
69bf6f45
GL		 553};
554
555/* Resource order important! */
556static struct resource sh7372_dmae0_resources[] = {
557 {
558 /* Channel registers and DMAOR */
559 .start = 0xfe008020,
e08b881a 560 .end = 0xfe00828f,
69bf6f45
GL		 561 .flags = IORESOURCE_MEM,
562 },
563 {
564 /* DMARSx */
565 .start = 0xfe009000,
566 .end = 0xfe00900b,
567 .flags = IORESOURCE_MEM,
568 },
569 {
20052462 570 .name = "error_irq",
f989ae5b
MD		 571 .start = evt2irq(0x20c0),
572 .end = evt2irq(0x20c0),
69bf6f45
GL		 573 .flags = IORESOURCE_IRQ,
574 },
575 {
576 /* IRQ for channels 0-5 */
f989ae5b
MD		 577 .start = evt2irq(0x2000),
578 .end = evt2irq(0x20a0),
69bf6f45
GL		 579 .flags = IORESOURCE_IRQ,
580 },
581};
582
583/* Resource order important! */
584static struct resource sh7372_dmae1_resources[] = {
585 {
586 /* Channel registers and DMAOR */
587 .start = 0xfe018020,
e08b881a 588 .end = 0xfe01828f,
69bf6f45
GL		 589 .flags = IORESOURCE_MEM,
590 },
591 {
592 /* DMARSx */
593 .start = 0xfe019000,
594 .end = 0xfe01900b,
595 .flags = IORESOURCE_MEM,
596 },
597 {
20052462 598 .name = "error_irq",
f989ae5b
MD		 599 .start = evt2irq(0x21c0),
600 .end = evt2irq(0x21c0),
69bf6f45
GL		 601 .flags = IORESOURCE_IRQ,
602 },
603 {
604 /* IRQ for channels 0-5 */
f989ae5b
MD		 605 .start = evt2irq(0x2100),
606 .end = evt2irq(0x21a0),
69bf6f45
GL		 607 .flags = IORESOURCE_IRQ,
608 },
609};
610
611/* Resource order important! */
612static struct resource sh7372_dmae2_resources[] = {
613 {
614 /* Channel registers and DMAOR */
615 .start = 0xfe028020,
e08b881a 616 .end = 0xfe02828f,
69bf6f45
GL		 617 .flags = IORESOURCE_MEM,
618 },
619 {
620 /* DMARSx */
621 .start = 0xfe029000,
622 .end = 0xfe02900b,
623 .flags = IORESOURCE_MEM,
624 },
625 {
20052462 626 .name = "error_irq",
f989ae5b
MD		 627 .start = evt2irq(0x22c0),
628 .end = evt2irq(0x22c0),
69bf6f45
GL		 629 .flags = IORESOURCE_IRQ,
630 },
631 {
632 /* IRQ for channels 0-5 */
f989ae5b
MD		 633 .start = evt2irq(0x2200),
634 .end = evt2irq(0x22a0),
69bf6f45
GL		 635 .flags = IORESOURCE_IRQ,
636 },
637};
638
639static struct platform_device dma0_device = {
640 .name = "sh-dma-engine",
641 .id = 0,
642 .resource = sh7372_dmae0_resources,
643 .num_resources = ARRAY_SIZE(sh7372_dmae0_resources),
644 .dev = {
645 .platform_data = &dma_platform_data,
646 },
647};
648
649static struct platform_device dma1_device = {
650 .name = "sh-dma-engine",
651 .id = 1,
652 .resource = sh7372_dmae1_resources,
653 .num_resources = ARRAY_SIZE(sh7372_dmae1_resources),
654 .dev = {
655 .platform_data = &dma_platform_data,
656 },
657};
658
659static struct platform_device dma2_device = {
660 .name = "sh-dma-engine",
661 .id = 2,
662 .resource = sh7372_dmae2_resources,
663 .num_resources = ARRAY_SIZE(sh7372_dmae2_resources),
664 .dev = {
665 .platform_data = &dma_platform_data,
666 },
667};
668
afe48049
KM		 669/*
670 * USB-DMAC
671 */
afe48049
KM		 672static const struct sh_dmae_channel sh7372_usb_dmae_channels[] = {
673 {
674 .offset = 0,
675 }, {
676 .offset = 0x20,
677 },
678};
679
680/* USB DMAC0 */
681static const struct sh_dmae_slave_config sh7372_usb_dmae0_slaves[] = {
682 {
683 .slave_id = SHDMA_SLAVE_USB0_TX,
c317fc59 684 .chcr = USBTS_INDEX2VAL(USBTS_XMIT_SZ_8BYTE),
afe48049
KM		 685 }, {
686 .slave_id = SHDMA_SLAVE_USB0_RX,
c317fc59 687 .chcr = USBTS_INDEX2VAL(USBTS_XMIT_SZ_8BYTE),
afe48049
KM		 688 },
689};
690
691static struct sh_dmae_pdata usb_dma0_platform_data = {
692 .slave = sh7372_usb_dmae0_slaves,
693 .slave_num = ARRAY_SIZE(sh7372_usb_dmae0_slaves),
694 .channel = sh7372_usb_dmae_channels,
695 .channel_num = ARRAY_SIZE(sh7372_usb_dmae_channels),
c317fc59
KM		 696 .ts_low_shift = USBTS_LOW_SHIFT,
697 .ts_low_mask = USBTS_LOW_BIT << USBTS_LOW_SHIFT,
698 .ts_high_shift = USBTS_HI_SHIFT,
699 .ts_high_mask = USBTS_HI_BIT << USBTS_HI_SHIFT,
700 .ts_shift = dma_usbts_shift,
701 .ts_shift_num = ARRAY_SIZE(dma_usbts_shift),
afe48049
KM		 702 .dmaor_init = DMAOR_DME,
703 .chcr_offset = 0x14,
704 .chcr_ie_bit = 1 << 5,
705 .dmaor_is_32bit = 1,
706 .needs_tend_set = 1,
707 .no_dmars = 1,
c8ddf036 708 .slave_only = 1,
afe48049
KM		 709};
710
711static struct resource sh7372_usb_dmae0_resources[] = {
712 {
713 /* Channel registers and DMAOR */
714 .start = 0xe68a0020,
715 .end = 0xe68a0064 - 1,
716 .flags = IORESOURCE_MEM,
717 },
718 {
719 /* VCR/SWR/DMICR */
720 .start = 0xe68a0000,
721 .end = 0xe68a0014 - 1,
722 .flags = IORESOURCE_MEM,
723 },
724 {
725 /* IRQ for channels */
726 .start = evt2irq(0x0a00),
727 .end = evt2irq(0x0a00),
728 .flags = IORESOURCE_IRQ,
729 },
730};
731
732static struct platform_device usb_dma0_device = {
733 .name = "sh-dma-engine",
734 .id = 3,
735 .resource = sh7372_usb_dmae0_resources,
736 .num_resources = ARRAY_SIZE(sh7372_usb_dmae0_resources),
737 .dev = {
738 .platform_data = &usb_dma0_platform_data,
739 },
740};
741
742/* USB DMAC1 */
743static const struct sh_dmae_slave_config sh7372_usb_dmae1_slaves[] = {
744 {
745 .slave_id = SHDMA_SLAVE_USB1_TX,
c317fc59 746 .chcr = USBTS_INDEX2VAL(USBTS_XMIT_SZ_8BYTE),
afe48049
KM		 747 }, {
748 .slave_id = SHDMA_SLAVE_USB1_RX,
c317fc59 749 .chcr = USBTS_INDEX2VAL(USBTS_XMIT_SZ_8BYTE),
afe48049
KM		 750 },
751};
752
753static struct sh_dmae_pdata usb_dma1_platform_data = {
754 .slave = sh7372_usb_dmae1_slaves,
755 .slave_num = ARRAY_SIZE(sh7372_usb_dmae1_slaves),
756 .channel = sh7372_usb_dmae_channels,
757 .channel_num = ARRAY_SIZE(sh7372_usb_dmae_channels),
c317fc59
KM		 758 .ts_low_shift = USBTS_LOW_SHIFT,
759 .ts_low_mask = USBTS_LOW_BIT << USBTS_LOW_SHIFT,
760 .ts_high_shift = USBTS_HI_SHIFT,
761 .ts_high_mask = USBTS_HI_BIT << USBTS_HI_SHIFT,
762 .ts_shift = dma_usbts_shift,
763 .ts_shift_num = ARRAY_SIZE(dma_usbts_shift),
afe48049
KM		 764 .dmaor_init = DMAOR_DME,
765 .chcr_offset = 0x14,
766 .chcr_ie_bit = 1 << 5,
767 .dmaor_is_32bit = 1,
768 .needs_tend_set = 1,
769 .no_dmars = 1,
c8ddf036 770 .slave_only = 1,
afe48049
KM		 771};
772
773static struct resource sh7372_usb_dmae1_resources[] = {
774 {
775 /* Channel registers and DMAOR */
776 .start = 0xe68c0020,
777 .end = 0xe68c0064 - 1,
778 .flags = IORESOURCE_MEM,
779 },
780 {
781 /* VCR/SWR/DMICR */
782 .start = 0xe68c0000,
783 .end = 0xe68c0014 - 1,
784 .flags = IORESOURCE_MEM,
785 },
786 {
787 /* IRQ for channels */
788 .start = evt2irq(0x1d00),
789 .end = evt2irq(0x1d00),
790 .flags = IORESOURCE_IRQ,
791 },
792};
793
794static struct platform_device usb_dma1_device = {
795 .name = "sh-dma-engine",
796 .id = 4,
797 .resource = sh7372_usb_dmae1_resources,
798 .num_resources = ARRAY_SIZE(sh7372_usb_dmae1_resources),
799 .dev = {
800 .platform_data = &usb_dma1_platform_data,
801 },
802};
803
6822471e
MD		 804/* VPU */
805static struct uio_info vpu_platform_data = {
806 .name = "VPU5HG",
807 .version = "0",
808 .irq = intcs_evt2irq(0x980),
809};
810
811static struct resource vpu_resources[] = {
812 [0] = {
813 .name = "VPU",
814 .start = 0xfe900000,
815 .end = 0xfe900157,
816 .flags = IORESOURCE_MEM,
817 },
818};
819
820static struct platform_device vpu_device = {
821 .name = "uio_pdrv_genirq",
822 .id = 0,
823 .dev = {
824 .platform_data = &vpu_platform_data,
825 },
826 .resource = vpu_resources,
827 .num_resources = ARRAY_SIZE(vpu_resources),
828};
829
830/* VEU0 */
831static struct uio_info veu0_platform_data = {
832 .name = "VEU0",
833 .version = "0",
834 .irq = intcs_evt2irq(0x700),
835};
836
837static struct resource veu0_resources[] = {
838 [0] = {
839 .name = "VEU0",
840 .start = 0xfe920000,
841 .end = 0xfe9200cb,
842 .flags = IORESOURCE_MEM,
843 },
844};
845
846static struct platform_device veu0_device = {
847 .name = "uio_pdrv_genirq",
848 .id = 1,
849 .dev = {
850 .platform_data = &veu0_platform_data,
851 },
852 .resource = veu0_resources,
853 .num_resources = ARRAY_SIZE(veu0_resources),
854};
855
856/* VEU1 */
857static struct uio_info veu1_platform_data = {
858 .name = "VEU1",
859 .version = "0",
860 .irq = intcs_evt2irq(0x720),
861};
862
863static struct resource veu1_resources[] = {
864 [0] = {
865 .name = "VEU1",
866 .start = 0xfe924000,
867 .end = 0xfe9240cb,
868 .flags = IORESOURCE_MEM,
869 },
870};
871
872static struct platform_device veu1_device = {
873 .name = "uio_pdrv_genirq",
874 .id = 2,
875 .dev = {
876 .platform_data = &veu1_platform_data,
877 },
878 .resource = veu1_resources,
879 .num_resources = ARRAY_SIZE(veu1_resources),
880};
881
882/* VEU2 */
883static struct uio_info veu2_platform_data = {
884 .name = "VEU2",
885 .version = "0",
886 .irq = intcs_evt2irq(0x740),
887};
888
889static struct resource veu2_resources[] = {
890 [0] = {
891 .name = "VEU2",
892 .start = 0xfe928000,
893 .end = 0xfe928307,
894 .flags = IORESOURCE_MEM,
895 },
896};
897
898static struct platform_device veu2_device = {
899 .name = "uio_pdrv_genirq",
900 .id = 3,
901 .dev = {
902 .platform_data = &veu2_platform_data,
903 },
904 .resource = veu2_resources,
905 .num_resources = ARRAY_SIZE(veu2_resources),
906};
907
908/* VEU3 */
909static struct uio_info veu3_platform_data = {
910 .name = "VEU3",
911 .version = "0",
912 .irq = intcs_evt2irq(0x760),
913};
914
915static struct resource veu3_resources[] = {
916 [0] = {
917 .name = "VEU3",
918 .start = 0xfe92c000,
919 .end = 0xfe92c307,
920 .flags = IORESOURCE_MEM,
921 },
922};
923
924static struct platform_device veu3_device = {
925 .name = "uio_pdrv_genirq",
926 .id = 4,
927 .dev = {
928 .platform_data = &veu3_platform_data,
929 },
930 .resource = veu3_resources,
931 .num_resources = ARRAY_SIZE(veu3_resources),
932};
933
934/* JPU */
935static struct uio_info jpu_platform_data = {
936 .name = "JPU",
937 .version = "0",
938 .irq = intcs_evt2irq(0x560),
939};
940
941static struct resource jpu_resources[] = {
942 [0] = {
943 .name = "JPU",
944 .start = 0xfe980000,
945 .end = 0xfe9902d3,
946 .flags = IORESOURCE_MEM,
947 },
948};
949
950static struct platform_device jpu_device = {
951 .name = "uio_pdrv_genirq",
952 .id = 5,
953 .dev = {
954 .platform_data = &jpu_platform_data,
955 },
956 .resource = jpu_resources,
957 .num_resources = ARRAY_SIZE(jpu_resources),
958};
959
960/* SPU2DSP0 */
961static struct uio_info spu0_platform_data = {
962 .name = "SPU2DSP0",
963 .version = "0",
964 .irq = evt2irq(0x1800),
965};
966
967static struct resource spu0_resources[] = {
968 [0] = {
969 .name = "SPU2DSP0",
970 .start = 0xfe200000,
971 .end = 0xfe2fffff,
972 .flags = IORESOURCE_MEM,
973 },
974};
975
976static struct platform_device spu0_device = {
977 .name = "uio_pdrv_genirq",
978 .id = 6,
979 .dev = {
980 .platform_data = &spu0_platform_data,
981 },
982 .resource = spu0_resources,
983 .num_resources = ARRAY_SIZE(spu0_resources),
984};
985
986/* SPU2DSP1 */
987static struct uio_info spu1_platform_data = {
988 .name = "SPU2DSP1",
989 .version = "0",
990 .irq = evt2irq(0x1820),
991};
992
993static struct resource spu1_resources[] = {
994 [0] = {
995 .name = "SPU2DSP1",
996 .start = 0xfe300000,
997 .end = 0xfe3fffff,
998 .flags = IORESOURCE_MEM,
999 },
1000};
1001
1002static struct platform_device spu1_device = {
1003 .name = "uio_pdrv_genirq",
1004 .id = 7,
1005 .dev = {
1006 .platform_data = &spu1_platform_data,
1007 },
1008 .resource = spu1_resources,
1009 .num_resources = ARRAY_SIZE(spu1_resources),
1010};
1011
3cfb8439
HE		 1012/* IPMMUI (an IPMMU module for ICB/LMB) */
1013static struct resource ipmmu_resources[] = {
1014 [0] = {
1015 .name = "IPMMUI",
1016 .start = 0xfe951000,
1017 .end = 0xfe9510ff,
1018 .flags = IORESOURCE_MEM,
1019 },
1020};
1021
1022static const char * const ipmmu_dev_names[] = {
1023 "sh_mobile_lcdc_fb.0",
1024 "sh_mobile_lcdc_fb.1",
1025 "sh_mobile_ceu.0",
1026 "uio_pdrv_genirq.0",
1027 "uio_pdrv_genirq.1",
1028 "uio_pdrv_genirq.2",
1029 "uio_pdrv_genirq.3",
1030 "uio_pdrv_genirq.4",
1031 "uio_pdrv_genirq.5",
1032};
1033
1034static struct shmobile_ipmmu_platform_data ipmmu_platform_data = {
1035 .dev_names = ipmmu_dev_names,
1036 .num_dev_names = ARRAY_SIZE(ipmmu_dev_names),
1037};
1038
1039static struct platform_device ipmmu_device = {
1040 .name = "ipmmu",
1041 .id = -1,
1042 .dev = {
1043 .platform_data = &ipmmu_platform_data,
1044 },
1045 .resource = ipmmu_resources,
1046 .num_resources = ARRAY_SIZE(ipmmu_resources),
1047};
1048
2b7eda63
MD		 1049static struct platform_device *sh7372_early_devices[] __initdata = {
1050 &scif0_device,
1051 &scif1_device,
1052 &scif2_device,
1053 &scif3_device,
1054 &scif4_device,
1055 &scif5_device,
1056 &scif6_device,
0ed61fc9 1057 &cmt2_device,
c6c049ec
MD		 1058 &tmu00_device,
1059 &tmu01_device,
3cfb8439 1060 &ipmmu_device,
934e4078
MD		 1061};
1062
1063static struct platform_device *sh7372_late_devices[] __initdata = {
c1909cc1
KM		 1064 &iic0_device,
1065 &iic1_device,
69bf6f45
GL		 1066 &dma0_device,
1067 &dma1_device,
1068 &dma2_device,
afe48049
KM		 1069 &usb_dma0_device,
1070 &usb_dma1_device,
6822471e
MD		 1071 &vpu_device,
1072 &veu0_device,
1073 &veu1_device,
1074 &veu2_device,
1075 &veu3_device,
1076 &jpu_device,
1077 &spu0_device,
1078 &spu1_device,
2b7eda63
MD		 1079};
1080
1081void __init sh7372_add_standard_devices(void)
1082{
ac18e02d
RW		 1083 struct pm_domain_device domain_devices[] = {
1084 { "A3RV", &vpu_device, },
1085 { "A4MP", &spu0_device, },
1086 { "A4MP", &spu1_device, },
1087 { "A3SP", &scif0_device, },
1088 { "A3SP", &scif1_device, },
1089 { "A3SP", &scif2_device, },
1090 { "A3SP", &scif3_device, },
1091 { "A3SP", &scif4_device, },
1092 { "A3SP", &scif5_device, },
1093 { "A3SP", &scif6_device, },
1094 { "A3SP", &iic1_device, },
1095 { "A3SP", &dma0_device, },
1096 { "A3SP", &dma1_device, },
1097 { "A3SP", &dma2_device, },
1098 { "A3SP", &usb_dma0_device, },
1099 { "A3SP", &usb_dma1_device, },
1100 { "A4R", &iic0_device, },
1101 { "A4R", &veu0_device, },
1102 { "A4R", &veu1_device, },
1103 { "A4R", &veu2_device, },
1104 { "A4R", &veu3_device, },
1105 { "A4R", &jpu_device, },
1106 { "A4R", &tmu00_device, },
1107 { "A4R", &tmu01_device, },
c37b7a7b
RW		 1108 };
1109
e7e59a4b 1110 sh7372_init_pm_domains();
f7dadb37 1111
2b7eda63
MD		 1112 platform_add_devices(sh7372_early_devices,
1113 ARRAY_SIZE(sh7372_early_devices));
934e4078
MD		 1114
1115 platform_add_devices(sh7372_late_devices,
1116 ARRAY_SIZE(sh7372_late_devices));
33afebf3 1117
ac18e02d
RW		 1118 rmobile_add_devices_to_domains(domain_devices,
1119 ARRAY_SIZE(domain_devices));
2b7eda63
MD		 1120}
1121
6bb27d73 1122void __init sh7372_earlytimer_init(void)
17254bff
MD		 1123{
1124 sh7372_clock_init();
1125 shmobile_earlytimer_init();
1126}
1127
2b7eda63
MD		 1128void __init sh7372_add_early_devices(void)
1129{
2b7eda63
MD		 1130 early_platform_add_devices(sh7372_early_devices,
1131 ARRAY_SIZE(sh7372_early_devices));
5d7220ec
MD		 1132
1133 /* setup early console here as well */
1134 shmobile_setup_console();
2b7eda63 1135}
3b7b7055
MD		 1136
1137#ifdef CONFIG_USE_OF
1138
1139void __init sh7372_add_early_devices_dt(void)
1140{
1141 shmobile_setup_delay(800, 1, 3); /* Cortex-A8 @ 800MHz */
1142
1143 early_platform_add_devices(sh7372_early_devices,
1144 ARRAY_SIZE(sh7372_early_devices));
1145
1146 /* setup early console here as well */
1147 shmobile_setup_console();
1148}
1149
1150static const struct of_dev_auxdata sh7372_auxdata_lookup[] __initconst = {
1151 { }
1152};
1153
1154void __init sh7372_add_standard_devices_dt(void)
1155{
1156 /* clocks are setup late during boot in the case of DT */
1157 sh7372_clock_init();
1158
1159 platform_add_devices(sh7372_early_devices,
1160 ARRAY_SIZE(sh7372_early_devices));
1161
1162 of_platform_populate(NULL, of_default_bus_match_table,
1163 sh7372_auxdata_lookup, NULL);
1164}
1165
1166static const char *sh7372_boards_compat_dt[] __initdata = {
1167 "renesas,sh7372",
1168 NULL,
1169};
1170
1171DT_MACHINE_START(SH7372_DT, "Generic SH7372 (Flattened Device Tree)")
1172 .map_io = sh7372_map_io,
1173 .init_early = sh7372_add_early_devices_dt,
1174 .nr_irqs = NR_IRQS_LEGACY,
1175 .init_irq = sh7372_init_irq,
1176 .handle_irq = shmobile_handle_irq_intc,
1177 .init_machine = sh7372_add_standard_devices_dt,
3b7b7055
MD		 1178 .dt_compat = sh7372_boards_compat_dt,
1179MACHINE_END
1180
1181#endif /* CONFIG_USE_OF */
Linux kernel - Deliverables
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