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ARM / mach-shmobile: Use preset_lpj with calibrate_delay()
[deliverable/linux.git] / arch / arm / mach-shmobile / setup-sh7372.c
CommitLineData
2b7eda63
MD		 1/*
2 * sh7372 processor support
3 *
4 * Copyright (C) 2010 Magnus Damm
5 * Copyright (C) 2008 Yoshihiro Shimoda
6 *
7 * This program is free software; you can redistribute it and/or modify
8 * it under the terms of the GNU General Public License as published by
9 * the Free Software Foundation; version 2 of the License.
10 *
11 * This program is distributed in the hope that it will be useful,
12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
14 * GNU General Public License for more details.
15 *
16 * You should have received a copy of the GNU General Public License
17 * along with this program; if not, write to the Free Software
18 * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
19 */
20#include <linux/kernel.h>
21#include <linux/init.h>
22#include <linux/interrupt.h>
23#include <linux/irq.h>
24#include <linux/platform_device.h>
3b7b7055 25#include <linux/of_platform.h>
6822471e 26#include <linux/uio_driver.h>
2b7eda63
MD		 27#include <linux/delay.h>
28#include <linux/input.h>
29#include <linux/io.h>
30#include <linux/serial_sci.h>
69bf6f45 31#include <linux/sh_dma.h>
2b7eda63
MD		 32#include <linux/sh_intc.h>
33#include <linux/sh_timer.h>
111058c3 34#include <linux/pm_domain.h>
426f1af9 35#include <linux/dma-mapping.h>
2b7eda63 36#include <mach/hardware.h>
250a2723 37#include <mach/irqs.h>
69bf6f45 38#include <mach/sh7372.h>
5d7220ec
MD		 39#include <mach/common.h>
40#include <asm/mach/map.h>
2b7eda63
MD		 41#include <asm/mach-types.h>
42#include <asm/mach/arch.h>
17254bff 43#include <asm/mach/time.h>
2b7eda63 44
5d7220ec
MD		 45static struct map_desc sh7372_io_desc[] __initdata = {
46 /* create a 1:1 entity map for 0xe6xxxxxx
47 * used by CPGA, INTC and PFC.
48 */
49 {
50 .virtual = 0xe6000000,
51 .pfn = __phys_to_pfn(0xe6000000),
52 .length = 256 << 20,
53 .type = MT_DEVICE_NONSHARED
54 },
55};
56
57void __init sh7372_map_io(void)
58{
59 iotable_init(sh7372_io_desc, ARRAY_SIZE(sh7372_io_desc));
426f1af9
AB		 60
61 /*
62 * DMA memory at 0xff200000 - 0xffdfffff. The default 2MB size isn't
63 * enough to allocate the frame buffer memory.
64 */
65 init_consistent_dma_size(12 << 20);
5d7220ec 66}
2b7eda63 67
33c9607a 68/* SCIFA0 */
2b7eda63
MD		 69static struct plat_sci_port scif0_platform_data = {
70 .mapbase = 0xe6c40000,
71 .flags = UPF_BOOT_AUTOCONF,
f43dc23d
PM		 72 .scscr = SCSCR_RE | SCSCR_TE,
73 .scbrr_algo_id = SCBRR_ALGO_4,
eb6e8605 74 .type = PORT_SCIFA,
33c9607a
MD		 75 .irqs = { evt2irq(0x0c00), evt2irq(0x0c00),
76 evt2irq(0x0c00), evt2irq(0x0c00) },
2b7eda63
MD		 77};
78
79static struct platform_device scif0_device = {
80 .name = "sh-sci",
81 .id = 0,
82 .dev = {
83 .platform_data = &scif0_platform_data,
84 },
85};
86
33c9607a 87/* SCIFA1 */
2b7eda63
MD		 88static struct plat_sci_port scif1_platform_data = {
89 .mapbase = 0xe6c50000,
90 .flags = UPF_BOOT_AUTOCONF,
f43dc23d
PM		 91 .scscr = SCSCR_RE | SCSCR_TE,
92 .scbrr_algo_id = SCBRR_ALGO_4,
eb6e8605 93 .type = PORT_SCIFA,
33c9607a
MD		 94 .irqs = { evt2irq(0x0c20), evt2irq(0x0c20),
95 evt2irq(0x0c20), evt2irq(0x0c20) },
2b7eda63
MD		 96};
97
98static struct platform_device scif1_device = {
99 .name = "sh-sci",
100 .id = 1,
101 .dev = {
102 .platform_data = &scif1_platform_data,
103 },
104};
105
33c9607a 106/* SCIFA2 */
2b7eda63
MD		 107static struct plat_sci_port scif2_platform_data = {
108 .mapbase = 0xe6c60000,
109 .flags = UPF_BOOT_AUTOCONF,
f43dc23d
PM		 110 .scscr = SCSCR_RE | SCSCR_TE,
111 .scbrr_algo_id = SCBRR_ALGO_4,
eb6e8605 112 .type = PORT_SCIFA,
33c9607a
MD		 113 .irqs = { evt2irq(0x0c40), evt2irq(0x0c40),
114 evt2irq(0x0c40), evt2irq(0x0c40) },
2b7eda63
MD		 115};
116
117static struct platform_device scif2_device = {
118 .name = "sh-sci",
119 .id = 2,
120 .dev = {
121 .platform_data = &scif2_platform_data,
122 },
123};
124
33c9607a 125/* SCIFA3 */
2b7eda63
MD		 126static struct plat_sci_port scif3_platform_data = {
127 .mapbase = 0xe6c70000,
128 .flags = UPF_BOOT_AUTOCONF,
f43dc23d
PM		 129 .scscr = SCSCR_RE | SCSCR_TE,
130 .scbrr_algo_id = SCBRR_ALGO_4,
eb6e8605 131 .type = PORT_SCIFA,
33c9607a
MD		 132 .irqs = { evt2irq(0x0c60), evt2irq(0x0c60),
133 evt2irq(0x0c60), evt2irq(0x0c60) },
2b7eda63
MD		 134};
135
136static struct platform_device scif3_device = {
137 .name = "sh-sci",
138 .id = 3,
139 .dev = {
140 .platform_data = &scif3_platform_data,
141 },
142};
143
33c9607a 144/* SCIFA4 */
2b7eda63
MD		 145static struct plat_sci_port scif4_platform_data = {
146 .mapbase = 0xe6c80000,
147 .flags = UPF_BOOT_AUTOCONF,
f43dc23d
PM		 148 .scscr = SCSCR_RE | SCSCR_TE,
149 .scbrr_algo_id = SCBRR_ALGO_4,
eb6e8605 150 .type = PORT_SCIFA,
33c9607a
MD		 151 .irqs = { evt2irq(0x0d20), evt2irq(0x0d20),
152 evt2irq(0x0d20), evt2irq(0x0d20) },
2b7eda63
MD		 153};
154
155static struct platform_device scif4_device = {
156 .name = "sh-sci",
157 .id = 4,
158 .dev = {
159 .platform_data = &scif4_platform_data,
160 },
161};
162
33c9607a 163/* SCIFA5 */
2b7eda63
MD		 164static struct plat_sci_port scif5_platform_data = {
165 .mapbase = 0xe6cb0000,
166 .flags = UPF_BOOT_AUTOCONF,
f43dc23d
PM		 167 .scscr = SCSCR_RE | SCSCR_TE,
168 .scbrr_algo_id = SCBRR_ALGO_4,
eb6e8605 169 .type = PORT_SCIFA,
33c9607a
MD		 170 .irqs = { evt2irq(0x0d40), evt2irq(0x0d40),
171 evt2irq(0x0d40), evt2irq(0x0d40) },
2b7eda63
MD		 172};
173
174static struct platform_device scif5_device = {
175 .name = "sh-sci",
176 .id = 5,
177 .dev = {
178 .platform_data = &scif5_platform_data,
179 },
180};
181
33c9607a 182/* SCIFB */
2b7eda63
MD		 183static struct plat_sci_port scif6_platform_data = {
184 .mapbase = 0xe6c30000,
185 .flags = UPF_BOOT_AUTOCONF,
f43dc23d
PM		 186 .scscr = SCSCR_RE | SCSCR_TE,
187 .scbrr_algo_id = SCBRR_ALGO_4,
eb6e8605 188 .type = PORT_SCIFB,
33c9607a
MD		 189 .irqs = { evt2irq(0x0d60), evt2irq(0x0d60),
190 evt2irq(0x0d60), evt2irq(0x0d60) },
2b7eda63
MD		 191};
192
193static struct platform_device scif6_device = {
194 .name = "sh-sci",
195 .id = 6,
196 .dev = {
197 .platform_data = &scif6_platform_data,
198 },
199};
200
c1909cc1 201/* CMT */
0ed61fc9
MD		 202static struct sh_timer_config cmt2_platform_data = {
203 .name = "CMT2",
204 .channel_offset = 0x40,
205 .timer_bit = 5,
2b7eda63
MD		 206 .clockevent_rating = 125,
207 .clocksource_rating = 125,
208};
209
0ed61fc9 210static struct resource cmt2_resources[] = {
2b7eda63 211 [0] = {
0ed61fc9
MD		 212 .name = "CMT2",
213 .start = 0xe6130040,
214 .end = 0xe613004b,
2b7eda63
MD		 215 .flags = IORESOURCE_MEM,
216 },
217 [1] = {
0ed61fc9 218 .start = evt2irq(0x0b80), /* CMT2 */
2b7eda63
MD		 219 .flags = IORESOURCE_IRQ,
220 },
221};
222
0ed61fc9 223static struct platform_device cmt2_device = {
2b7eda63 224 .name = "sh_cmt",
0ed61fc9 225 .id = 2,
2b7eda63 226 .dev = {
0ed61fc9 227 .platform_data = &cmt2_platform_data,
2b7eda63 228 },
0ed61fc9
MD		 229 .resource = cmt2_resources,
230 .num_resources = ARRAY_SIZE(cmt2_resources),
2b7eda63
MD		 231};
232
c6c049ec
MD		 233/* TMU */
234static struct sh_timer_config tmu00_platform_data = {
235 .name = "TMU00",
236 .channel_offset = 0x4,
237 .timer_bit = 0,
238 .clockevent_rating = 200,
239};
240
241static struct resource tmu00_resources[] = {
242 [0] = {
243 .name = "TMU00",
244 .start = 0xfff60008,
245 .end = 0xfff60013,
246 .flags = IORESOURCE_MEM,
247 },
248 [1] = {
249 .start = intcs_evt2irq(0xe80), /* TMU_TUNI0 */
250 .flags = IORESOURCE_IRQ,
251 },
252};
253
254static struct platform_device tmu00_device = {
255 .name = "sh_tmu",
256 .id = 0,
257 .dev = {
258 .platform_data = &tmu00_platform_data,
259 },
260 .resource = tmu00_resources,
261 .num_resources = ARRAY_SIZE(tmu00_resources),
262};
263
264static struct sh_timer_config tmu01_platform_data = {
265 .name = "TMU01",
266 .channel_offset = 0x10,
267 .timer_bit = 1,
268 .clocksource_rating = 200,
269};
270
271static struct resource tmu01_resources[] = {
272 [0] = {
273 .name = "TMU01",
274 .start = 0xfff60014,
275 .end = 0xfff6001f,
276 .flags = IORESOURCE_MEM,
277 },
278 [1] = {
279 .start = intcs_evt2irq(0xea0), /* TMU_TUNI1 */
280 .flags = IORESOURCE_IRQ,
281 },
282};
283
284static struct platform_device tmu01_device = {
285 .name = "sh_tmu",
286 .id = 1,
287 .dev = {
288 .platform_data = &tmu01_platform_data,
289 },
290 .resource = tmu01_resources,
291 .num_resources = ARRAY_SIZE(tmu01_resources),
292};
293
c1909cc1
KM		 294/* I2C */
295static struct resource iic0_resources[] = {
296 [0] = {
297 .name = "IIC0",
298 .start = 0xFFF20000,
299 .end = 0xFFF20425 - 1,
300 .flags = IORESOURCE_MEM,
301 },
302 [1] = {
33c9607a
MD		 303 .start = intcs_evt2irq(0xe00), /* IIC0_ALI0 */
304 .end = intcs_evt2irq(0xe60), /* IIC0_DTEI0 */
c1909cc1
KM		 305 .flags = IORESOURCE_IRQ,
306 },
307};
308
309static struct platform_device iic0_device = {
310 .name = "i2c-sh_mobile",
311 .id = 0, /* "i2c0" clock */
312 .num_resources = ARRAY_SIZE(iic0_resources),
313 .resource = iic0_resources,
314};
315
316static struct resource iic1_resources[] = {
317 [0] = {
318 .name = "IIC1",
319 .start = 0xE6C20000,
320 .end = 0xE6C20425 - 1,
321 .flags = IORESOURCE_MEM,
322 },
323 [1] = {
33c9607a
MD		 324 .start = evt2irq(0x780), /* IIC1_ALI1 */
325 .end = evt2irq(0x7e0), /* IIC1_DTEI1 */
c1909cc1
KM		 326 .flags = IORESOURCE_IRQ,
327 },
328};
329
330static struct platform_device iic1_device = {
331 .name = "i2c-sh_mobile",
332 .id = 1, /* "i2c1" clock */
333 .num_resources = ARRAY_SIZE(iic1_resources),
334 .resource = iic1_resources,
335};
336
69bf6f45
GL		 337/* DMA */
338/* Transmit sizes and respective CHCR register values */
339enum {
340 XMIT_SZ_8BIT = 0,
341 XMIT_SZ_16BIT = 1,
342 XMIT_SZ_32BIT = 2,
343 XMIT_SZ_64BIT = 7,
344 XMIT_SZ_128BIT = 3,
345 XMIT_SZ_256BIT = 4,
346 XMIT_SZ_512BIT = 5,
347};
348
349/* log2(size / 8) - used to calculate number of transfers */
350#define TS_SHIFT { \
351 [XMIT_SZ_8BIT] = 0, \
352 [XMIT_SZ_16BIT] = 1, \
353 [XMIT_SZ_32BIT] = 2, \
354 [XMIT_SZ_64BIT] = 3, \
355 [XMIT_SZ_128BIT] = 4, \
356 [XMIT_SZ_256BIT] = 5, \
357 [XMIT_SZ_512BIT] = 6, \
358}
359
360#define TS_INDEX2VAL(i) ((((i) & 3) << 3) | \
361 (((i) & 0xc) << (20 - 2)))
362
363static const struct sh_dmae_slave_config sh7372_dmae_slaves[] = {
364 {
8d3e17ba
GL		 365 .slave_id = SHDMA_SLAVE_SCIF0_TX,
366 .addr = 0xe6c40020,
367 .chcr = DM_FIX | SM_INC | 0x800 | TS_INDEX2VAL(XMIT_SZ_8BIT),
368 .mid_rid = 0x21,
369 }, {
370 .slave_id = SHDMA_SLAVE_SCIF0_RX,
371 .addr = 0xe6c40024,
372 .chcr = DM_INC | SM_FIX | 0x800 | TS_INDEX2VAL(XMIT_SZ_8BIT),
373 .mid_rid = 0x22,
374 }, {
375 .slave_id = SHDMA_SLAVE_SCIF1_TX,
376 .addr = 0xe6c50020,
377 .chcr = DM_FIX | SM_INC | 0x800 | TS_INDEX2VAL(XMIT_SZ_8BIT),
378 .mid_rid = 0x25,
379 }, {
380 .slave_id = SHDMA_SLAVE_SCIF1_RX,
381 .addr = 0xe6c50024,
382 .chcr = DM_INC | SM_FIX | 0x800 | TS_INDEX2VAL(XMIT_SZ_8BIT),
383 .mid_rid = 0x26,
384 }, {
385 .slave_id = SHDMA_SLAVE_SCIF2_TX,
386 .addr = 0xe6c60020,
387 .chcr = DM_FIX | SM_INC | 0x800 | TS_INDEX2VAL(XMIT_SZ_8BIT),
388 .mid_rid = 0x29,
389 }, {
390 .slave_id = SHDMA_SLAVE_SCIF2_RX,
391 .addr = 0xe6c60024,
392 .chcr = DM_INC | SM_FIX | 0x800 | TS_INDEX2VAL(XMIT_SZ_8BIT),
393 .mid_rid = 0x2a,
394 }, {
395 .slave_id = SHDMA_SLAVE_SCIF3_TX,
396 .addr = 0xe6c70020,
397 .chcr = DM_FIX | SM_INC | 0x800 | TS_INDEX2VAL(XMIT_SZ_8BIT),
398 .mid_rid = 0x2d,
399 }, {
400 .slave_id = SHDMA_SLAVE_SCIF3_RX,
401 .addr = 0xe6c70024,
402 .chcr = DM_INC | SM_FIX | 0x800 | TS_INDEX2VAL(XMIT_SZ_8BIT),
403 .mid_rid = 0x2e,
404 }, {
405 .slave_id = SHDMA_SLAVE_SCIF4_TX,
406 .addr = 0xe6c80020,
407 .chcr = DM_FIX | SM_INC | 0x800 | TS_INDEX2VAL(XMIT_SZ_8BIT),
408 .mid_rid = 0x39,
409 }, {
410 .slave_id = SHDMA_SLAVE_SCIF4_RX,
411 .addr = 0xe6c80024,
412 .chcr = DM_INC | SM_FIX | 0x800 | TS_INDEX2VAL(XMIT_SZ_8BIT),
413 .mid_rid = 0x3a,
414 }, {
415 .slave_id = SHDMA_SLAVE_SCIF5_TX,
416 .addr = 0xe6cb0020,
417 .chcr = DM_FIX | SM_INC | 0x800 | TS_INDEX2VAL(XMIT_SZ_8BIT),
418 .mid_rid = 0x35,
419 }, {
420 .slave_id = SHDMA_SLAVE_SCIF5_RX,
421 .addr = 0xe6cb0024,
422 .chcr = DM_INC | SM_FIX | 0x800 | TS_INDEX2VAL(XMIT_SZ_8BIT),
423 .mid_rid = 0x36,
424 }, {
425 .slave_id = SHDMA_SLAVE_SCIF6_TX,
426 .addr = 0xe6c30040,
427 .chcr = DM_FIX | SM_INC | 0x800 | TS_INDEX2VAL(XMIT_SZ_8BIT),
428 .mid_rid = 0x3d,
429 }, {
430 .slave_id = SHDMA_SLAVE_SCIF6_RX,
431 .addr = 0xe6c30060,
432 .chcr = DM_INC | SM_FIX | 0x800 | TS_INDEX2VAL(XMIT_SZ_8BIT),
433 .mid_rid = 0x3e,
434 }, {
69bf6f45
GL		 435 .slave_id = SHDMA_SLAVE_SDHI0_TX,
436 .addr = 0xe6850030,
437 .chcr = DM_FIX | SM_INC | 0x800 | TS_INDEX2VAL(XMIT_SZ_16BIT),
438 .mid_rid = 0xc1,
439 }, {
440 .slave_id = SHDMA_SLAVE_SDHI0_RX,
441 .addr = 0xe6850030,
442 .chcr = DM_INC | SM_FIX | 0x800 | TS_INDEX2VAL(XMIT_SZ_16BIT),
443 .mid_rid = 0xc2,
444 }, {
445 .slave_id = SHDMA_SLAVE_SDHI1_TX,
446 .addr = 0xe6860030,
447 .chcr = DM_FIX | SM_INC | 0x800 | TS_INDEX2VAL(XMIT_SZ_16BIT),
448 .mid_rid = 0xc9,
449 }, {
450 .slave_id = SHDMA_SLAVE_SDHI1_RX,
451 .addr = 0xe6860030,
452 .chcr = DM_INC | SM_FIX | 0x800 | TS_INDEX2VAL(XMIT_SZ_16BIT),
453 .mid_rid = 0xca,
454 }, {
455 .slave_id = SHDMA_SLAVE_SDHI2_TX,
456 .addr = 0xe6870030,
457 .chcr = DM_FIX | SM_INC | 0x800 | TS_INDEX2VAL(XMIT_SZ_16BIT),
458 .mid_rid = 0xcd,
459 }, {
460 .slave_id = SHDMA_SLAVE_SDHI2_RX,
461 .addr = 0xe6870030,
462 .chcr = DM_INC | SM_FIX | 0x800 | TS_INDEX2VAL(XMIT_SZ_16BIT),
463 .mid_rid = 0xce,
6d11dc14
GL		 464 }, {
465 .slave_id = SHDMA_SLAVE_MMCIF_TX,
466 .addr = 0xe6bd0034,
467 .chcr = DM_FIX | SM_INC | 0x800 | TS_INDEX2VAL(XMIT_SZ_32BIT),
468 .mid_rid = 0xd1,
469 }, {
470 .slave_id = SHDMA_SLAVE_MMCIF_RX,
471 .addr = 0xe6bd0034,
472 .chcr = DM_INC | SM_FIX | 0x800 | TS_INDEX2VAL(XMIT_SZ_32BIT),
473 .mid_rid = 0xd2,
69bf6f45
GL		 474 },
475};
476
e08b881a
GL		 477#define SH7372_CHCLR 0x220
478
69bf6f45
GL		 479static const struct sh_dmae_channel sh7372_dmae_channels[] = {
480 {
481 .offset = 0,
482 .dmars = 0,
483 .dmars_bit = 0,
e08b881a 484 .chclr_offset = SH7372_CHCLR + 0,
69bf6f45
GL		 485 }, {
486 .offset = 0x10,
487 .dmars = 0,
488 .dmars_bit = 8,
e08b881a 489 .chclr_offset = SH7372_CHCLR + 0x10,
69bf6f45
GL		 490 }, {
491 .offset = 0x20,
492 .dmars = 4,
493 .dmars_bit = 0,
e08b881a 494 .chclr_offset = SH7372_CHCLR + 0x20,
69bf6f45
GL		 495 }, {
496 .offset = 0x30,
497 .dmars = 4,
498 .dmars_bit = 8,
e08b881a 499 .chclr_offset = SH7372_CHCLR + 0x30,
69bf6f45
GL		 500 }, {
501 .offset = 0x50,
502 .dmars = 8,
503 .dmars_bit = 0,
e08b881a 504 .chclr_offset = SH7372_CHCLR + 0x50,
69bf6f45
GL		 505 }, {
506 .offset = 0x60,
507 .dmars = 8,
508 .dmars_bit = 8,
e08b881a 509 .chclr_offset = SH7372_CHCLR + 0x60,
69bf6f45
GL		 510 }
511};
512
513static const unsigned int ts_shift[] = TS_SHIFT;
514
515static struct sh_dmae_pdata dma_platform_data = {
516 .slave = sh7372_dmae_slaves,
517 .slave_num = ARRAY_SIZE(sh7372_dmae_slaves),
518 .channel = sh7372_dmae_channels,
519 .channel_num = ARRAY_SIZE(sh7372_dmae_channels),
520 .ts_low_shift = 3,
521 .ts_low_mask = 0x18,
522 .ts_high_shift = (20 - 2), /* 2 bits for shifted low TS */
523 .ts_high_mask = 0x00300000,
524 .ts_shift = ts_shift,
525 .ts_shift_num = ARRAY_SIZE(ts_shift),
526 .dmaor_init = DMAOR_DME,
e08b881a 527 .chclr_present = 1,
69bf6f45
GL		 528};
529
530/* Resource order important! */
531static struct resource sh7372_dmae0_resources[] = {
532 {
533 /* Channel registers and DMAOR */
534 .start = 0xfe008020,
e08b881a 535 .end = 0xfe00828f,
69bf6f45
GL		 536 .flags = IORESOURCE_MEM,
537 },
538 {
539 /* DMARSx */
540 .start = 0xfe009000,
541 .end = 0xfe00900b,
542 .flags = IORESOURCE_MEM,
543 },
544 {
20052462 545 .name = "error_irq",
f989ae5b
MD		 546 .start = evt2irq(0x20c0),
547 .end = evt2irq(0x20c0),
69bf6f45
GL		 548 .flags = IORESOURCE_IRQ,
549 },
550 {
551 /* IRQ for channels 0-5 */
f989ae5b
MD		 552 .start = evt2irq(0x2000),
553 .end = evt2irq(0x20a0),
69bf6f45
GL		 554 .flags = IORESOURCE_IRQ,
555 },
556};
557
558/* Resource order important! */
559static struct resource sh7372_dmae1_resources[] = {
560 {
561 /* Channel registers and DMAOR */
562 .start = 0xfe018020,
e08b881a 563 .end = 0xfe01828f,
69bf6f45
GL		 564 .flags = IORESOURCE_MEM,
565 },
566 {
567 /* DMARSx */
568 .start = 0xfe019000,
569 .end = 0xfe01900b,
570 .flags = IORESOURCE_MEM,
571 },
572 {
20052462 573 .name = "error_irq",
f989ae5b
MD		 574 .start = evt2irq(0x21c0),
575 .end = evt2irq(0x21c0),
69bf6f45
GL		 576 .flags = IORESOURCE_IRQ,
577 },
578 {
579 /* IRQ for channels 0-5 */
f989ae5b
MD		 580 .start = evt2irq(0x2100),
581 .end = evt2irq(0x21a0),
69bf6f45
GL		 582 .flags = IORESOURCE_IRQ,
583 },
584};
585
586/* Resource order important! */
587static struct resource sh7372_dmae2_resources[] = {
588 {
589 /* Channel registers and DMAOR */
590 .start = 0xfe028020,
e08b881a 591 .end = 0xfe02828f,
69bf6f45
GL		 592 .flags = IORESOURCE_MEM,
593 },
594 {
595 /* DMARSx */
596 .start = 0xfe029000,
597 .end = 0xfe02900b,
598 .flags = IORESOURCE_MEM,
599 },
600 {
20052462 601 .name = "error_irq",
f989ae5b
MD		 602 .start = evt2irq(0x22c0),
603 .end = evt2irq(0x22c0),
69bf6f45
GL		 604 .flags = IORESOURCE_IRQ,
605 },
606 {
607 /* IRQ for channels 0-5 */
f989ae5b
MD		 608 .start = evt2irq(0x2200),
609 .end = evt2irq(0x22a0),
69bf6f45
GL		 610 .flags = IORESOURCE_IRQ,
611 },
612};
613
614static struct platform_device dma0_device = {
615 .name = "sh-dma-engine",
616 .id = 0,
617 .resource = sh7372_dmae0_resources,
618 .num_resources = ARRAY_SIZE(sh7372_dmae0_resources),
619 .dev = {
620 .platform_data = &dma_platform_data,
621 },
622};
623
624static struct platform_device dma1_device = {
625 .name = "sh-dma-engine",
626 .id = 1,
627 .resource = sh7372_dmae1_resources,
628 .num_resources = ARRAY_SIZE(sh7372_dmae1_resources),
629 .dev = {
630 .platform_data = &dma_platform_data,
631 },
632};
633
634static struct platform_device dma2_device = {
635 .name = "sh-dma-engine",
636 .id = 2,
637 .resource = sh7372_dmae2_resources,
638 .num_resources = ARRAY_SIZE(sh7372_dmae2_resources),
639 .dev = {
640 .platform_data = &dma_platform_data,
641 },
642};
643
afe48049
KM		 644/*
645 * USB-DMAC
646 */
647
648unsigned int usbts_shift[] = {3, 4, 5};
649
650enum {
651 XMIT_SZ_8BYTE = 0,
652 XMIT_SZ_16BYTE = 1,
653 XMIT_SZ_32BYTE = 2,
654};
655
656#define USBTS_INDEX2VAL(i) (((i) & 3) << 6)
657
658static const struct sh_dmae_channel sh7372_usb_dmae_channels[] = {
659 {
660 .offset = 0,
661 }, {
662 .offset = 0x20,
663 },
664};
665
666/* USB DMAC0 */
667static const struct sh_dmae_slave_config sh7372_usb_dmae0_slaves[] = {
668 {
669 .slave_id = SHDMA_SLAVE_USB0_TX,
670 .chcr = USBTS_INDEX2VAL(XMIT_SZ_8BYTE),
671 }, {
672 .slave_id = SHDMA_SLAVE_USB0_RX,
673 .chcr = USBTS_INDEX2VAL(XMIT_SZ_8BYTE),
674 },
675};
676
677static struct sh_dmae_pdata usb_dma0_platform_data = {
678 .slave = sh7372_usb_dmae0_slaves,
679 .slave_num = ARRAY_SIZE(sh7372_usb_dmae0_slaves),
680 .channel = sh7372_usb_dmae_channels,
681 .channel_num = ARRAY_SIZE(sh7372_usb_dmae_channels),
682 .ts_low_shift = 6,
683 .ts_low_mask = 0xc0,
684 .ts_high_shift = 0,
685 .ts_high_mask = 0,
686 .ts_shift = usbts_shift,
687 .ts_shift_num = ARRAY_SIZE(usbts_shift),
688 .dmaor_init = DMAOR_DME,
689 .chcr_offset = 0x14,
690 .chcr_ie_bit = 1 << 5,
691 .dmaor_is_32bit = 1,
692 .needs_tend_set = 1,
693 .no_dmars = 1,
c8ddf036 694 .slave_only = 1,
afe48049
KM		 695};
696
697static struct resource sh7372_usb_dmae0_resources[] = {
698 {
699 /* Channel registers and DMAOR */
700 .start = 0xe68a0020,
701 .end = 0xe68a0064 - 1,
702 .flags = IORESOURCE_MEM,
703 },
704 {
705 /* VCR/SWR/DMICR */
706 .start = 0xe68a0000,
707 .end = 0xe68a0014 - 1,
708 .flags = IORESOURCE_MEM,
709 },
710 {
711 /* IRQ for channels */
712 .start = evt2irq(0x0a00),
713 .end = evt2irq(0x0a00),
714 .flags = IORESOURCE_IRQ,
715 },
716};
717
718static struct platform_device usb_dma0_device = {
719 .name = "sh-dma-engine",
720 .id = 3,
721 .resource = sh7372_usb_dmae0_resources,
722 .num_resources = ARRAY_SIZE(sh7372_usb_dmae0_resources),
723 .dev = {
724 .platform_data = &usb_dma0_platform_data,
725 },
726};
727
728/* USB DMAC1 */
729static const struct sh_dmae_slave_config sh7372_usb_dmae1_slaves[] = {
730 {
731 .slave_id = SHDMA_SLAVE_USB1_TX,
732 .chcr = USBTS_INDEX2VAL(XMIT_SZ_8BYTE),
733 }, {
734 .slave_id = SHDMA_SLAVE_USB1_RX,
735 .chcr = USBTS_INDEX2VAL(XMIT_SZ_8BYTE),
736 },
737};
738
739static struct sh_dmae_pdata usb_dma1_platform_data = {
740 .slave = sh7372_usb_dmae1_slaves,
741 .slave_num = ARRAY_SIZE(sh7372_usb_dmae1_slaves),
742 .channel = sh7372_usb_dmae_channels,
743 .channel_num = ARRAY_SIZE(sh7372_usb_dmae_channels),
744 .ts_low_shift = 6,
745 .ts_low_mask = 0xc0,
746 .ts_high_shift = 0,
747 .ts_high_mask = 0,
748 .ts_shift = usbts_shift,
749 .ts_shift_num = ARRAY_SIZE(usbts_shift),
750 .dmaor_init = DMAOR_DME,
751 .chcr_offset = 0x14,
752 .chcr_ie_bit = 1 << 5,
753 .dmaor_is_32bit = 1,
754 .needs_tend_set = 1,
755 .no_dmars = 1,
c8ddf036 756 .slave_only = 1,
afe48049
KM		 757};
758
759static struct resource sh7372_usb_dmae1_resources[] = {
760 {
761 /* Channel registers and DMAOR */
762 .start = 0xe68c0020,
763 .end = 0xe68c0064 - 1,
764 .flags = IORESOURCE_MEM,
765 },
766 {
767 /* VCR/SWR/DMICR */
768 .start = 0xe68c0000,
769 .end = 0xe68c0014 - 1,
770 .flags = IORESOURCE_MEM,
771 },
772 {
773 /* IRQ for channels */
774 .start = evt2irq(0x1d00),
775 .end = evt2irq(0x1d00),
776 .flags = IORESOURCE_IRQ,
777 },
778};
779
780static struct platform_device usb_dma1_device = {
781 .name = "sh-dma-engine",
782 .id = 4,
783 .resource = sh7372_usb_dmae1_resources,
784 .num_resources = ARRAY_SIZE(sh7372_usb_dmae1_resources),
785 .dev = {
786 .platform_data = &usb_dma1_platform_data,
787 },
788};
789
6822471e
MD		 790/* VPU */
791static struct uio_info vpu_platform_data = {
792 .name = "VPU5HG",
793 .version = "0",
794 .irq = intcs_evt2irq(0x980),
795};
796
797static struct resource vpu_resources[] = {
798 [0] = {
799 .name = "VPU",
800 .start = 0xfe900000,
801 .end = 0xfe900157,
802 .flags = IORESOURCE_MEM,
803 },
804};
805
806static struct platform_device vpu_device = {
807 .name = "uio_pdrv_genirq",
808 .id = 0,
809 .dev = {
810 .platform_data = &vpu_platform_data,
811 },
812 .resource = vpu_resources,
813 .num_resources = ARRAY_SIZE(vpu_resources),
814};
815
816/* VEU0 */
817static struct uio_info veu0_platform_data = {
818 .name = "VEU0",
819 .version = "0",
820 .irq = intcs_evt2irq(0x700),
821};
822
823static struct resource veu0_resources[] = {
824 [0] = {
825 .name = "VEU0",
826 .start = 0xfe920000,
827 .end = 0xfe9200cb,
828 .flags = IORESOURCE_MEM,
829 },
830};
831
832static struct platform_device veu0_device = {
833 .name = "uio_pdrv_genirq",
834 .id = 1,
835 .dev = {
836 .platform_data = &veu0_platform_data,
837 },
838 .resource = veu0_resources,
839 .num_resources = ARRAY_SIZE(veu0_resources),
840};
841
842/* VEU1 */
843static struct uio_info veu1_platform_data = {
844 .name = "VEU1",
845 .version = "0",
846 .irq = intcs_evt2irq(0x720),
847};
848
849static struct resource veu1_resources[] = {
850 [0] = {
851 .name = "VEU1",
852 .start = 0xfe924000,
853 .end = 0xfe9240cb,
854 .flags = IORESOURCE_MEM,
855 },
856};
857
858static struct platform_device veu1_device = {
859 .name = "uio_pdrv_genirq",
860 .id = 2,
861 .dev = {
862 .platform_data = &veu1_platform_data,
863 },
864 .resource = veu1_resources,
865 .num_resources = ARRAY_SIZE(veu1_resources),
866};
867
868/* VEU2 */
869static struct uio_info veu2_platform_data = {
870 .name = "VEU2",
871 .version = "0",
872 .irq = intcs_evt2irq(0x740),
873};
874
875static struct resource veu2_resources[] = {
876 [0] = {
877 .name = "VEU2",
878 .start = 0xfe928000,
879 .end = 0xfe928307,
880 .flags = IORESOURCE_MEM,
881 },
882};
883
884static struct platform_device veu2_device = {
885 .name = "uio_pdrv_genirq",
886 .id = 3,
887 .dev = {
888 .platform_data = &veu2_platform_data,
889 },
890 .resource = veu2_resources,
891 .num_resources = ARRAY_SIZE(veu2_resources),
892};
893
894/* VEU3 */
895static struct uio_info veu3_platform_data = {
896 .name = "VEU3",
897 .version = "0",
898 .irq = intcs_evt2irq(0x760),
899};
900
901static struct resource veu3_resources[] = {
902 [0] = {
903 .name = "VEU3",
904 .start = 0xfe92c000,
905 .end = 0xfe92c307,
906 .flags = IORESOURCE_MEM,
907 },
908};
909
910static struct platform_device veu3_device = {
911 .name = "uio_pdrv_genirq",
912 .id = 4,
913 .dev = {
914 .platform_data = &veu3_platform_data,
915 },
916 .resource = veu3_resources,
917 .num_resources = ARRAY_SIZE(veu3_resources),
918};
919
920/* JPU */
921static struct uio_info jpu_platform_data = {
922 .name = "JPU",
923 .version = "0",
924 .irq = intcs_evt2irq(0x560),
925};
926
927static struct resource jpu_resources[] = {
928 [0] = {
929 .name = "JPU",
930 .start = 0xfe980000,
931 .end = 0xfe9902d3,
932 .flags = IORESOURCE_MEM,
933 },
934};
935
936static struct platform_device jpu_device = {
937 .name = "uio_pdrv_genirq",
938 .id = 5,
939 .dev = {
940 .platform_data = &jpu_platform_data,
941 },
942 .resource = jpu_resources,
943 .num_resources = ARRAY_SIZE(jpu_resources),
944};
945
946/* SPU2DSP0 */
947static struct uio_info spu0_platform_data = {
948 .name = "SPU2DSP0",
949 .version = "0",
950 .irq = evt2irq(0x1800),
951};
952
953static struct resource spu0_resources[] = {
954 [0] = {
955 .name = "SPU2DSP0",
956 .start = 0xfe200000,
957 .end = 0xfe2fffff,
958 .flags = IORESOURCE_MEM,
959 },
960};
961
962static struct platform_device spu0_device = {
963 .name = "uio_pdrv_genirq",
964 .id = 6,
965 .dev = {
966 .platform_data = &spu0_platform_data,
967 },
968 .resource = spu0_resources,
969 .num_resources = ARRAY_SIZE(spu0_resources),
970};
971
972/* SPU2DSP1 */
973static struct uio_info spu1_platform_data = {
974 .name = "SPU2DSP1",
975 .version = "0",
976 .irq = evt2irq(0x1820),
977};
978
979static struct resource spu1_resources[] = {
980 [0] = {
981 .name = "SPU2DSP1",
982 .start = 0xfe300000,
983 .end = 0xfe3fffff,
984 .flags = IORESOURCE_MEM,
985 },
986};
987
988static struct platform_device spu1_device = {
989 .name = "uio_pdrv_genirq",
990 .id = 7,
991 .dev = {
992 .platform_data = &spu1_platform_data,
993 },
994 .resource = spu1_resources,
995 .num_resources = ARRAY_SIZE(spu1_resources),
996};
997
2b7eda63
MD		 998static struct platform_device *sh7372_early_devices[] __initdata = {
999 &scif0_device,
1000 &scif1_device,
1001 &scif2_device,
1002 &scif3_device,
1003 &scif4_device,
1004 &scif5_device,
1005 &scif6_device,
0ed61fc9 1006 &cmt2_device,
c6c049ec
MD		 1007 &tmu00_device,
1008 &tmu01_device,
934e4078
MD		 1009};
1010
1011static struct platform_device *sh7372_late_devices[] __initdata = {
c1909cc1
KM		 1012 &iic0_device,
1013 &iic1_device,
69bf6f45
GL		 1014 &dma0_device,
1015 &dma1_device,
1016 &dma2_device,
afe48049
KM		 1017 &usb_dma0_device,
1018 &usb_dma1_device,
6822471e
MD		 1019 &vpu_device,
1020 &veu0_device,
1021 &veu1_device,
1022 &veu2_device,
1023 &veu3_device,
1024 &jpu_device,
1025 &spu0_device,
1026 &spu1_device,
2b7eda63
MD		 1027};
1028
1029void __init sh7372_add_standard_devices(void)
1030{
96f7934e 1031 sh7372_init_pm_domain(&sh7372_a4lc);
c1ba5bb5 1032 sh7372_init_pm_domain(&sh7372_a4mp);
d24771de 1033 sh7372_init_pm_domain(&sh7372_d4);
382414b9 1034 sh7372_init_pm_domain(&sh7372_a4r);
33afebf3 1035 sh7372_init_pm_domain(&sh7372_a3rv);
082517aa 1036 sh7372_init_pm_domain(&sh7372_a3ri);
f7dadb37 1037 sh7372_init_pm_domain(&sh7372_a4s);
d93f5cde 1038 sh7372_init_pm_domain(&sh7372_a3sp);
f7dadb37 1039 sh7372_init_pm_domain(&sh7372_a3sg);
96f7934e 1040
111058c3 1041 sh7372_pm_add_subdomain(&sh7372_a4lc, &sh7372_a3rv);
382414b9 1042 sh7372_pm_add_subdomain(&sh7372_a4r, &sh7372_a4lc);
111058c3 1043
f7dadb37
MD		 1044 sh7372_pm_add_subdomain(&sh7372_a4s, &sh7372_a3sg);
1045 sh7372_pm_add_subdomain(&sh7372_a4s, &sh7372_a3sp);
1046
2b7eda63
MD		 1047 platform_add_devices(sh7372_early_devices,
1048 ARRAY_SIZE(sh7372_early_devices));
934e4078
MD		 1049
1050 platform_add_devices(sh7372_late_devices,
1051 ARRAY_SIZE(sh7372_late_devices));
33afebf3
MD		 1052
1053 sh7372_add_device_to_domain(&sh7372_a3rv, &vpu_device);
c1ba5bb5
KM		 1054 sh7372_add_device_to_domain(&sh7372_a4mp, &spu0_device);
1055 sh7372_add_device_to_domain(&sh7372_a4mp, &spu1_device);
d93f5cde
MD		 1056 sh7372_add_device_to_domain(&sh7372_a3sp, &scif0_device);
1057 sh7372_add_device_to_domain(&sh7372_a3sp, &scif1_device);
1058 sh7372_add_device_to_domain(&sh7372_a3sp, &scif2_device);
1059 sh7372_add_device_to_domain(&sh7372_a3sp, &scif3_device);
1060 sh7372_add_device_to_domain(&sh7372_a3sp, &scif4_device);
1061 sh7372_add_device_to_domain(&sh7372_a3sp, &scif5_device);
1062 sh7372_add_device_to_domain(&sh7372_a3sp, &scif6_device);
1063 sh7372_add_device_to_domain(&sh7372_a3sp, &iic1_device);
1064 sh7372_add_device_to_domain(&sh7372_a3sp, &dma0_device);
1065 sh7372_add_device_to_domain(&sh7372_a3sp, &dma1_device);
1066 sh7372_add_device_to_domain(&sh7372_a3sp, &dma2_device);
1067 sh7372_add_device_to_domain(&sh7372_a3sp, &usb_dma0_device);
1068 sh7372_add_device_to_domain(&sh7372_a3sp, &usb_dma1_device);
382414b9
MD		 1069 sh7372_add_device_to_domain(&sh7372_a4r, &iic0_device);
1070 sh7372_add_device_to_domain(&sh7372_a4r, &veu0_device);
1071 sh7372_add_device_to_domain(&sh7372_a4r, &veu1_device);
1072 sh7372_add_device_to_domain(&sh7372_a4r, &veu2_device);
1073 sh7372_add_device_to_domain(&sh7372_a4r, &veu3_device);
1074 sh7372_add_device_to_domain(&sh7372_a4r, &jpu_device);
2ee619f9
RW		 1075 sh7372_add_device_to_domain(&sh7372_a4r, &tmu00_device);
1076 sh7372_add_device_to_domain(&sh7372_a4r, &tmu01_device);
2b7eda63
MD		 1077}
1078
17254bff
MD		 1079static void __init sh7372_earlytimer_init(void)
1080{
1081 sh7372_clock_init();
1082 shmobile_earlytimer_init();
1083}
1084
2b7eda63
MD		 1085void __init sh7372_add_early_devices(void)
1086{
2b7eda63
MD		 1087 early_platform_add_devices(sh7372_early_devices,
1088 ARRAY_SIZE(sh7372_early_devices));
5d7220ec
MD		 1089
1090 /* setup early console here as well */
1091 shmobile_setup_console();
17254bff
MD		 1092
1093 /* override timer setup with soc-specific code */
1094 shmobile_timer.init = sh7372_earlytimer_init;
2b7eda63 1095}
3b7b7055
MD		 1096
1097#ifdef CONFIG_USE_OF
1098
1099void __init sh7372_add_early_devices_dt(void)
1100{
1101 shmobile_setup_delay(800, 1, 3); /* Cortex-A8 @ 800MHz */
1102
1103 early_platform_add_devices(sh7372_early_devices,
1104 ARRAY_SIZE(sh7372_early_devices));
1105
1106 /* setup early console here as well */
1107 shmobile_setup_console();
1108}
1109
1110static const struct of_dev_auxdata sh7372_auxdata_lookup[] __initconst = {
1111 { }
1112};
1113
1114void __init sh7372_add_standard_devices_dt(void)
1115{
1116 /* clocks are setup late during boot in the case of DT */
1117 sh7372_clock_init();
1118
1119 platform_add_devices(sh7372_early_devices,
1120 ARRAY_SIZE(sh7372_early_devices));
1121
1122 of_platform_populate(NULL, of_default_bus_match_table,
1123 sh7372_auxdata_lookup, NULL);
1124}
1125
1126static const char *sh7372_boards_compat_dt[] __initdata = {
1127 "renesas,sh7372",
1128 NULL,
1129};
1130
1131DT_MACHINE_START(SH7372_DT, "Generic SH7372 (Flattened Device Tree)")
1132 .map_io = sh7372_map_io,
1133 .init_early = sh7372_add_early_devices_dt,
1134 .nr_irqs = NR_IRQS_LEGACY,
1135 .init_irq = sh7372_init_irq,
1136 .handle_irq = shmobile_handle_irq_intc,
1137 .init_machine = sh7372_add_standard_devices_dt,
1138 .timer = &shmobile_timer,
1139 .dt_compat = sh7372_boards_compat_dt,
1140MACHINE_END
1141
1142#endif /* CONFIG_USE_OF */
Linux kernel - Deliverables
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