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PM / Sleep: Mark devices involved in wakeup signaling during suspend
[deliverable/linux.git] / arch / arm / mach-shmobile / setup-sh7372.c
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2b7eda63
MD		 1/*
2 * sh7372 processor support
3 *
4 * Copyright (C) 2010 Magnus Damm
5 * Copyright (C) 2008 Yoshihiro Shimoda
6 *
7 * This program is free software; you can redistribute it and/or modify
8 * it under the terms of the GNU General Public License as published by
9 * the Free Software Foundation; version 2 of the License.
10 *
11 * This program is distributed in the hope that it will be useful,
12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
14 * GNU General Public License for more details.
15 *
16 * You should have received a copy of the GNU General Public License
17 * along with this program; if not, write to the Free Software
18 * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
19 */
20#include <linux/kernel.h>
21#include <linux/init.h>
22#include <linux/interrupt.h>
23#include <linux/irq.h>
24#include <linux/platform_device.h>
6822471e 25#include <linux/uio_driver.h>
2b7eda63
MD		 26#include <linux/delay.h>
27#include <linux/input.h>
28#include <linux/io.h>
29#include <linux/serial_sci.h>
69bf6f45 30#include <linux/sh_dma.h>
2b7eda63
MD		 31#include <linux/sh_intc.h>
32#include <linux/sh_timer.h>
111058c3 33#include <linux/pm_domain.h>
2b7eda63 34#include <mach/hardware.h>
69bf6f45 35#include <mach/sh7372.h>
2b7eda63
MD		 36#include <asm/mach-types.h>
37#include <asm/mach/arch.h>
38
33c9607a 39/* SCIFA0 */
2b7eda63
MD		 40static struct plat_sci_port scif0_platform_data = {
41 .mapbase = 0xe6c40000,
42 .flags = UPF_BOOT_AUTOCONF,
f43dc23d
PM		 43 .scscr = SCSCR_RE | SCSCR_TE,
44 .scbrr_algo_id = SCBRR_ALGO_4,
eb6e8605 45 .type = PORT_SCIFA,
33c9607a
MD		 46 .irqs = { evt2irq(0x0c00), evt2irq(0x0c00),
47 evt2irq(0x0c00), evt2irq(0x0c00) },
2b7eda63
MD		 48};
49
50static struct platform_device scif0_device = {
51 .name = "sh-sci",
52 .id = 0,
53 .dev = {
54 .platform_data = &scif0_platform_data,
55 },
56};
57
33c9607a 58/* SCIFA1 */
2b7eda63
MD		 59static struct plat_sci_port scif1_platform_data = {
60 .mapbase = 0xe6c50000,
61 .flags = UPF_BOOT_AUTOCONF,
f43dc23d
PM		 62 .scscr = SCSCR_RE | SCSCR_TE,
63 .scbrr_algo_id = SCBRR_ALGO_4,
eb6e8605 64 .type = PORT_SCIFA,
33c9607a
MD		 65 .irqs = { evt2irq(0x0c20), evt2irq(0x0c20),
66 evt2irq(0x0c20), evt2irq(0x0c20) },
2b7eda63
MD		 67};
68
69static struct platform_device scif1_device = {
70 .name = "sh-sci",
71 .id = 1,
72 .dev = {
73 .platform_data = &scif1_platform_data,
74 },
75};
76
33c9607a 77/* SCIFA2 */
2b7eda63
MD		 78static struct plat_sci_port scif2_platform_data = {
79 .mapbase = 0xe6c60000,
80 .flags = UPF_BOOT_AUTOCONF,
f43dc23d
PM		 81 .scscr = SCSCR_RE | SCSCR_TE,
82 .scbrr_algo_id = SCBRR_ALGO_4,
eb6e8605 83 .type = PORT_SCIFA,
33c9607a
MD		 84 .irqs = { evt2irq(0x0c40), evt2irq(0x0c40),
85 evt2irq(0x0c40), evt2irq(0x0c40) },
2b7eda63
MD		 86};
87
88static struct platform_device scif2_device = {
89 .name = "sh-sci",
90 .id = 2,
91 .dev = {
92 .platform_data = &scif2_platform_data,
93 },
94};
95
33c9607a 96/* SCIFA3 */
2b7eda63
MD		 97static struct plat_sci_port scif3_platform_data = {
98 .mapbase = 0xe6c70000,
99 .flags = UPF_BOOT_AUTOCONF,
f43dc23d
PM		 100 .scscr = SCSCR_RE | SCSCR_TE,
101 .scbrr_algo_id = SCBRR_ALGO_4,
eb6e8605 102 .type = PORT_SCIFA,
33c9607a
MD		 103 .irqs = { evt2irq(0x0c60), evt2irq(0x0c60),
104 evt2irq(0x0c60), evt2irq(0x0c60) },
2b7eda63
MD		 105};
106
107static struct platform_device scif3_device = {
108 .name = "sh-sci",
109 .id = 3,
110 .dev = {
111 .platform_data = &scif3_platform_data,
112 },
113};
114
33c9607a 115/* SCIFA4 */
2b7eda63
MD		 116static struct plat_sci_port scif4_platform_data = {
117 .mapbase = 0xe6c80000,
118 .flags = UPF_BOOT_AUTOCONF,
f43dc23d
PM		 119 .scscr = SCSCR_RE | SCSCR_TE,
120 .scbrr_algo_id = SCBRR_ALGO_4,
eb6e8605 121 .type = PORT_SCIFA,
33c9607a
MD		 122 .irqs = { evt2irq(0x0d20), evt2irq(0x0d20),
123 evt2irq(0x0d20), evt2irq(0x0d20) },
2b7eda63
MD		 124};
125
126static struct platform_device scif4_device = {
127 .name = "sh-sci",
128 .id = 4,
129 .dev = {
130 .platform_data = &scif4_platform_data,
131 },
132};
133
33c9607a 134/* SCIFA5 */
2b7eda63
MD		 135static struct plat_sci_port scif5_platform_data = {
136 .mapbase = 0xe6cb0000,
137 .flags = UPF_BOOT_AUTOCONF,
f43dc23d
PM		 138 .scscr = SCSCR_RE | SCSCR_TE,
139 .scbrr_algo_id = SCBRR_ALGO_4,
eb6e8605 140 .type = PORT_SCIFA,
33c9607a
MD		 141 .irqs = { evt2irq(0x0d40), evt2irq(0x0d40),
142 evt2irq(0x0d40), evt2irq(0x0d40) },
2b7eda63
MD		 143};
144
145static struct platform_device scif5_device = {
146 .name = "sh-sci",
147 .id = 5,
148 .dev = {
149 .platform_data = &scif5_platform_data,
150 },
151};
152
33c9607a 153/* SCIFB */
2b7eda63
MD		 154static struct plat_sci_port scif6_platform_data = {
155 .mapbase = 0xe6c30000,
156 .flags = UPF_BOOT_AUTOCONF,
f43dc23d
PM		 157 .scscr = SCSCR_RE | SCSCR_TE,
158 .scbrr_algo_id = SCBRR_ALGO_4,
eb6e8605 159 .type = PORT_SCIFB,
33c9607a
MD		 160 .irqs = { evt2irq(0x0d60), evt2irq(0x0d60),
161 evt2irq(0x0d60), evt2irq(0x0d60) },
2b7eda63
MD		 162};
163
164static struct platform_device scif6_device = {
165 .name = "sh-sci",
166 .id = 6,
167 .dev = {
168 .platform_data = &scif6_platform_data,
169 },
170};
171
c1909cc1 172/* CMT */
0ed61fc9
MD		 173static struct sh_timer_config cmt2_platform_data = {
174 .name = "CMT2",
175 .channel_offset = 0x40,
176 .timer_bit = 5,
2b7eda63
MD		 177 .clockevent_rating = 125,
178 .clocksource_rating = 125,
179};
180
0ed61fc9 181static struct resource cmt2_resources[] = {
2b7eda63 182 [0] = {
0ed61fc9
MD		 183 .name = "CMT2",
184 .start = 0xe6130040,
185 .end = 0xe613004b,
2b7eda63
MD		 186 .flags = IORESOURCE_MEM,
187 },
188 [1] = {
0ed61fc9 189 .start = evt2irq(0x0b80), /* CMT2 */
2b7eda63
MD		 190 .flags = IORESOURCE_IRQ,
191 },
192};
193
0ed61fc9 194static struct platform_device cmt2_device = {
2b7eda63 195 .name = "sh_cmt",
0ed61fc9 196 .id = 2,
2b7eda63 197 .dev = {
0ed61fc9 198 .platform_data = &cmt2_platform_data,
2b7eda63 199 },
0ed61fc9
MD		 200 .resource = cmt2_resources,
201 .num_resources = ARRAY_SIZE(cmt2_resources),
2b7eda63
MD		 202};
203
c6c049ec
MD		 204/* TMU */
205static struct sh_timer_config tmu00_platform_data = {
206 .name = "TMU00",
207 .channel_offset = 0x4,
208 .timer_bit = 0,
209 .clockevent_rating = 200,
210};
211
212static struct resource tmu00_resources[] = {
213 [0] = {
214 .name = "TMU00",
215 .start = 0xfff60008,
216 .end = 0xfff60013,
217 .flags = IORESOURCE_MEM,
218 },
219 [1] = {
220 .start = intcs_evt2irq(0xe80), /* TMU_TUNI0 */
221 .flags = IORESOURCE_IRQ,
222 },
223};
224
225static struct platform_device tmu00_device = {
226 .name = "sh_tmu",
227 .id = 0,
228 .dev = {
229 .platform_data = &tmu00_platform_data,
230 },
231 .resource = tmu00_resources,
232 .num_resources = ARRAY_SIZE(tmu00_resources),
233};
234
235static struct sh_timer_config tmu01_platform_data = {
236 .name = "TMU01",
237 .channel_offset = 0x10,
238 .timer_bit = 1,
239 .clocksource_rating = 200,
240};
241
242static struct resource tmu01_resources[] = {
243 [0] = {
244 .name = "TMU01",
245 .start = 0xfff60014,
246 .end = 0xfff6001f,
247 .flags = IORESOURCE_MEM,
248 },
249 [1] = {
250 .start = intcs_evt2irq(0xea0), /* TMU_TUNI1 */
251 .flags = IORESOURCE_IRQ,
252 },
253};
254
255static struct platform_device tmu01_device = {
256 .name = "sh_tmu",
257 .id = 1,
258 .dev = {
259 .platform_data = &tmu01_platform_data,
260 },
261 .resource = tmu01_resources,
262 .num_resources = ARRAY_SIZE(tmu01_resources),
263};
264
c1909cc1
KM		 265/* I2C */
266static struct resource iic0_resources[] = {
267 [0] = {
268 .name = "IIC0",
269 .start = 0xFFF20000,
270 .end = 0xFFF20425 - 1,
271 .flags = IORESOURCE_MEM,
272 },
273 [1] = {
33c9607a
MD		 274 .start = intcs_evt2irq(0xe00), /* IIC0_ALI0 */
275 .end = intcs_evt2irq(0xe60), /* IIC0_DTEI0 */
c1909cc1
KM		 276 .flags = IORESOURCE_IRQ,
277 },
278};
279
280static struct platform_device iic0_device = {
281 .name = "i2c-sh_mobile",
282 .id = 0, /* "i2c0" clock */
283 .num_resources = ARRAY_SIZE(iic0_resources),
284 .resource = iic0_resources,
285};
286
287static struct resource iic1_resources[] = {
288 [0] = {
289 .name = "IIC1",
290 .start = 0xE6C20000,
291 .end = 0xE6C20425 - 1,
292 .flags = IORESOURCE_MEM,
293 },
294 [1] = {
33c9607a
MD		 295 .start = evt2irq(0x780), /* IIC1_ALI1 */
296 .end = evt2irq(0x7e0), /* IIC1_DTEI1 */
c1909cc1
KM		 297 .flags = IORESOURCE_IRQ,
298 },
299};
300
301static struct platform_device iic1_device = {
302 .name = "i2c-sh_mobile",
303 .id = 1, /* "i2c1" clock */
304 .num_resources = ARRAY_SIZE(iic1_resources),
305 .resource = iic1_resources,
306};
307
69bf6f45
GL		 308/* DMA */
309/* Transmit sizes and respective CHCR register values */
310enum {
311 XMIT_SZ_8BIT = 0,
312 XMIT_SZ_16BIT = 1,
313 XMIT_SZ_32BIT = 2,
314 XMIT_SZ_64BIT = 7,
315 XMIT_SZ_128BIT = 3,
316 XMIT_SZ_256BIT = 4,
317 XMIT_SZ_512BIT = 5,
318};
319
320/* log2(size / 8) - used to calculate number of transfers */
321#define TS_SHIFT { \
322 [XMIT_SZ_8BIT] = 0, \
323 [XMIT_SZ_16BIT] = 1, \
324 [XMIT_SZ_32BIT] = 2, \
325 [XMIT_SZ_64BIT] = 3, \
326 [XMIT_SZ_128BIT] = 4, \
327 [XMIT_SZ_256BIT] = 5, \
328 [XMIT_SZ_512BIT] = 6, \
329}
330
331#define TS_INDEX2VAL(i) ((((i) & 3) << 3) | \
332 (((i) & 0xc) << (20 - 2)))
333
334static const struct sh_dmae_slave_config sh7372_dmae_slaves[] = {
335 {
8d3e17ba
GL		 336 .slave_id = SHDMA_SLAVE_SCIF0_TX,
337 .addr = 0xe6c40020,
338 .chcr = DM_FIX | SM_INC | 0x800 | TS_INDEX2VAL(XMIT_SZ_8BIT),
339 .mid_rid = 0x21,
340 }, {
341 .slave_id = SHDMA_SLAVE_SCIF0_RX,
342 .addr = 0xe6c40024,
343 .chcr = DM_INC | SM_FIX | 0x800 | TS_INDEX2VAL(XMIT_SZ_8BIT),
344 .mid_rid = 0x22,
345 }, {
346 .slave_id = SHDMA_SLAVE_SCIF1_TX,
347 .addr = 0xe6c50020,
348 .chcr = DM_FIX | SM_INC | 0x800 | TS_INDEX2VAL(XMIT_SZ_8BIT),
349 .mid_rid = 0x25,
350 }, {
351 .slave_id = SHDMA_SLAVE_SCIF1_RX,
352 .addr = 0xe6c50024,
353 .chcr = DM_INC | SM_FIX | 0x800 | TS_INDEX2VAL(XMIT_SZ_8BIT),
354 .mid_rid = 0x26,
355 }, {
356 .slave_id = SHDMA_SLAVE_SCIF2_TX,
357 .addr = 0xe6c60020,
358 .chcr = DM_FIX | SM_INC | 0x800 | TS_INDEX2VAL(XMIT_SZ_8BIT),
359 .mid_rid = 0x29,
360 }, {
361 .slave_id = SHDMA_SLAVE_SCIF2_RX,
362 .addr = 0xe6c60024,
363 .chcr = DM_INC | SM_FIX | 0x800 | TS_INDEX2VAL(XMIT_SZ_8BIT),
364 .mid_rid = 0x2a,
365 }, {
366 .slave_id = SHDMA_SLAVE_SCIF3_TX,
367 .addr = 0xe6c70020,
368 .chcr = DM_FIX | SM_INC | 0x800 | TS_INDEX2VAL(XMIT_SZ_8BIT),
369 .mid_rid = 0x2d,
370 }, {
371 .slave_id = SHDMA_SLAVE_SCIF3_RX,
372 .addr = 0xe6c70024,
373 .chcr = DM_INC | SM_FIX | 0x800 | TS_INDEX2VAL(XMIT_SZ_8BIT),
374 .mid_rid = 0x2e,
375 }, {
376 .slave_id = SHDMA_SLAVE_SCIF4_TX,
377 .addr = 0xe6c80020,
378 .chcr = DM_FIX | SM_INC | 0x800 | TS_INDEX2VAL(XMIT_SZ_8BIT),
379 .mid_rid = 0x39,
380 }, {
381 .slave_id = SHDMA_SLAVE_SCIF4_RX,
382 .addr = 0xe6c80024,
383 .chcr = DM_INC | SM_FIX | 0x800 | TS_INDEX2VAL(XMIT_SZ_8BIT),
384 .mid_rid = 0x3a,
385 }, {
386 .slave_id = SHDMA_SLAVE_SCIF5_TX,
387 .addr = 0xe6cb0020,
388 .chcr = DM_FIX | SM_INC | 0x800 | TS_INDEX2VAL(XMIT_SZ_8BIT),
389 .mid_rid = 0x35,
390 }, {
391 .slave_id = SHDMA_SLAVE_SCIF5_RX,
392 .addr = 0xe6cb0024,
393 .chcr = DM_INC | SM_FIX | 0x800 | TS_INDEX2VAL(XMIT_SZ_8BIT),
394 .mid_rid = 0x36,
395 }, {
396 .slave_id = SHDMA_SLAVE_SCIF6_TX,
397 .addr = 0xe6c30040,
398 .chcr = DM_FIX | SM_INC | 0x800 | TS_INDEX2VAL(XMIT_SZ_8BIT),
399 .mid_rid = 0x3d,
400 }, {
401 .slave_id = SHDMA_SLAVE_SCIF6_RX,
402 .addr = 0xe6c30060,
403 .chcr = DM_INC | SM_FIX | 0x800 | TS_INDEX2VAL(XMIT_SZ_8BIT),
404 .mid_rid = 0x3e,
405 }, {
69bf6f45
GL		 406 .slave_id = SHDMA_SLAVE_SDHI0_TX,
407 .addr = 0xe6850030,
408 .chcr = DM_FIX | SM_INC | 0x800 | TS_INDEX2VAL(XMIT_SZ_16BIT),
409 .mid_rid = 0xc1,
410 }, {
411 .slave_id = SHDMA_SLAVE_SDHI0_RX,
412 .addr = 0xe6850030,
413 .chcr = DM_INC | SM_FIX | 0x800 | TS_INDEX2VAL(XMIT_SZ_16BIT),
414 .mid_rid = 0xc2,
415 }, {
416 .slave_id = SHDMA_SLAVE_SDHI1_TX,
417 .addr = 0xe6860030,
418 .chcr = DM_FIX | SM_INC | 0x800 | TS_INDEX2VAL(XMIT_SZ_16BIT),
419 .mid_rid = 0xc9,
420 }, {
421 .slave_id = SHDMA_SLAVE_SDHI1_RX,
422 .addr = 0xe6860030,
423 .chcr = DM_INC | SM_FIX | 0x800 | TS_INDEX2VAL(XMIT_SZ_16BIT),
424 .mid_rid = 0xca,
425 }, {
426 .slave_id = SHDMA_SLAVE_SDHI2_TX,
427 .addr = 0xe6870030,
428 .chcr = DM_FIX | SM_INC | 0x800 | TS_INDEX2VAL(XMIT_SZ_16BIT),
429 .mid_rid = 0xcd,
430 }, {
431 .slave_id = SHDMA_SLAVE_SDHI2_RX,
432 .addr = 0xe6870030,
433 .chcr = DM_INC | SM_FIX | 0x800 | TS_INDEX2VAL(XMIT_SZ_16BIT),
434 .mid_rid = 0xce,
6d11dc14
GL		 435 }, {
436 .slave_id = SHDMA_SLAVE_MMCIF_TX,
437 .addr = 0xe6bd0034,
438 .chcr = DM_FIX | SM_INC | 0x800 | TS_INDEX2VAL(XMIT_SZ_32BIT),
439 .mid_rid = 0xd1,
440 }, {
441 .slave_id = SHDMA_SLAVE_MMCIF_RX,
442 .addr = 0xe6bd0034,
443 .chcr = DM_INC | SM_FIX | 0x800 | TS_INDEX2VAL(XMIT_SZ_32BIT),
444 .mid_rid = 0xd2,
69bf6f45
GL		 445 },
446};
447
448static const struct sh_dmae_channel sh7372_dmae_channels[] = {
449 {
450 .offset = 0,
451 .dmars = 0,
452 .dmars_bit = 0,
453 }, {
454 .offset = 0x10,
455 .dmars = 0,
456 .dmars_bit = 8,
457 }, {
458 .offset = 0x20,
459 .dmars = 4,
460 .dmars_bit = 0,
461 }, {
462 .offset = 0x30,
463 .dmars = 4,
464 .dmars_bit = 8,
465 }, {
466 .offset = 0x50,
467 .dmars = 8,
468 .dmars_bit = 0,
469 }, {
470 .offset = 0x60,
471 .dmars = 8,
472 .dmars_bit = 8,
473 }
474};
475
476static const unsigned int ts_shift[] = TS_SHIFT;
477
478static struct sh_dmae_pdata dma_platform_data = {
479 .slave = sh7372_dmae_slaves,
480 .slave_num = ARRAY_SIZE(sh7372_dmae_slaves),
481 .channel = sh7372_dmae_channels,
482 .channel_num = ARRAY_SIZE(sh7372_dmae_channels),
483 .ts_low_shift = 3,
484 .ts_low_mask = 0x18,
485 .ts_high_shift = (20 - 2), /* 2 bits for shifted low TS */
486 .ts_high_mask = 0x00300000,
487 .ts_shift = ts_shift,
488 .ts_shift_num = ARRAY_SIZE(ts_shift),
489 .dmaor_init = DMAOR_DME,
490};
491
492/* Resource order important! */
493static struct resource sh7372_dmae0_resources[] = {
494 {
495 /* Channel registers and DMAOR */
496 .start = 0xfe008020,
497 .end = 0xfe00808f,
498 .flags = IORESOURCE_MEM,
499 },
500 {
501 /* DMARSx */
502 .start = 0xfe009000,
503 .end = 0xfe00900b,
504 .flags = IORESOURCE_MEM,
505 },
506 {
507 /* DMA error IRQ */
f989ae5b
MD		 508 .start = evt2irq(0x20c0),
509 .end = evt2irq(0x20c0),
69bf6f45
GL		 510 .flags = IORESOURCE_IRQ,
511 },
512 {
513 /* IRQ for channels 0-5 */
f989ae5b
MD		 514 .start = evt2irq(0x2000),
515 .end = evt2irq(0x20a0),
69bf6f45
GL		 516 .flags = IORESOURCE_IRQ,
517 },
518};
519
520/* Resource order important! */
521static struct resource sh7372_dmae1_resources[] = {
522 {
523 /* Channel registers and DMAOR */
524 .start = 0xfe018020,
525 .end = 0xfe01808f,
526 .flags = IORESOURCE_MEM,
527 },
528 {
529 /* DMARSx */
530 .start = 0xfe019000,
531 .end = 0xfe01900b,
532 .flags = IORESOURCE_MEM,
533 },
534 {
535 /* DMA error IRQ */
f989ae5b
MD		 536 .start = evt2irq(0x21c0),
537 .end = evt2irq(0x21c0),
69bf6f45
GL		 538 .flags = IORESOURCE_IRQ,
539 },
540 {
541 /* IRQ for channels 0-5 */
f989ae5b
MD		 542 .start = evt2irq(0x2100),
543 .end = evt2irq(0x21a0),
69bf6f45
GL		 544 .flags = IORESOURCE_IRQ,
545 },
546};
547
548/* Resource order important! */
549static struct resource sh7372_dmae2_resources[] = {
550 {
551 /* Channel registers and DMAOR */
552 .start = 0xfe028020,
553 .end = 0xfe02808f,
554 .flags = IORESOURCE_MEM,
555 },
556 {
557 /* DMARSx */
558 .start = 0xfe029000,
559 .end = 0xfe02900b,
560 .flags = IORESOURCE_MEM,
561 },
562 {
563 /* DMA error IRQ */
f989ae5b
MD		 564 .start = evt2irq(0x22c0),
565 .end = evt2irq(0x22c0),
69bf6f45
GL		 566 .flags = IORESOURCE_IRQ,
567 },
568 {
569 /* IRQ for channels 0-5 */
f989ae5b
MD		 570 .start = evt2irq(0x2200),
571 .end = evt2irq(0x22a0),
69bf6f45
GL		 572 .flags = IORESOURCE_IRQ,
573 },
574};
575
576static struct platform_device dma0_device = {
577 .name = "sh-dma-engine",
578 .id = 0,
579 .resource = sh7372_dmae0_resources,
580 .num_resources = ARRAY_SIZE(sh7372_dmae0_resources),
581 .dev = {
582 .platform_data = &dma_platform_data,
583 },
584};
585
586static struct platform_device dma1_device = {
587 .name = "sh-dma-engine",
588 .id = 1,
589 .resource = sh7372_dmae1_resources,
590 .num_resources = ARRAY_SIZE(sh7372_dmae1_resources),
591 .dev = {
592 .platform_data = &dma_platform_data,
593 },
594};
595
596static struct platform_device dma2_device = {
597 .name = "sh-dma-engine",
598 .id = 2,
599 .resource = sh7372_dmae2_resources,
600 .num_resources = ARRAY_SIZE(sh7372_dmae2_resources),
601 .dev = {
602 .platform_data = &dma_platform_data,
603 },
604};
605
afe48049
KM		 606/*
607 * USB-DMAC
608 */
609
610unsigned int usbts_shift[] = {3, 4, 5};
611
612enum {
613 XMIT_SZ_8BYTE = 0,
614 XMIT_SZ_16BYTE = 1,
615 XMIT_SZ_32BYTE = 2,
616};
617
618#define USBTS_INDEX2VAL(i) (((i) & 3) << 6)
619
620static const struct sh_dmae_channel sh7372_usb_dmae_channels[] = {
621 {
622 .offset = 0,
623 }, {
624 .offset = 0x20,
625 },
626};
627
628/* USB DMAC0 */
629static const struct sh_dmae_slave_config sh7372_usb_dmae0_slaves[] = {
630 {
631 .slave_id = SHDMA_SLAVE_USB0_TX,
632 .chcr = USBTS_INDEX2VAL(XMIT_SZ_8BYTE),
633 }, {
634 .slave_id = SHDMA_SLAVE_USB0_RX,
635 .chcr = USBTS_INDEX2VAL(XMIT_SZ_8BYTE),
636 },
637};
638
639static struct sh_dmae_pdata usb_dma0_platform_data = {
640 .slave = sh7372_usb_dmae0_slaves,
641 .slave_num = ARRAY_SIZE(sh7372_usb_dmae0_slaves),
642 .channel = sh7372_usb_dmae_channels,
643 .channel_num = ARRAY_SIZE(sh7372_usb_dmae_channels),
644 .ts_low_shift = 6,
645 .ts_low_mask = 0xc0,
646 .ts_high_shift = 0,
647 .ts_high_mask = 0,
648 .ts_shift = usbts_shift,
649 .ts_shift_num = ARRAY_SIZE(usbts_shift),
650 .dmaor_init = DMAOR_DME,
651 .chcr_offset = 0x14,
652 .chcr_ie_bit = 1 << 5,
653 .dmaor_is_32bit = 1,
654 .needs_tend_set = 1,
655 .no_dmars = 1,
656};
657
658static struct resource sh7372_usb_dmae0_resources[] = {
659 {
660 /* Channel registers and DMAOR */
661 .start = 0xe68a0020,
662 .end = 0xe68a0064 - 1,
663 .flags = IORESOURCE_MEM,
664 },
665 {
666 /* VCR/SWR/DMICR */
667 .start = 0xe68a0000,
668 .end = 0xe68a0014 - 1,
669 .flags = IORESOURCE_MEM,
670 },
671 {
672 /* IRQ for channels */
673 .start = evt2irq(0x0a00),
674 .end = evt2irq(0x0a00),
675 .flags = IORESOURCE_IRQ,
676 },
677};
678
679static struct platform_device usb_dma0_device = {
680 .name = "sh-dma-engine",
681 .id = 3,
682 .resource = sh7372_usb_dmae0_resources,
683 .num_resources = ARRAY_SIZE(sh7372_usb_dmae0_resources),
684 .dev = {
685 .platform_data = &usb_dma0_platform_data,
686 },
687};
688
689/* USB DMAC1 */
690static const struct sh_dmae_slave_config sh7372_usb_dmae1_slaves[] = {
691 {
692 .slave_id = SHDMA_SLAVE_USB1_TX,
693 .chcr = USBTS_INDEX2VAL(XMIT_SZ_8BYTE),
694 }, {
695 .slave_id = SHDMA_SLAVE_USB1_RX,
696 .chcr = USBTS_INDEX2VAL(XMIT_SZ_8BYTE),
697 },
698};
699
700static struct sh_dmae_pdata usb_dma1_platform_data = {
701 .slave = sh7372_usb_dmae1_slaves,
702 .slave_num = ARRAY_SIZE(sh7372_usb_dmae1_slaves),
703 .channel = sh7372_usb_dmae_channels,
704 .channel_num = ARRAY_SIZE(sh7372_usb_dmae_channels),
705 .ts_low_shift = 6,
706 .ts_low_mask = 0xc0,
707 .ts_high_shift = 0,
708 .ts_high_mask = 0,
709 .ts_shift = usbts_shift,
710 .ts_shift_num = ARRAY_SIZE(usbts_shift),
711 .dmaor_init = DMAOR_DME,
712 .chcr_offset = 0x14,
713 .chcr_ie_bit = 1 << 5,
714 .dmaor_is_32bit = 1,
715 .needs_tend_set = 1,
716 .no_dmars = 1,
717};
718
719static struct resource sh7372_usb_dmae1_resources[] = {
720 {
721 /* Channel registers and DMAOR */
722 .start = 0xe68c0020,
723 .end = 0xe68c0064 - 1,
724 .flags = IORESOURCE_MEM,
725 },
726 {
727 /* VCR/SWR/DMICR */
728 .start = 0xe68c0000,
729 .end = 0xe68c0014 - 1,
730 .flags = IORESOURCE_MEM,
731 },
732 {
733 /* IRQ for channels */
734 .start = evt2irq(0x1d00),
735 .end = evt2irq(0x1d00),
736 .flags = IORESOURCE_IRQ,
737 },
738};
739
740static struct platform_device usb_dma1_device = {
741 .name = "sh-dma-engine",
742 .id = 4,
743 .resource = sh7372_usb_dmae1_resources,
744 .num_resources = ARRAY_SIZE(sh7372_usb_dmae1_resources),
745 .dev = {
746 .platform_data = &usb_dma1_platform_data,
747 },
748};
749
6822471e
MD		 750/* VPU */
751static struct uio_info vpu_platform_data = {
752 .name = "VPU5HG",
753 .version = "0",
754 .irq = intcs_evt2irq(0x980),
755};
756
757static struct resource vpu_resources[] = {
758 [0] = {
759 .name = "VPU",
760 .start = 0xfe900000,
761 .end = 0xfe900157,
762 .flags = IORESOURCE_MEM,
763 },
764};
765
766static struct platform_device vpu_device = {
767 .name = "uio_pdrv_genirq",
768 .id = 0,
769 .dev = {
770 .platform_data = &vpu_platform_data,
771 },
772 .resource = vpu_resources,
773 .num_resources = ARRAY_SIZE(vpu_resources),
774};
775
776/* VEU0 */
777static struct uio_info veu0_platform_data = {
778 .name = "VEU0",
779 .version = "0",
780 .irq = intcs_evt2irq(0x700),
781};
782
783static struct resource veu0_resources[] = {
784 [0] = {
785 .name = "VEU0",
786 .start = 0xfe920000,
787 .end = 0xfe9200cb,
788 .flags = IORESOURCE_MEM,
789 },
790};
791
792static struct platform_device veu0_device = {
793 .name = "uio_pdrv_genirq",
794 .id = 1,
795 .dev = {
796 .platform_data = &veu0_platform_data,
797 },
798 .resource = veu0_resources,
799 .num_resources = ARRAY_SIZE(veu0_resources),
800};
801
802/* VEU1 */
803static struct uio_info veu1_platform_data = {
804 .name = "VEU1",
805 .version = "0",
806 .irq = intcs_evt2irq(0x720),
807};
808
809static struct resource veu1_resources[] = {
810 [0] = {
811 .name = "VEU1",
812 .start = 0xfe924000,
813 .end = 0xfe9240cb,
814 .flags = IORESOURCE_MEM,
815 },
816};
817
818static struct platform_device veu1_device = {
819 .name = "uio_pdrv_genirq",
820 .id = 2,
821 .dev = {
822 .platform_data = &veu1_platform_data,
823 },
824 .resource = veu1_resources,
825 .num_resources = ARRAY_SIZE(veu1_resources),
826};
827
828/* VEU2 */
829static struct uio_info veu2_platform_data = {
830 .name = "VEU2",
831 .version = "0",
832 .irq = intcs_evt2irq(0x740),
833};
834
835static struct resource veu2_resources[] = {
836 [0] = {
837 .name = "VEU2",
838 .start = 0xfe928000,
839 .end = 0xfe928307,
840 .flags = IORESOURCE_MEM,
841 },
842};
843
844static struct platform_device veu2_device = {
845 .name = "uio_pdrv_genirq",
846 .id = 3,
847 .dev = {
848 .platform_data = &veu2_platform_data,
849 },
850 .resource = veu2_resources,
851 .num_resources = ARRAY_SIZE(veu2_resources),
852};
853
854/* VEU3 */
855static struct uio_info veu3_platform_data = {
856 .name = "VEU3",
857 .version = "0",
858 .irq = intcs_evt2irq(0x760),
859};
860
861static struct resource veu3_resources[] = {
862 [0] = {
863 .name = "VEU3",
864 .start = 0xfe92c000,
865 .end = 0xfe92c307,
866 .flags = IORESOURCE_MEM,
867 },
868};
869
870static struct platform_device veu3_device = {
871 .name = "uio_pdrv_genirq",
872 .id = 4,
873 .dev = {
874 .platform_data = &veu3_platform_data,
875 },
876 .resource = veu3_resources,
877 .num_resources = ARRAY_SIZE(veu3_resources),
878};
879
880/* JPU */
881static struct uio_info jpu_platform_data = {
882 .name = "JPU",
883 .version = "0",
884 .irq = intcs_evt2irq(0x560),
885};
886
887static struct resource jpu_resources[] = {
888 [0] = {
889 .name = "JPU",
890 .start = 0xfe980000,
891 .end = 0xfe9902d3,
892 .flags = IORESOURCE_MEM,
893 },
894};
895
896static struct platform_device jpu_device = {
897 .name = "uio_pdrv_genirq",
898 .id = 5,
899 .dev = {
900 .platform_data = &jpu_platform_data,
901 },
902 .resource = jpu_resources,
903 .num_resources = ARRAY_SIZE(jpu_resources),
904};
905
906/* SPU2DSP0 */
907static struct uio_info spu0_platform_data = {
908 .name = "SPU2DSP0",
909 .version = "0",
910 .irq = evt2irq(0x1800),
911};
912
913static struct resource spu0_resources[] = {
914 [0] = {
915 .name = "SPU2DSP0",
916 .start = 0xfe200000,
917 .end = 0xfe2fffff,
918 .flags = IORESOURCE_MEM,
919 },
920};
921
922static struct platform_device spu0_device = {
923 .name = "uio_pdrv_genirq",
924 .id = 6,
925 .dev = {
926 .platform_data = &spu0_platform_data,
927 },
928 .resource = spu0_resources,
929 .num_resources = ARRAY_SIZE(spu0_resources),
930};
931
932/* SPU2DSP1 */
933static struct uio_info spu1_platform_data = {
934 .name = "SPU2DSP1",
935 .version = "0",
936 .irq = evt2irq(0x1820),
937};
938
939static struct resource spu1_resources[] = {
940 [0] = {
941 .name = "SPU2DSP1",
942 .start = 0xfe300000,
943 .end = 0xfe3fffff,
944 .flags = IORESOURCE_MEM,
945 },
946};
947
948static struct platform_device spu1_device = {
949 .name = "uio_pdrv_genirq",
950 .id = 7,
951 .dev = {
952 .platform_data = &spu1_platform_data,
953 },
954 .resource = spu1_resources,
955 .num_resources = ARRAY_SIZE(spu1_resources),
956};
957
2b7eda63
MD		 958static struct platform_device *sh7372_early_devices[] __initdata = {
959 &scif0_device,
960 &scif1_device,
961 &scif2_device,
962 &scif3_device,
963 &scif4_device,
964 &scif5_device,
965 &scif6_device,
0ed61fc9 966 &cmt2_device,
c6c049ec
MD		 967 &tmu00_device,
968 &tmu01_device,
934e4078
MD		 969};
970
971static struct platform_device *sh7372_late_devices[] __initdata = {
c1909cc1
KM		 972 &iic0_device,
973 &iic1_device,
69bf6f45
GL		 974 &dma0_device,
975 &dma1_device,
976 &dma2_device,
afe48049
KM		 977 &usb_dma0_device,
978 &usb_dma1_device,
6822471e
MD		 979 &vpu_device,
980 &veu0_device,
981 &veu1_device,
982 &veu2_device,
983 &veu3_device,
984 &jpu_device,
985 &spu0_device,
986 &spu1_device,
2b7eda63
MD		 987};
988
989void __init sh7372_add_standard_devices(void)
990{
96f7934e 991 sh7372_init_pm_domain(&sh7372_a4lc);
c1ba5bb5 992 sh7372_init_pm_domain(&sh7372_a4mp);
d24771de 993 sh7372_init_pm_domain(&sh7372_d4);
33afebf3 994 sh7372_init_pm_domain(&sh7372_a3rv);
082517aa 995 sh7372_init_pm_domain(&sh7372_a3ri);
c47586b6 996 sh7372_init_pm_domain(&sh7372_a3sg);
96f7934e 997
111058c3
RW		 998 sh7372_pm_add_subdomain(&sh7372_a4lc, &sh7372_a3rv);
999
2b7eda63
MD		 1000 platform_add_devices(sh7372_early_devices,
1001 ARRAY_SIZE(sh7372_early_devices));
934e4078
MD		 1002
1003 platform_add_devices(sh7372_late_devices,
1004 ARRAY_SIZE(sh7372_late_devices));
33afebf3
MD		 1005
1006 sh7372_add_device_to_domain(&sh7372_a3rv, &vpu_device);
c1ba5bb5
KM		 1007 sh7372_add_device_to_domain(&sh7372_a4mp, &spu0_device);
1008 sh7372_add_device_to_domain(&sh7372_a4mp, &spu1_device);
2b7eda63
MD		 1009}
1010
2b7eda63
MD		 1011void __init sh7372_add_early_devices(void)
1012{
2b7eda63
MD		 1013 early_platform_add_devices(sh7372_early_devices,
1014 ARRAY_SIZE(sh7372_early_devices));
1015}
Linux kernel - Deliverables
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