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f2aaf66d MD |
1 | /* |
2 | * sh7377 processor support | |
3 | * | |
4 | * Copyright (C) 2010 Magnus Damm | |
5 | * Copyright (C) 2008 Yoshihiro Shimoda | |
6 | * | |
7 | * This program is free software; you can redistribute it and/or modify | |
8 | * it under the terms of the GNU General Public License as published by | |
9 | * the Free Software Foundation; version 2 of the License. | |
10 | * | |
11 | * This program is distributed in the hope that it will be useful, | |
12 | * but WITHOUT ANY WARRANTY; without even the implied warranty of | |
13 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
14 | * GNU General Public License for more details. | |
15 | * | |
16 | * You should have received a copy of the GNU General Public License | |
17 | * along with this program; if not, write to the Free Software | |
18 | * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA | |
19 | */ | |
20 | #include <linux/kernel.h> | |
21 | #include <linux/init.h> | |
22 | #include <linux/interrupt.h> | |
23 | #include <linux/irq.h> | |
24 | #include <linux/platform_device.h> | |
c9fcf007 | 25 | #include <linux/uio_driver.h> |
f2aaf66d MD |
26 | #include <linux/delay.h> |
27 | #include <linux/input.h> | |
28 | #include <linux/io.h> | |
29 | #include <linux/serial_sci.h> | |
30 | #include <linux/sh_intc.h> | |
31 | #include <linux/sh_timer.h> | |
32 | #include <mach/hardware.h> | |
bfc46f3e MD |
33 | #include <mach/common.h> |
34 | #include <asm/mach/map.h> | |
250a2723 | 35 | #include <mach/irqs.h> |
f2aaf66d MD |
36 | #include <asm/mach-types.h> |
37 | #include <asm/mach/arch.h> | |
03f7beef | 38 | #include <asm/mach/time.h> |
f2aaf66d | 39 | |
bfc46f3e MD |
40 | static struct map_desc sh7377_io_desc[] __initdata = { |
41 | /* create a 1:1 entity map for 0xe6xxxxxx | |
42 | * used by CPGA, INTC and PFC. | |
43 | */ | |
44 | { | |
45 | .virtual = 0xe6000000, | |
46 | .pfn = __phys_to_pfn(0xe6000000), | |
47 | .length = 256 << 20, | |
48 | .type = MT_DEVICE_NONSHARED | |
49 | }, | |
50 | }; | |
51 | ||
52 | void __init sh7377_map_io(void) | |
53 | { | |
54 | iotable_init(sh7377_io_desc, ARRAY_SIZE(sh7377_io_desc)); | |
55 | } | |
56 | ||
043296dd | 57 | /* SCIFA0 */ |
f2aaf66d MD |
58 | static struct plat_sci_port scif0_platform_data = { |
59 | .mapbase = 0xe6c40000, | |
60 | .flags = UPF_BOOT_AUTOCONF, | |
f43dc23d PM |
61 | .scscr = SCSCR_RE | SCSCR_TE, |
62 | .scbrr_algo_id = SCBRR_ALGO_4, | |
1d0738ea | 63 | .type = PORT_SCIFA, |
043296dd MD |
64 | .irqs = { evt2irq(0xc00), evt2irq(0xc00), |
65 | evt2irq(0xc00), evt2irq(0xc00) }, | |
f2aaf66d MD |
66 | }; |
67 | ||
68 | static struct platform_device scif0_device = { | |
69 | .name = "sh-sci", | |
70 | .id = 0, | |
71 | .dev = { | |
72 | .platform_data = &scif0_platform_data, | |
73 | }, | |
74 | }; | |
75 | ||
043296dd | 76 | /* SCIFA1 */ |
f2aaf66d MD |
77 | static struct plat_sci_port scif1_platform_data = { |
78 | .mapbase = 0xe6c50000, | |
79 | .flags = UPF_BOOT_AUTOCONF, | |
f43dc23d PM |
80 | .scscr = SCSCR_RE | SCSCR_TE, |
81 | .scbrr_algo_id = SCBRR_ALGO_4, | |
1d0738ea | 82 | .type = PORT_SCIFA, |
043296dd MD |
83 | .irqs = { evt2irq(0xc20), evt2irq(0xc20), |
84 | evt2irq(0xc20), evt2irq(0xc20) }, | |
f2aaf66d MD |
85 | }; |
86 | ||
87 | static struct platform_device scif1_device = { | |
88 | .name = "sh-sci", | |
89 | .id = 1, | |
90 | .dev = { | |
91 | .platform_data = &scif1_platform_data, | |
92 | }, | |
93 | }; | |
94 | ||
043296dd | 95 | /* SCIFA2 */ |
f2aaf66d MD |
96 | static struct plat_sci_port scif2_platform_data = { |
97 | .mapbase = 0xe6c60000, | |
98 | .flags = UPF_BOOT_AUTOCONF, | |
f43dc23d PM |
99 | .scscr = SCSCR_RE | SCSCR_TE, |
100 | .scbrr_algo_id = SCBRR_ALGO_4, | |
1d0738ea | 101 | .type = PORT_SCIFA, |
043296dd MD |
102 | .irqs = { evt2irq(0xc40), evt2irq(0xc40), |
103 | evt2irq(0xc40), evt2irq(0xc40) }, | |
f2aaf66d MD |
104 | }; |
105 | ||
106 | static struct platform_device scif2_device = { | |
107 | .name = "sh-sci", | |
108 | .id = 2, | |
109 | .dev = { | |
110 | .platform_data = &scif2_platform_data, | |
111 | }, | |
112 | }; | |
113 | ||
043296dd | 114 | /* SCIFA3 */ |
f2aaf66d MD |
115 | static struct plat_sci_port scif3_platform_data = { |
116 | .mapbase = 0xe6c70000, | |
117 | .flags = UPF_BOOT_AUTOCONF, | |
f43dc23d PM |
118 | .scscr = SCSCR_RE | SCSCR_TE, |
119 | .scbrr_algo_id = SCBRR_ALGO_4, | |
1d0738ea | 120 | .type = PORT_SCIFA, |
043296dd MD |
121 | .irqs = { evt2irq(0xc60), evt2irq(0xc60), |
122 | evt2irq(0xc60), evt2irq(0xc60) }, | |
f2aaf66d MD |
123 | }; |
124 | ||
125 | static struct platform_device scif3_device = { | |
126 | .name = "sh-sci", | |
127 | .id = 3, | |
128 | .dev = { | |
129 | .platform_data = &scif3_platform_data, | |
130 | }, | |
131 | }; | |
132 | ||
043296dd | 133 | /* SCIFA4 */ |
f2aaf66d MD |
134 | static struct plat_sci_port scif4_platform_data = { |
135 | .mapbase = 0xe6c80000, | |
136 | .flags = UPF_BOOT_AUTOCONF, | |
f43dc23d PM |
137 | .scscr = SCSCR_RE | SCSCR_TE, |
138 | .scbrr_algo_id = SCBRR_ALGO_4, | |
1d0738ea | 139 | .type = PORT_SCIFA, |
043296dd MD |
140 | .irqs = { evt2irq(0xd20), evt2irq(0xd20), |
141 | evt2irq(0xd20), evt2irq(0xd20) }, | |
f2aaf66d MD |
142 | }; |
143 | ||
144 | static struct platform_device scif4_device = { | |
145 | .name = "sh-sci", | |
146 | .id = 4, | |
147 | .dev = { | |
148 | .platform_data = &scif4_platform_data, | |
149 | }, | |
150 | }; | |
151 | ||
043296dd | 152 | /* SCIFA5 */ |
f2aaf66d MD |
153 | static struct plat_sci_port scif5_platform_data = { |
154 | .mapbase = 0xe6cb0000, | |
155 | .flags = UPF_BOOT_AUTOCONF, | |
f43dc23d PM |
156 | .scscr = SCSCR_RE | SCSCR_TE, |
157 | .scbrr_algo_id = SCBRR_ALGO_4, | |
1d0738ea | 158 | .type = PORT_SCIFA, |
043296dd MD |
159 | .irqs = { evt2irq(0xd40), evt2irq(0xd40), |
160 | evt2irq(0xd40), evt2irq(0xd40) }, | |
f2aaf66d MD |
161 | }; |
162 | ||
163 | static struct platform_device scif5_device = { | |
164 | .name = "sh-sci", | |
165 | .id = 5, | |
166 | .dev = { | |
167 | .platform_data = &scif5_platform_data, | |
168 | }, | |
169 | }; | |
170 | ||
043296dd | 171 | /* SCIFA6 */ |
f2aaf66d MD |
172 | static struct plat_sci_port scif6_platform_data = { |
173 | .mapbase = 0xe6cc0000, | |
174 | .flags = UPF_BOOT_AUTOCONF, | |
f43dc23d PM |
175 | .scscr = SCSCR_RE | SCSCR_TE, |
176 | .scbrr_algo_id = SCBRR_ALGO_4, | |
1d0738ea | 177 | .type = PORT_SCIFA, |
043296dd MD |
178 | .irqs = { intcs_evt2irq(0x1a80), intcs_evt2irq(0x1a80), |
179 | intcs_evt2irq(0x1a80), intcs_evt2irq(0x1a80) }, | |
f2aaf66d MD |
180 | }; |
181 | ||
182 | static struct platform_device scif6_device = { | |
183 | .name = "sh-sci", | |
184 | .id = 6, | |
185 | .dev = { | |
186 | .platform_data = &scif6_platform_data, | |
187 | }, | |
188 | }; | |
189 | ||
043296dd | 190 | /* SCIFB */ |
f2aaf66d MD |
191 | static struct plat_sci_port scif7_platform_data = { |
192 | .mapbase = 0xe6c30000, | |
193 | .flags = UPF_BOOT_AUTOCONF, | |
f43dc23d PM |
194 | .scscr = SCSCR_RE | SCSCR_TE, |
195 | .scbrr_algo_id = SCBRR_ALGO_4, | |
1d0738ea | 196 | .type = PORT_SCIFB, |
043296dd MD |
197 | .irqs = { evt2irq(0xd60), evt2irq(0xd60), |
198 | evt2irq(0xd60), evt2irq(0xd60) }, | |
f2aaf66d MD |
199 | }; |
200 | ||
201 | static struct platform_device scif7_device = { | |
202 | .name = "sh-sci", | |
203 | .id = 7, | |
204 | .dev = { | |
205 | .platform_data = &scif7_platform_data, | |
206 | }, | |
207 | }; | |
208 | ||
209 | static struct sh_timer_config cmt10_platform_data = { | |
210 | .name = "CMT10", | |
211 | .channel_offset = 0x10, | |
212 | .timer_bit = 0, | |
f2aaf66d MD |
213 | .clockevent_rating = 125, |
214 | .clocksource_rating = 125, | |
215 | }; | |
216 | ||
217 | static struct resource cmt10_resources[] = { | |
218 | [0] = { | |
219 | .name = "CMT10", | |
220 | .start = 0xe6138010, | |
221 | .end = 0xe613801b, | |
222 | .flags = IORESOURCE_MEM, | |
223 | }, | |
224 | [1] = { | |
043296dd | 225 | .start = evt2irq(0xb00), /* CMT1_CMT10 */ |
f2aaf66d MD |
226 | .flags = IORESOURCE_IRQ, |
227 | }, | |
228 | }; | |
229 | ||
230 | static struct platform_device cmt10_device = { | |
231 | .name = "sh_cmt", | |
232 | .id = 10, | |
233 | .dev = { | |
234 | .platform_data = &cmt10_platform_data, | |
235 | }, | |
236 | .resource = cmt10_resources, | |
237 | .num_resources = ARRAY_SIZE(cmt10_resources), | |
238 | }; | |
239 | ||
c9fcf007 MD |
240 | /* VPU */ |
241 | static struct uio_info vpu_platform_data = { | |
242 | .name = "VPU5HG", | |
243 | .version = "0", | |
244 | .irq = intcs_evt2irq(0x980), | |
245 | }; | |
246 | ||
247 | static struct resource vpu_resources[] = { | |
248 | [0] = { | |
249 | .name = "VPU", | |
250 | .start = 0xfe900000, | |
251 | .end = 0xfe900157, | |
252 | .flags = IORESOURCE_MEM, | |
253 | }, | |
254 | }; | |
255 | ||
256 | static struct platform_device vpu_device = { | |
257 | .name = "uio_pdrv_genirq", | |
258 | .id = 0, | |
259 | .dev = { | |
260 | .platform_data = &vpu_platform_data, | |
261 | }, | |
262 | .resource = vpu_resources, | |
263 | .num_resources = ARRAY_SIZE(vpu_resources), | |
264 | }; | |
265 | ||
266 | /* VEU0 */ | |
267 | static struct uio_info veu0_platform_data = { | |
268 | .name = "VEU0", | |
269 | .version = "0", | |
270 | .irq = intcs_evt2irq(0x700), | |
271 | }; | |
272 | ||
273 | static struct resource veu0_resources[] = { | |
274 | [0] = { | |
275 | .name = "VEU0", | |
276 | .start = 0xfe920000, | |
277 | .end = 0xfe9200cb, | |
278 | .flags = IORESOURCE_MEM, | |
279 | }, | |
280 | }; | |
281 | ||
282 | static struct platform_device veu0_device = { | |
283 | .name = "uio_pdrv_genirq", | |
284 | .id = 1, | |
285 | .dev = { | |
286 | .platform_data = &veu0_platform_data, | |
287 | }, | |
288 | .resource = veu0_resources, | |
289 | .num_resources = ARRAY_SIZE(veu0_resources), | |
290 | }; | |
291 | ||
292 | /* VEU1 */ | |
293 | static struct uio_info veu1_platform_data = { | |
294 | .name = "VEU1", | |
295 | .version = "0", | |
296 | .irq = intcs_evt2irq(0x720), | |
297 | }; | |
298 | ||
299 | static struct resource veu1_resources[] = { | |
300 | [0] = { | |
301 | .name = "VEU1", | |
302 | .start = 0xfe924000, | |
303 | .end = 0xfe9240cb, | |
304 | .flags = IORESOURCE_MEM, | |
305 | }, | |
306 | }; | |
307 | ||
308 | static struct platform_device veu1_device = { | |
309 | .name = "uio_pdrv_genirq", | |
310 | .id = 2, | |
311 | .dev = { | |
312 | .platform_data = &veu1_platform_data, | |
313 | }, | |
314 | .resource = veu1_resources, | |
315 | .num_resources = ARRAY_SIZE(veu1_resources), | |
316 | }; | |
317 | ||
318 | /* VEU2 */ | |
319 | static struct uio_info veu2_platform_data = { | |
320 | .name = "VEU2", | |
321 | .version = "0", | |
322 | .irq = intcs_evt2irq(0x740), | |
323 | }; | |
324 | ||
325 | static struct resource veu2_resources[] = { | |
326 | [0] = { | |
327 | .name = "VEU2", | |
328 | .start = 0xfe928000, | |
329 | .end = 0xfe928307, | |
330 | .flags = IORESOURCE_MEM, | |
331 | }, | |
332 | }; | |
333 | ||
334 | static struct platform_device veu2_device = { | |
335 | .name = "uio_pdrv_genirq", | |
336 | .id = 3, | |
337 | .dev = { | |
338 | .platform_data = &veu2_platform_data, | |
339 | }, | |
340 | .resource = veu2_resources, | |
341 | .num_resources = ARRAY_SIZE(veu2_resources), | |
342 | }; | |
343 | ||
344 | /* VEU3 */ | |
345 | static struct uio_info veu3_platform_data = { | |
346 | .name = "VEU3", | |
347 | .version = "0", | |
348 | .irq = intcs_evt2irq(0x760), | |
349 | }; | |
350 | ||
351 | static struct resource veu3_resources[] = { | |
352 | [0] = { | |
353 | .name = "VEU3", | |
354 | .start = 0xfe92c000, | |
355 | .end = 0xfe92c307, | |
356 | .flags = IORESOURCE_MEM, | |
357 | }, | |
358 | }; | |
359 | ||
360 | static struct platform_device veu3_device = { | |
361 | .name = "uio_pdrv_genirq", | |
362 | .id = 4, | |
363 | .dev = { | |
364 | .platform_data = &veu3_platform_data, | |
365 | }, | |
366 | .resource = veu3_resources, | |
367 | .num_resources = ARRAY_SIZE(veu3_resources), | |
368 | }; | |
369 | ||
370 | /* JPU */ | |
371 | static struct uio_info jpu_platform_data = { | |
372 | .name = "JPU", | |
373 | .version = "0", | |
374 | .irq = intcs_evt2irq(0x560), | |
375 | }; | |
376 | ||
377 | static struct resource jpu_resources[] = { | |
378 | [0] = { | |
379 | .name = "JPU", | |
380 | .start = 0xfe980000, | |
381 | .end = 0xfe9902d3, | |
382 | .flags = IORESOURCE_MEM, | |
383 | }, | |
384 | }; | |
385 | ||
386 | static struct platform_device jpu_device = { | |
387 | .name = "uio_pdrv_genirq", | |
388 | .id = 5, | |
389 | .dev = { | |
390 | .platform_data = &jpu_platform_data, | |
391 | }, | |
392 | .resource = jpu_resources, | |
393 | .num_resources = ARRAY_SIZE(jpu_resources), | |
394 | }; | |
395 | ||
396 | /* SPU2DSP0 */ | |
397 | static struct uio_info spu0_platform_data = { | |
398 | .name = "SPU2DSP0", | |
399 | .version = "0", | |
400 | .irq = evt2irq(0x1800), | |
401 | }; | |
402 | ||
403 | static struct resource spu0_resources[] = { | |
404 | [0] = { | |
405 | .name = "SPU2DSP0", | |
406 | .start = 0xfe200000, | |
407 | .end = 0xfe2fffff, | |
408 | .flags = IORESOURCE_MEM, | |
409 | }, | |
410 | }; | |
411 | ||
412 | static struct platform_device spu0_device = { | |
413 | .name = "uio_pdrv_genirq", | |
414 | .id = 6, | |
415 | .dev = { | |
416 | .platform_data = &spu0_platform_data, | |
417 | }, | |
418 | .resource = spu0_resources, | |
419 | .num_resources = ARRAY_SIZE(spu0_resources), | |
420 | }; | |
421 | ||
422 | /* SPU2DSP1 */ | |
423 | static struct uio_info spu1_platform_data = { | |
424 | .name = "SPU2DSP1", | |
425 | .version = "0", | |
426 | .irq = evt2irq(0x1820), | |
427 | }; | |
428 | ||
429 | static struct resource spu1_resources[] = { | |
430 | [0] = { | |
431 | .name = "SPU2DSP1", | |
432 | .start = 0xfe300000, | |
433 | .end = 0xfe3fffff, | |
434 | .flags = IORESOURCE_MEM, | |
435 | }, | |
436 | }; | |
437 | ||
438 | static struct platform_device spu1_device = { | |
439 | .name = "uio_pdrv_genirq", | |
440 | .id = 7, | |
441 | .dev = { | |
442 | .platform_data = &spu1_platform_data, | |
443 | }, | |
444 | .resource = spu1_resources, | |
445 | .num_resources = ARRAY_SIZE(spu1_resources), | |
446 | }; | |
447 | ||
f2aaf66d MD |
448 | static struct platform_device *sh7377_early_devices[] __initdata = { |
449 | &scif0_device, | |
450 | &scif1_device, | |
451 | &scif2_device, | |
452 | &scif3_device, | |
453 | &scif4_device, | |
454 | &scif5_device, | |
455 | &scif6_device, | |
456 | &scif7_device, | |
457 | &cmt10_device, | |
458 | }; | |
459 | ||
c9fcf007 MD |
460 | static struct platform_device *sh7377_devices[] __initdata = { |
461 | &vpu_device, | |
462 | &veu0_device, | |
463 | &veu1_device, | |
464 | &veu2_device, | |
465 | &veu3_device, | |
466 | &jpu_device, | |
467 | &spu0_device, | |
468 | &spu1_device, | |
469 | }; | |
470 | ||
f2aaf66d MD |
471 | void __init sh7377_add_standard_devices(void) |
472 | { | |
473 | platform_add_devices(sh7377_early_devices, | |
474 | ARRAY_SIZE(sh7377_early_devices)); | |
c9fcf007 MD |
475 | |
476 | platform_add_devices(sh7377_devices, | |
477 | ARRAY_SIZE(sh7377_devices)); | |
f2aaf66d MD |
478 | } |
479 | ||
03f7beef MD |
480 | static void __init sh7377_earlytimer_init(void) |
481 | { | |
482 | sh7377_clock_init(); | |
483 | shmobile_earlytimer_init(); | |
484 | } | |
485 | ||
f2aaf66d MD |
486 | #define SMSTPCR3 0xe615013c |
487 | #define SMSTPCR3_CMT1 (1 << 29) | |
488 | ||
489 | void __init sh7377_add_early_devices(void) | |
490 | { | |
491 | /* enable clock to CMT1 */ | |
492 | __raw_writel(__raw_readl(SMSTPCR3) & ~SMSTPCR3_CMT1, SMSTPCR3); | |
493 | ||
494 | early_platform_add_devices(sh7377_early_devices, | |
495 | ARRAY_SIZE(sh7377_early_devices)); | |
bfc46f3e MD |
496 | |
497 | /* setup early console here as well */ | |
498 | shmobile_setup_console(); | |
03f7beef MD |
499 | |
500 | /* override timer setup with soc-specific code */ | |
501 | shmobile_timer.init = sh7377_earlytimer_init; | |
f2aaf66d | 502 | } |