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6d9598e2 MD |
1 | /* |
2 | * sh73a0 processor support | |
3 | * | |
4 | * Copyright (C) 2010 Takashi Yoshii | |
5 | * Copyright (C) 2010 Magnus Damm | |
6 | * Copyright (C) 2008 Yoshihiro Shimoda | |
7 | * | |
8 | * This program is free software; you can redistribute it and/or modify | |
9 | * it under the terms of the GNU General Public License as published by | |
10 | * the Free Software Foundation; version 2 of the License. | |
11 | * | |
12 | * This program is distributed in the hope that it will be useful, | |
13 | * but WITHOUT ANY WARRANTY; without even the implied warranty of | |
14 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
15 | * GNU General Public License for more details. | |
16 | * | |
17 | * You should have received a copy of the GNU General Public License | |
18 | * along with this program; if not, write to the Free Software | |
19 | * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA | |
20 | */ | |
21 | #include <linux/kernel.h> | |
22 | #include <linux/init.h> | |
23 | #include <linux/interrupt.h> | |
24 | #include <linux/irq.h> | |
25 | #include <linux/platform_device.h> | |
26 | #include <linux/delay.h> | |
27 | #include <linux/input.h> | |
28 | #include <linux/io.h> | |
29 | #include <linux/serial_sci.h> | |
681e1b3e | 30 | #include <linux/sh_dma.h> |
6d9598e2 MD |
31 | #include <linux/sh_intc.h> |
32 | #include <linux/sh_timer.h> | |
33 | #include <mach/hardware.h> | |
250a2723 | 34 | #include <mach/irqs.h> |
681e1b3e | 35 | #include <mach/sh73a0.h> |
50e15c34 | 36 | #include <mach/common.h> |
6d9598e2 | 37 | #include <asm/mach-types.h> |
50e15c34 | 38 | #include <asm/mach/map.h> |
6d9598e2 | 39 | #include <asm/mach/arch.h> |
3be26fdb | 40 | #include <asm/mach/time.h> |
6d9598e2 | 41 | |
50e15c34 MD |
42 | static struct map_desc sh73a0_io_desc[] __initdata = { |
43 | /* create a 1:1 entity map for 0xe6xxxxxx | |
44 | * used by CPGA, INTC and PFC. | |
45 | */ | |
46 | { | |
47 | .virtual = 0xe6000000, | |
48 | .pfn = __phys_to_pfn(0xe6000000), | |
49 | .length = 256 << 20, | |
50 | .type = MT_DEVICE_NONSHARED | |
51 | }, | |
52 | }; | |
53 | ||
54 | void __init sh73a0_map_io(void) | |
55 | { | |
56 | iotable_init(sh73a0_io_desc, ARRAY_SIZE(sh73a0_io_desc)); | |
57 | } | |
58 | ||
6d9598e2 MD |
59 | static struct plat_sci_port scif0_platform_data = { |
60 | .mapbase = 0xe6c40000, | |
61 | .flags = UPF_BOOT_AUTOCONF, | |
f43dc23d PM |
62 | .scscr = SCSCR_RE | SCSCR_TE, |
63 | .scbrr_algo_id = SCBRR_ALGO_4, | |
6d9598e2 MD |
64 | .type = PORT_SCIFA, |
65 | .irqs = { gic_spi(72), gic_spi(72), | |
66 | gic_spi(72), gic_spi(72) }, | |
67 | }; | |
68 | ||
69 | static struct platform_device scif0_device = { | |
70 | .name = "sh-sci", | |
71 | .id = 0, | |
72 | .dev = { | |
73 | .platform_data = &scif0_platform_data, | |
74 | }, | |
75 | }; | |
76 | ||
77 | static struct plat_sci_port scif1_platform_data = { | |
78 | .mapbase = 0xe6c50000, | |
79 | .flags = UPF_BOOT_AUTOCONF, | |
f43dc23d PM |
80 | .scscr = SCSCR_RE | SCSCR_TE, |
81 | .scbrr_algo_id = SCBRR_ALGO_4, | |
6d9598e2 MD |
82 | .type = PORT_SCIFA, |
83 | .irqs = { gic_spi(73), gic_spi(73), | |
84 | gic_spi(73), gic_spi(73) }, | |
85 | }; | |
86 | ||
87 | static struct platform_device scif1_device = { | |
88 | .name = "sh-sci", | |
89 | .id = 1, | |
90 | .dev = { | |
91 | .platform_data = &scif1_platform_data, | |
92 | }, | |
93 | }; | |
94 | ||
95 | static struct plat_sci_port scif2_platform_data = { | |
96 | .mapbase = 0xe6c60000, | |
97 | .flags = UPF_BOOT_AUTOCONF, | |
f43dc23d PM |
98 | .scscr = SCSCR_RE | SCSCR_TE, |
99 | .scbrr_algo_id = SCBRR_ALGO_4, | |
6d9598e2 MD |
100 | .type = PORT_SCIFA, |
101 | .irqs = { gic_spi(74), gic_spi(74), | |
102 | gic_spi(74), gic_spi(74) }, | |
103 | }; | |
104 | ||
105 | static struct platform_device scif2_device = { | |
106 | .name = "sh-sci", | |
107 | .id = 2, | |
108 | .dev = { | |
109 | .platform_data = &scif2_platform_data, | |
110 | }, | |
111 | }; | |
112 | ||
113 | static struct plat_sci_port scif3_platform_data = { | |
114 | .mapbase = 0xe6c70000, | |
115 | .flags = UPF_BOOT_AUTOCONF, | |
f43dc23d PM |
116 | .scscr = SCSCR_RE | SCSCR_TE, |
117 | .scbrr_algo_id = SCBRR_ALGO_4, | |
6d9598e2 MD |
118 | .type = PORT_SCIFA, |
119 | .irqs = { gic_spi(75), gic_spi(75), | |
120 | gic_spi(75), gic_spi(75) }, | |
121 | }; | |
122 | ||
123 | static struct platform_device scif3_device = { | |
124 | .name = "sh-sci", | |
125 | .id = 3, | |
126 | .dev = { | |
127 | .platform_data = &scif3_platform_data, | |
128 | }, | |
129 | }; | |
130 | ||
131 | static struct plat_sci_port scif4_platform_data = { | |
132 | .mapbase = 0xe6c80000, | |
133 | .flags = UPF_BOOT_AUTOCONF, | |
f43dc23d PM |
134 | .scscr = SCSCR_RE | SCSCR_TE, |
135 | .scbrr_algo_id = SCBRR_ALGO_4, | |
6d9598e2 MD |
136 | .type = PORT_SCIFA, |
137 | .irqs = { gic_spi(78), gic_spi(78), | |
138 | gic_spi(78), gic_spi(78) }, | |
139 | }; | |
140 | ||
141 | static struct platform_device scif4_device = { | |
142 | .name = "sh-sci", | |
143 | .id = 4, | |
144 | .dev = { | |
145 | .platform_data = &scif4_platform_data, | |
146 | }, | |
147 | }; | |
148 | ||
149 | static struct plat_sci_port scif5_platform_data = { | |
150 | .mapbase = 0xe6cb0000, | |
151 | .flags = UPF_BOOT_AUTOCONF, | |
f43dc23d PM |
152 | .scscr = SCSCR_RE | SCSCR_TE, |
153 | .scbrr_algo_id = SCBRR_ALGO_4, | |
6d9598e2 MD |
154 | .type = PORT_SCIFA, |
155 | .irqs = { gic_spi(79), gic_spi(79), | |
156 | gic_spi(79), gic_spi(79) }, | |
157 | }; | |
158 | ||
159 | static struct platform_device scif5_device = { | |
160 | .name = "sh-sci", | |
161 | .id = 5, | |
162 | .dev = { | |
163 | .platform_data = &scif5_platform_data, | |
164 | }, | |
165 | }; | |
166 | ||
167 | static struct plat_sci_port scif6_platform_data = { | |
168 | .mapbase = 0xe6cc0000, | |
169 | .flags = UPF_BOOT_AUTOCONF, | |
f43dc23d PM |
170 | .scscr = SCSCR_RE | SCSCR_TE, |
171 | .scbrr_algo_id = SCBRR_ALGO_4, | |
6d9598e2 MD |
172 | .type = PORT_SCIFA, |
173 | .irqs = { gic_spi(156), gic_spi(156), | |
174 | gic_spi(156), gic_spi(156) }, | |
175 | }; | |
176 | ||
177 | static struct platform_device scif6_device = { | |
178 | .name = "sh-sci", | |
179 | .id = 6, | |
180 | .dev = { | |
181 | .platform_data = &scif6_platform_data, | |
182 | }, | |
183 | }; | |
184 | ||
185 | static struct plat_sci_port scif7_platform_data = { | |
186 | .mapbase = 0xe6cd0000, | |
187 | .flags = UPF_BOOT_AUTOCONF, | |
f43dc23d PM |
188 | .scscr = SCSCR_RE | SCSCR_TE, |
189 | .scbrr_algo_id = SCBRR_ALGO_4, | |
6d9598e2 MD |
190 | .type = PORT_SCIFA, |
191 | .irqs = { gic_spi(143), gic_spi(143), | |
192 | gic_spi(143), gic_spi(143) }, | |
193 | }; | |
194 | ||
195 | static struct platform_device scif7_device = { | |
196 | .name = "sh-sci", | |
197 | .id = 7, | |
198 | .dev = { | |
199 | .platform_data = &scif7_platform_data, | |
200 | }, | |
201 | }; | |
202 | ||
203 | static struct plat_sci_port scif8_platform_data = { | |
204 | .mapbase = 0xe6c30000, | |
205 | .flags = UPF_BOOT_AUTOCONF, | |
f43dc23d PM |
206 | .scscr = SCSCR_RE | SCSCR_TE, |
207 | .scbrr_algo_id = SCBRR_ALGO_4, | |
6d9598e2 MD |
208 | .type = PORT_SCIFB, |
209 | .irqs = { gic_spi(80), gic_spi(80), | |
210 | gic_spi(80), gic_spi(80) }, | |
211 | }; | |
212 | ||
213 | static struct platform_device scif8_device = { | |
214 | .name = "sh-sci", | |
215 | .id = 8, | |
216 | .dev = { | |
217 | .platform_data = &scif8_platform_data, | |
218 | }, | |
219 | }; | |
220 | ||
221 | static struct sh_timer_config cmt10_platform_data = { | |
222 | .name = "CMT10", | |
223 | .channel_offset = 0x10, | |
224 | .timer_bit = 0, | |
225 | .clockevent_rating = 125, | |
226 | .clocksource_rating = 125, | |
227 | }; | |
228 | ||
229 | static struct resource cmt10_resources[] = { | |
230 | [0] = { | |
231 | .name = "CMT10", | |
232 | .start = 0xe6138010, | |
233 | .end = 0xe613801b, | |
234 | .flags = IORESOURCE_MEM, | |
235 | }, | |
236 | [1] = { | |
237 | .start = gic_spi(65), | |
238 | .flags = IORESOURCE_IRQ, | |
239 | }, | |
240 | }; | |
241 | ||
242 | static struct platform_device cmt10_device = { | |
243 | .name = "sh_cmt", | |
244 | .id = 10, | |
245 | .dev = { | |
246 | .platform_data = &cmt10_platform_data, | |
247 | }, | |
248 | .resource = cmt10_resources, | |
249 | .num_resources = ARRAY_SIZE(cmt10_resources), | |
250 | }; | |
251 | ||
5010f3db MD |
252 | /* TMU */ |
253 | static struct sh_timer_config tmu00_platform_data = { | |
254 | .name = "TMU00", | |
255 | .channel_offset = 0x4, | |
256 | .timer_bit = 0, | |
257 | .clockevent_rating = 200, | |
258 | }; | |
259 | ||
260 | static struct resource tmu00_resources[] = { | |
261 | [0] = { | |
262 | .name = "TMU00", | |
263 | .start = 0xfff60008, | |
264 | .end = 0xfff60013, | |
265 | .flags = IORESOURCE_MEM, | |
266 | }, | |
267 | [1] = { | |
268 | .start = intcs_evt2irq(0x0e80), /* TMU0_TUNI00 */ | |
269 | .flags = IORESOURCE_IRQ, | |
270 | }, | |
271 | }; | |
272 | ||
273 | static struct platform_device tmu00_device = { | |
274 | .name = "sh_tmu", | |
275 | .id = 0, | |
276 | .dev = { | |
277 | .platform_data = &tmu00_platform_data, | |
278 | }, | |
279 | .resource = tmu00_resources, | |
280 | .num_resources = ARRAY_SIZE(tmu00_resources), | |
281 | }; | |
282 | ||
283 | static struct sh_timer_config tmu01_platform_data = { | |
284 | .name = "TMU01", | |
285 | .channel_offset = 0x10, | |
286 | .timer_bit = 1, | |
287 | .clocksource_rating = 200, | |
288 | }; | |
289 | ||
290 | static struct resource tmu01_resources[] = { | |
291 | [0] = { | |
292 | .name = "TMU01", | |
293 | .start = 0xfff60014, | |
294 | .end = 0xfff6001f, | |
295 | .flags = IORESOURCE_MEM, | |
296 | }, | |
297 | [1] = { | |
298 | .start = intcs_evt2irq(0x0ea0), /* TMU0_TUNI01 */ | |
299 | .flags = IORESOURCE_IRQ, | |
300 | }, | |
301 | }; | |
302 | ||
303 | static struct platform_device tmu01_device = { | |
304 | .name = "sh_tmu", | |
305 | .id = 1, | |
306 | .dev = { | |
307 | .platform_data = &tmu01_platform_data, | |
308 | }, | |
309 | .resource = tmu01_resources, | |
310 | .num_resources = ARRAY_SIZE(tmu01_resources), | |
311 | }; | |
312 | ||
b028f94b YT |
313 | static struct resource i2c0_resources[] = { |
314 | [0] = { | |
315 | .name = "IIC0", | |
316 | .start = 0xe6820000, | |
317 | .end = 0xe6820425 - 1, | |
318 | .flags = IORESOURCE_MEM, | |
319 | }, | |
320 | [1] = { | |
321 | .start = gic_spi(167), | |
322 | .end = gic_spi(170), | |
323 | .flags = IORESOURCE_IRQ, | |
324 | }, | |
325 | }; | |
326 | ||
327 | static struct resource i2c1_resources[] = { | |
328 | [0] = { | |
329 | .name = "IIC1", | |
330 | .start = 0xe6822000, | |
331 | .end = 0xe6822425 - 1, | |
332 | .flags = IORESOURCE_MEM, | |
333 | }, | |
334 | [1] = { | |
335 | .start = gic_spi(51), | |
336 | .end = gic_spi(54), | |
337 | .flags = IORESOURCE_IRQ, | |
338 | }, | |
339 | }; | |
340 | ||
341 | static struct resource i2c2_resources[] = { | |
342 | [0] = { | |
343 | .name = "IIC2", | |
344 | .start = 0xe6824000, | |
345 | .end = 0xe6824425 - 1, | |
346 | .flags = IORESOURCE_MEM, | |
347 | }, | |
348 | [1] = { | |
349 | .start = gic_spi(171), | |
350 | .end = gic_spi(174), | |
351 | .flags = IORESOURCE_IRQ, | |
352 | }, | |
353 | }; | |
354 | ||
355 | static struct resource i2c3_resources[] = { | |
356 | [0] = { | |
357 | .name = "IIC3", | |
358 | .start = 0xe6826000, | |
359 | .end = 0xe6826425 - 1, | |
360 | .flags = IORESOURCE_MEM, | |
361 | }, | |
362 | [1] = { | |
363 | .start = gic_spi(183), | |
364 | .end = gic_spi(186), | |
365 | .flags = IORESOURCE_IRQ, | |
366 | }, | |
367 | }; | |
368 | ||
369 | static struct resource i2c4_resources[] = { | |
370 | [0] = { | |
371 | .name = "IIC4", | |
372 | .start = 0xe6828000, | |
373 | .end = 0xe6828425 - 1, | |
374 | .flags = IORESOURCE_MEM, | |
375 | }, | |
376 | [1] = { | |
377 | .start = gic_spi(187), | |
378 | .end = gic_spi(190), | |
379 | .flags = IORESOURCE_IRQ, | |
380 | }, | |
381 | }; | |
382 | ||
383 | static struct platform_device i2c0_device = { | |
384 | .name = "i2c-sh_mobile", | |
385 | .id = 0, | |
386 | .resource = i2c0_resources, | |
387 | .num_resources = ARRAY_SIZE(i2c0_resources), | |
388 | }; | |
389 | ||
390 | static struct platform_device i2c1_device = { | |
391 | .name = "i2c-sh_mobile", | |
392 | .id = 1, | |
393 | .resource = i2c1_resources, | |
394 | .num_resources = ARRAY_SIZE(i2c1_resources), | |
395 | }; | |
396 | ||
397 | static struct platform_device i2c2_device = { | |
398 | .name = "i2c-sh_mobile", | |
399 | .id = 2, | |
400 | .resource = i2c2_resources, | |
401 | .num_resources = ARRAY_SIZE(i2c2_resources), | |
402 | }; | |
403 | ||
404 | static struct platform_device i2c3_device = { | |
405 | .name = "i2c-sh_mobile", | |
406 | .id = 3, | |
407 | .resource = i2c3_resources, | |
408 | .num_resources = ARRAY_SIZE(i2c3_resources), | |
409 | }; | |
410 | ||
411 | static struct platform_device i2c4_device = { | |
412 | .name = "i2c-sh_mobile", | |
413 | .id = 4, | |
414 | .resource = i2c4_resources, | |
415 | .num_resources = ARRAY_SIZE(i2c4_resources), | |
416 | }; | |
417 | ||
681e1b3e MD |
418 | /* Transmit sizes and respective CHCR register values */ |
419 | enum { | |
420 | XMIT_SZ_8BIT = 0, | |
421 | XMIT_SZ_16BIT = 1, | |
422 | XMIT_SZ_32BIT = 2, | |
423 | XMIT_SZ_64BIT = 7, | |
424 | XMIT_SZ_128BIT = 3, | |
425 | XMIT_SZ_256BIT = 4, | |
426 | XMIT_SZ_512BIT = 5, | |
427 | }; | |
428 | ||
429 | /* log2(size / 8) - used to calculate number of transfers */ | |
430 | #define TS_SHIFT { \ | |
431 | [XMIT_SZ_8BIT] = 0, \ | |
432 | [XMIT_SZ_16BIT] = 1, \ | |
433 | [XMIT_SZ_32BIT] = 2, \ | |
434 | [XMIT_SZ_64BIT] = 3, \ | |
435 | [XMIT_SZ_128BIT] = 4, \ | |
436 | [XMIT_SZ_256BIT] = 5, \ | |
437 | [XMIT_SZ_512BIT] = 6, \ | |
438 | } | |
439 | ||
440 | #define TS_INDEX2VAL(i) ((((i) & 3) << 3) | (((i) & 0xc) << (20 - 2))) | |
441 | #define CHCR_TX(xmit_sz) (DM_FIX | SM_INC | 0x800 | TS_INDEX2VAL((xmit_sz))) | |
442 | #define CHCR_RX(xmit_sz) (DM_INC | SM_FIX | 0x800 | TS_INDEX2VAL((xmit_sz))) | |
443 | ||
444 | static const struct sh_dmae_slave_config sh73a0_dmae_slaves[] = { | |
445 | { | |
446 | .slave_id = SHDMA_SLAVE_SCIF0_TX, | |
447 | .addr = 0xe6c40020, | |
448 | .chcr = CHCR_TX(XMIT_SZ_8BIT), | |
449 | .mid_rid = 0x21, | |
450 | }, { | |
451 | .slave_id = SHDMA_SLAVE_SCIF0_RX, | |
452 | .addr = 0xe6c40024, | |
453 | .chcr = CHCR_RX(XMIT_SZ_8BIT), | |
454 | .mid_rid = 0x22, | |
455 | }, { | |
456 | .slave_id = SHDMA_SLAVE_SCIF1_TX, | |
457 | .addr = 0xe6c50020, | |
458 | .chcr = CHCR_TX(XMIT_SZ_8BIT), | |
459 | .mid_rid = 0x25, | |
460 | }, { | |
461 | .slave_id = SHDMA_SLAVE_SCIF1_RX, | |
462 | .addr = 0xe6c50024, | |
463 | .chcr = CHCR_RX(XMIT_SZ_8BIT), | |
464 | .mid_rid = 0x26, | |
465 | }, { | |
466 | .slave_id = SHDMA_SLAVE_SCIF2_TX, | |
467 | .addr = 0xe6c60020, | |
468 | .chcr = CHCR_TX(XMIT_SZ_8BIT), | |
469 | .mid_rid = 0x29, | |
470 | }, { | |
471 | .slave_id = SHDMA_SLAVE_SCIF2_RX, | |
472 | .addr = 0xe6c60024, | |
473 | .chcr = CHCR_RX(XMIT_SZ_8BIT), | |
474 | .mid_rid = 0x2a, | |
475 | }, { | |
476 | .slave_id = SHDMA_SLAVE_SCIF3_TX, | |
477 | .addr = 0xe6c70020, | |
478 | .chcr = CHCR_TX(XMIT_SZ_8BIT), | |
479 | .mid_rid = 0x2d, | |
480 | }, { | |
481 | .slave_id = SHDMA_SLAVE_SCIF3_RX, | |
482 | .addr = 0xe6c70024, | |
483 | .chcr = CHCR_RX(XMIT_SZ_8BIT), | |
484 | .mid_rid = 0x2e, | |
485 | }, { | |
486 | .slave_id = SHDMA_SLAVE_SCIF4_TX, | |
487 | .addr = 0xe6c80020, | |
488 | .chcr = CHCR_TX(XMIT_SZ_8BIT), | |
489 | .mid_rid = 0x39, | |
490 | }, { | |
491 | .slave_id = SHDMA_SLAVE_SCIF4_RX, | |
492 | .addr = 0xe6c80024, | |
493 | .chcr = CHCR_RX(XMIT_SZ_8BIT), | |
494 | .mid_rid = 0x3a, | |
495 | }, { | |
496 | .slave_id = SHDMA_SLAVE_SCIF5_TX, | |
497 | .addr = 0xe6cb0020, | |
498 | .chcr = CHCR_TX(XMIT_SZ_8BIT), | |
499 | .mid_rid = 0x35, | |
500 | }, { | |
501 | .slave_id = SHDMA_SLAVE_SCIF5_RX, | |
502 | .addr = 0xe6cb0024, | |
503 | .chcr = CHCR_RX(XMIT_SZ_8BIT), | |
504 | .mid_rid = 0x36, | |
505 | }, { | |
506 | .slave_id = SHDMA_SLAVE_SCIF6_TX, | |
507 | .addr = 0xe6cc0020, | |
508 | .chcr = CHCR_TX(XMIT_SZ_8BIT), | |
509 | .mid_rid = 0x1d, | |
510 | }, { | |
511 | .slave_id = SHDMA_SLAVE_SCIF6_RX, | |
512 | .addr = 0xe6cc0024, | |
513 | .chcr = CHCR_RX(XMIT_SZ_8BIT), | |
514 | .mid_rid = 0x1e, | |
515 | }, { | |
516 | .slave_id = SHDMA_SLAVE_SCIF7_TX, | |
517 | .addr = 0xe6cd0020, | |
518 | .chcr = CHCR_TX(XMIT_SZ_8BIT), | |
519 | .mid_rid = 0x19, | |
520 | }, { | |
521 | .slave_id = SHDMA_SLAVE_SCIF7_RX, | |
522 | .addr = 0xe6cd0024, | |
523 | .chcr = CHCR_RX(XMIT_SZ_8BIT), | |
524 | .mid_rid = 0x1a, | |
525 | }, { | |
526 | .slave_id = SHDMA_SLAVE_SCIF8_TX, | |
527 | .addr = 0xe6c30040, | |
528 | .chcr = CHCR_TX(XMIT_SZ_8BIT), | |
529 | .mid_rid = 0x3d, | |
530 | }, { | |
531 | .slave_id = SHDMA_SLAVE_SCIF8_RX, | |
532 | .addr = 0xe6c30060, | |
533 | .chcr = CHCR_RX(XMIT_SZ_8BIT), | |
534 | .mid_rid = 0x3e, | |
535 | }, { | |
536 | .slave_id = SHDMA_SLAVE_SDHI0_TX, | |
537 | .addr = 0xee100030, | |
538 | .chcr = CHCR_TX(XMIT_SZ_16BIT), | |
539 | .mid_rid = 0xc1, | |
540 | }, { | |
541 | .slave_id = SHDMA_SLAVE_SDHI0_RX, | |
542 | .addr = 0xee100030, | |
543 | .chcr = CHCR_RX(XMIT_SZ_16BIT), | |
544 | .mid_rid = 0xc2, | |
545 | }, { | |
546 | .slave_id = SHDMA_SLAVE_SDHI1_TX, | |
547 | .addr = 0xee120030, | |
548 | .chcr = CHCR_TX(XMIT_SZ_16BIT), | |
549 | .mid_rid = 0xc9, | |
550 | }, { | |
551 | .slave_id = SHDMA_SLAVE_SDHI1_RX, | |
552 | .addr = 0xee120030, | |
553 | .chcr = CHCR_RX(XMIT_SZ_16BIT), | |
554 | .mid_rid = 0xca, | |
555 | }, { | |
556 | .slave_id = SHDMA_SLAVE_SDHI2_TX, | |
557 | .addr = 0xee140030, | |
558 | .chcr = CHCR_TX(XMIT_SZ_16BIT), | |
559 | .mid_rid = 0xcd, | |
560 | }, { | |
561 | .slave_id = SHDMA_SLAVE_SDHI2_RX, | |
562 | .addr = 0xee140030, | |
563 | .chcr = CHCR_RX(XMIT_SZ_16BIT), | |
564 | .mid_rid = 0xce, | |
565 | }, { | |
566 | .slave_id = SHDMA_SLAVE_MMCIF_TX, | |
567 | .addr = 0xe6bd0034, | |
568 | .chcr = CHCR_TX(XMIT_SZ_32BIT), | |
569 | .mid_rid = 0xd1, | |
570 | }, { | |
571 | .slave_id = SHDMA_SLAVE_MMCIF_RX, | |
572 | .addr = 0xe6bd0034, | |
573 | .chcr = CHCR_RX(XMIT_SZ_32BIT), | |
574 | .mid_rid = 0xd2, | |
575 | }, | |
576 | }; | |
577 | ||
578 | #define DMAE_CHANNEL(_offset) \ | |
579 | { \ | |
580 | .offset = _offset - 0x20, \ | |
581 | .dmars = _offset - 0x20 + 0x40, \ | |
582 | } | |
583 | ||
584 | static const struct sh_dmae_channel sh73a0_dmae_channels[] = { | |
585 | DMAE_CHANNEL(0x8000), | |
586 | DMAE_CHANNEL(0x8080), | |
587 | DMAE_CHANNEL(0x8100), | |
588 | DMAE_CHANNEL(0x8180), | |
589 | DMAE_CHANNEL(0x8200), | |
590 | DMAE_CHANNEL(0x8280), | |
591 | DMAE_CHANNEL(0x8300), | |
592 | DMAE_CHANNEL(0x8380), | |
593 | DMAE_CHANNEL(0x8400), | |
594 | DMAE_CHANNEL(0x8480), | |
595 | DMAE_CHANNEL(0x8500), | |
596 | DMAE_CHANNEL(0x8580), | |
597 | DMAE_CHANNEL(0x8600), | |
598 | DMAE_CHANNEL(0x8680), | |
599 | DMAE_CHANNEL(0x8700), | |
600 | DMAE_CHANNEL(0x8780), | |
601 | DMAE_CHANNEL(0x8800), | |
602 | DMAE_CHANNEL(0x8880), | |
603 | DMAE_CHANNEL(0x8900), | |
604 | DMAE_CHANNEL(0x8980), | |
605 | }; | |
606 | ||
607 | static const unsigned int ts_shift[] = TS_SHIFT; | |
608 | ||
609 | static struct sh_dmae_pdata sh73a0_dmae_platform_data = { | |
610 | .slave = sh73a0_dmae_slaves, | |
611 | .slave_num = ARRAY_SIZE(sh73a0_dmae_slaves), | |
612 | .channel = sh73a0_dmae_channels, | |
613 | .channel_num = ARRAY_SIZE(sh73a0_dmae_channels), | |
614 | .ts_low_shift = 3, | |
615 | .ts_low_mask = 0x18, | |
616 | .ts_high_shift = (20 - 2), /* 2 bits for shifted low TS */ | |
617 | .ts_high_mask = 0x00300000, | |
618 | .ts_shift = ts_shift, | |
619 | .ts_shift_num = ARRAY_SIZE(ts_shift), | |
620 | .dmaor_init = DMAOR_DME, | |
621 | }; | |
622 | ||
623 | static struct resource sh73a0_dmae_resources[] = { | |
624 | { | |
625 | /* Registers including DMAOR and channels including DMARSx */ | |
626 | .start = 0xfe000020, | |
627 | .end = 0xfe008a00 - 1, | |
628 | .flags = IORESOURCE_MEM, | |
629 | }, | |
630 | { | |
20052462 | 631 | .name = "error_irq", |
681e1b3e MD |
632 | .start = gic_spi(129), |
633 | .end = gic_spi(129), | |
634 | .flags = IORESOURCE_IRQ, | |
635 | }, | |
636 | { | |
637 | /* IRQ for channels 0-19 */ | |
638 | .start = gic_spi(109), | |
639 | .end = gic_spi(128), | |
640 | .flags = IORESOURCE_IRQ, | |
641 | }, | |
642 | }; | |
643 | ||
644 | static struct platform_device dma0_device = { | |
645 | .name = "sh-dma-engine", | |
646 | .id = 0, | |
647 | .resource = sh73a0_dmae_resources, | |
648 | .num_resources = ARRAY_SIZE(sh73a0_dmae_resources), | |
649 | .dev = { | |
650 | .platform_data = &sh73a0_dmae_platform_data, | |
651 | }, | |
652 | }; | |
653 | ||
6d9598e2 MD |
654 | static struct platform_device *sh73a0_early_devices[] __initdata = { |
655 | &scif0_device, | |
656 | &scif1_device, | |
657 | &scif2_device, | |
658 | &scif3_device, | |
659 | &scif4_device, | |
660 | &scif5_device, | |
661 | &scif6_device, | |
662 | &scif7_device, | |
663 | &scif8_device, | |
664 | &cmt10_device, | |
5010f3db MD |
665 | &tmu00_device, |
666 | &tmu01_device, | |
6d9598e2 MD |
667 | }; |
668 | ||
b028f94b YT |
669 | static struct platform_device *sh73a0_late_devices[] __initdata = { |
670 | &i2c0_device, | |
671 | &i2c1_device, | |
672 | &i2c2_device, | |
673 | &i2c3_device, | |
674 | &i2c4_device, | |
681e1b3e | 675 | &dma0_device, |
b028f94b YT |
676 | }; |
677 | ||
681e1b3e MD |
678 | #define SRCR2 0xe61580b0 |
679 | ||
6d9598e2 MD |
680 | void __init sh73a0_add_standard_devices(void) |
681 | { | |
681e1b3e MD |
682 | /* Clear software reset bit on SY-DMAC module */ |
683 | __raw_writel(__raw_readl(SRCR2) & ~(1 << 18), SRCR2); | |
684 | ||
6d9598e2 MD |
685 | platform_add_devices(sh73a0_early_devices, |
686 | ARRAY_SIZE(sh73a0_early_devices)); | |
b028f94b YT |
687 | platform_add_devices(sh73a0_late_devices, |
688 | ARRAY_SIZE(sh73a0_late_devices)); | |
6d9598e2 MD |
689 | } |
690 | ||
d6720003 KM |
691 | /* do nothing for !CONFIG_SMP or !CONFIG_HAVE_TWD */ |
692 | void __init __weak sh73a0_register_twd(void) { } | |
693 | ||
3be26fdb MD |
694 | static void __init sh73a0_earlytimer_init(void) |
695 | { | |
696 | sh73a0_clock_init(); | |
697 | shmobile_earlytimer_init(); | |
d6720003 | 698 | sh73a0_register_twd(); |
3be26fdb MD |
699 | } |
700 | ||
6d9598e2 MD |
701 | void __init sh73a0_add_early_devices(void) |
702 | { | |
703 | early_platform_add_devices(sh73a0_early_devices, | |
704 | ARRAY_SIZE(sh73a0_early_devices)); | |
50e15c34 MD |
705 | |
706 | /* setup early console here as well */ | |
707 | shmobile_setup_console(); | |
3be26fdb MD |
708 | |
709 | /* override timer setup with soc-specific code */ | |
710 | shmobile_timer.init = sh73a0_earlytimer_init; | |
6d9598e2 | 711 | } |