projects / deliverable / linux.git / blame
| Commit | Line | Data |
|---|---|---|
| ad09cb83 MD |
1 | /* |
| 2 | * SMP support for r8a7790 | |
| 3 | * | |
| 4 | * Copyright (C) 2012-2013 Renesas Solutions Corp. | |
| 5 | * Copyright (C) 2012 Takashi Yoshii <takashi.yoshii.ze@renesas.com> | |
| 6 | * | |
| 7 | * This program is free software; you can redistribute it and/or modify | |
| 8 | * it under the terms of the GNU General Public License as published by | |
| 9 | * the Free Software Foundation; version 2 of the License. | |
| 10 | * | |
| 11 | * This program is distributed in the hope that it will be useful, | |
| 12 | * but WITHOUT ANY WARRANTY; without even the implied warranty of | |
| 13 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
| 14 | * GNU General Public License for more details. | |
| 15 | */ | |
| 16 | #include <linux/kernel.h> | |
| 17 | #include <linux/init.h> | |
| 18 | #include <linux/smp.h> | |
| 19 | #include <linux/io.h> | |
| 20 | #include <asm/smp_plat.h> | |
| 0445ded6 GI |
21 | #include <mach/pm-rcar.h> |
| 22 | #include <mach/r8a7790.h> | |
| fd44aa5e | 23 | #include "common.h" |
| ad09cb83 MD |
24 | |
| 25 | #define RST 0xe6160000 | |
| 26 | #define CA15BAR 0x0020 | |
| 27 | #define CA7BAR 0x0030 | |
| 28 | #define CA15RESCNT 0x0040 | |
| 29 | #define CA7RESCNT 0x0044 | |
| 30 | #define MERAM 0xe8080000 | |
| 31 | ||
| c2c97ec5 KK |
32 | static struct rcar_sysc_ch r8a7790_ca15_scu = { |
| 33 | .chan_offs = 0x180, /* PWRSR5 .. PWRER5 */ | |
| 34 | .isr_bit = 12, /* CA15-SCU */ | |
| 35 | }; | |
| 36 | ||
| 0445ded6 GI |
37 | static struct rcar_sysc_ch r8a7790_ca7_scu = { |
| 38 | .chan_offs = 0x100, /* PWRSR3 .. PWRER3 */ | |
| 39 | .isr_bit = 21, /* CA7-SCU */ | |
| 40 | }; | |
| 41 | ||
| ad09cb83 MD |
42 | static void __init r8a7790_smp_prepare_cpus(unsigned int max_cpus) |
| 43 | { | |
| 44 | void __iomem *p; | |
| 45 | u32 bar; | |
| 46 | ||
| 47 | /* let APMU code install data related to shmobile_boot_vector */ | |
| 48 | shmobile_smp_apmu_prepare_cpus(max_cpus); | |
| 49 | ||
| 50 | /* MERAM for jump stub, because BAR requires 256KB aligned address */ | |
| 51 | p = ioremap_nocache(MERAM, shmobile_boot_size); | |
| 52 | memcpy_toio(p, shmobile_boot_vector, shmobile_boot_size); | |
| 53 | iounmap(p); | |
| 54 | ||
| 55 | /* setup reset vectors */ | |
| 56 | p = ioremap_nocache(RST, 0x63); | |
| 57 | bar = (MERAM >> 8) & 0xfffffc00; | |
| 58 | writel_relaxed(bar, p + CA15BAR); | |
| 59 | writel_relaxed(bar, p + CA7BAR); | |
| 60 | writel_relaxed(bar | 0x10, p + CA15BAR); | |
| 61 | writel_relaxed(bar | 0x10, p + CA7BAR); | |
| 62 | ||
| 63 | /* enable clocks to all CPUs */ | |
| 64 | writel_relaxed((readl_relaxed(p + CA15RESCNT) & ~0x0f) | 0xa5a50000, | |
| 65 | p + CA15RESCNT); | |
| 66 | writel_relaxed((readl_relaxed(p + CA7RESCNT) & ~0x0f) | 0x5a5a0000, | |
| 67 | p + CA7RESCNT); | |
| 68 | iounmap(p); | |
| 0445ded6 GI |
69 | |
| 70 | /* turn on power to SCU */ | |
| 71 | r8a7790_pm_init(); | |
| c2c97ec5 | 72 | rcar_sysc_power_up(&r8a7790_ca15_scu); |
| 0445ded6 | 73 | rcar_sysc_power_up(&r8a7790_ca7_scu); |
| ad09cb83 MD |
74 | } |
| 75 | ||
| 76 | struct smp_operations r8a7790_smp_ops __initdata = { | |
| 77 | .smp_prepare_cpus = r8a7790_smp_prepare_cpus, | |
| 78 | .smp_boot_secondary = shmobile_smp_apmu_boot_secondary, | |
| 79 | #ifdef CONFIG_HOTPLUG_CPU | |
| 80 | .cpu_disable = shmobile_smp_cpu_disable, | |
| 81 | .cpu_die = shmobile_smp_apmu_cpu_die, | |
| 82 | .cpu_kill = shmobile_smp_apmu_cpu_kill, | |
| 83 | #endif | |
| 84 | }; |