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66314223 DN |
1 | /* |
2 | * Copyright (C) 2012 Altera Corporation | |
3 | * | |
4 | * This program is free software; you can redistribute it and/or modify | |
5 | * it under the terms of the GNU General Public License as published by | |
6 | * the Free Software Foundation; either version 2 of the License, or | |
7 | * (at your option) any later version. | |
8 | * | |
9 | * This program is distributed in the hope that it will be useful, | |
10 | * but WITHOUT ANY WARRANTY; without even the implied warranty of | |
11 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
12 | * GNU General Public License for more details. | |
13 | * | |
14 | * You should have received a copy of the GNU General Public License | |
15 | * along with this program. If not, see <http://www.gnu.org/licenses/>. | |
16 | */ | |
0529e315 | 17 | #include <linux/irqchip.h> |
9c4566a1 | 18 | #include <linux/of_address.h> |
66314223 DN |
19 | #include <linux/of_irq.h> |
20 | #include <linux/of_platform.h> | |
7b6d864b | 21 | #include <linux/reboot.h> |
66314223 DN |
22 | |
23 | #include <asm/hardware/cache-l2x0.h> | |
66314223 | 24 | #include <asm/mach/arch.h> |
9c4566a1 | 25 | #include <asm/mach/map.h> |
cee9b8d6 | 26 | #include <asm/cacheflush.h> |
66314223 | 27 | |
9c4566a1 DN |
28 | #include "core.h" |
29 | ||
9c4566a1 DN |
30 | void __iomem *sys_manager_base_addr; |
31 | void __iomem *rst_manager_base_addr; | |
3a4356c0 | 32 | unsigned long socfpga_cpu1start_addr; |
9c4566a1 | 33 | |
9c4566a1 DN |
34 | void __init socfpga_sysmgr_init(void) |
35 | { | |
36 | struct device_node *np; | |
37 | ||
38 | np = of_find_compatible_node(NULL, NULL, "altr,sys-mgr"); | |
d6dd735f DN |
39 | |
40 | if (of_property_read_u32(np, "cpu1-start-addr", | |
3a4356c0 | 41 | (u32 *) &socfpga_cpu1start_addr)) |
d6dd735f DN |
42 | pr_err("SMP: Need cpu1-start-addr in device tree.\n"); |
43 | ||
cee9b8d6 RK |
44 | /* Ensure that socfpga_cpu1start_addr is visible to other CPUs */ |
45 | smp_wmb(); | |
46 | sync_cache_w(&socfpga_cpu1start_addr); | |
47 | ||
9c4566a1 DN |
48 | sys_manager_base_addr = of_iomap(np, 0); |
49 | ||
50 | np = of_find_compatible_node(NULL, NULL, "altr,rst-mgr"); | |
51 | rst_manager_base_addr = of_iomap(np, 0); | |
52 | } | |
53 | ||
0529e315 | 54 | static void __init socfpga_init_irq(void) |
66314223 | 55 | { |
0529e315 | 56 | irqchip_init(); |
9c4566a1 | 57 | socfpga_sysmgr_init(); |
66314223 DN |
58 | } |
59 | ||
7b6d864b | 60 | static void socfpga_cyclone5_restart(enum reboot_mode mode, const char *cmd) |
66314223 | 61 | { |
5c04b57f DN |
62 | u32 temp; |
63 | ||
64 | temp = readl(rst_manager_base_addr + SOCFPGA_RSTMGR_CTRL); | |
65 | ||
7b6d864b | 66 | if (mode == REBOOT_HARD) |
5c04b57f DN |
67 | temp |= RSTMGR_CTRL_SWCOLDRSTREQ; |
68 | else | |
69 | temp |= RSTMGR_CTRL_SWWARMRSTREQ; | |
70 | writel(temp, rst_manager_base_addr + SOCFPGA_RSTMGR_CTRL); | |
66314223 DN |
71 | } |
72 | ||
66314223 DN |
73 | static const char *altera_dt_match[] = { |
74 | "altr,socfpga", | |
66314223 DN |
75 | NULL |
76 | }; | |
77 | ||
78 | DT_MACHINE_START(SOCFPGA, "Altera SOCFPGA") | |
8b5c18f0 RK |
79 | .l2c_aux_val = 0, |
80 | .l2c_aux_mask = ~0, | |
0529e315 | 81 | .init_irq = socfpga_init_irq, |
66314223 DN |
82 | .restart = socfpga_cyclone5_restart, |
83 | .dt_compat = altera_dt_match, | |
84 | MACHINE_END |