Commit | Line | Data |
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66314223 | 1 | /* |
44fd8c7d | 2 | * Copyright (C) 2012-2015 Altera Corporation |
66314223 DN |
3 | * |
4 | * This program is free software; you can redistribute it and/or modify | |
5 | * it under the terms of the GNU General Public License as published by | |
6 | * the Free Software Foundation; either version 2 of the License, or | |
7 | * (at your option) any later version. | |
8 | * | |
9 | * This program is distributed in the hope that it will be useful, | |
10 | * but WITHOUT ANY WARRANTY; without even the implied warranty of | |
11 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
12 | * GNU General Public License for more details. | |
13 | * | |
14 | * You should have received a copy of the GNU General Public License | |
15 | * along with this program. If not, see <http://www.gnu.org/licenses/>. | |
16 | */ | |
0529e315 | 17 | #include <linux/irqchip.h> |
9c4566a1 | 18 | #include <linux/of_address.h> |
66314223 DN |
19 | #include <linux/of_irq.h> |
20 | #include <linux/of_platform.h> | |
7b6d864b | 21 | #include <linux/reboot.h> |
66314223 DN |
22 | |
23 | #include <asm/hardware/cache-l2x0.h> | |
66314223 | 24 | #include <asm/mach/arch.h> |
9c4566a1 | 25 | #include <asm/mach/map.h> |
cee9b8d6 | 26 | #include <asm/cacheflush.h> |
66314223 | 27 | |
9c4566a1 DN |
28 | #include "core.h" |
29 | ||
9c4566a1 DN |
30 | void __iomem *sys_manager_base_addr; |
31 | void __iomem *rst_manager_base_addr; | |
44fd8c7d | 32 | void __iomem *sdr_ctl_base_addr; |
3a4356c0 | 33 | unsigned long socfpga_cpu1start_addr; |
9c4566a1 | 34 | |
9c4566a1 DN |
35 | void __init socfpga_sysmgr_init(void) |
36 | { | |
37 | struct device_node *np; | |
38 | ||
39 | np = of_find_compatible_node(NULL, NULL, "altr,sys-mgr"); | |
d6dd735f DN |
40 | |
41 | if (of_property_read_u32(np, "cpu1-start-addr", | |
3a4356c0 | 42 | (u32 *) &socfpga_cpu1start_addr)) |
d6dd735f DN |
43 | pr_err("SMP: Need cpu1-start-addr in device tree.\n"); |
44 | ||
cee9b8d6 RK |
45 | /* Ensure that socfpga_cpu1start_addr is visible to other CPUs */ |
46 | smp_wmb(); | |
47 | sync_cache_w(&socfpga_cpu1start_addr); | |
48 | ||
9c4566a1 DN |
49 | sys_manager_base_addr = of_iomap(np, 0); |
50 | ||
51 | np = of_find_compatible_node(NULL, NULL, "altr,rst-mgr"); | |
52 | rst_manager_base_addr = of_iomap(np, 0); | |
44fd8c7d AT |
53 | |
54 | np = of_find_compatible_node(NULL, NULL, "altr,sdr-ctl"); | |
55 | sdr_ctl_base_addr = of_iomap(np, 0); | |
9c4566a1 DN |
56 | } |
57 | ||
0529e315 | 58 | static void __init socfpga_init_irq(void) |
66314223 | 59 | { |
0529e315 | 60 | irqchip_init(); |
9c4566a1 | 61 | socfpga_sysmgr_init(); |
4d113838 TT |
62 | if (IS_ENABLED(CONFIG_EDAC_ALTERA_L2C)) |
63 | socfpga_init_l2_ecc(); | |
7cc5a5d3 TT |
64 | |
65 | if (IS_ENABLED(CONFIG_EDAC_ALTERA_OCRAM)) | |
66 | socfpga_init_ocram_ecc(); | |
66314223 DN |
67 | } |
68 | ||
ff6fd147 TT |
69 | static void __init socfpga_arria10_init_irq(void) |
70 | { | |
71 | irqchip_init(); | |
72 | socfpga_sysmgr_init(); | |
73 | if (IS_ENABLED(CONFIG_EDAC_ALTERA_L2C)) | |
74 | socfpga_init_arria10_l2_ecc(); | |
c5fb04cc TT |
75 | if (IS_ENABLED(CONFIG_EDAC_ALTERA_OCRAM)) |
76 | socfpga_init_arria10_ocram_ecc(); | |
ff6fd147 TT |
77 | } |
78 | ||
7b6d864b | 79 | static void socfpga_cyclone5_restart(enum reboot_mode mode, const char *cmd) |
66314223 | 80 | { |
5c04b57f DN |
81 | u32 temp; |
82 | ||
83 | temp = readl(rst_manager_base_addr + SOCFPGA_RSTMGR_CTRL); | |
84 | ||
7b6d864b | 85 | if (mode == REBOOT_HARD) |
5c04b57f DN |
86 | temp |= RSTMGR_CTRL_SWCOLDRSTREQ; |
87 | else | |
88 | temp |= RSTMGR_CTRL_SWWARMRSTREQ; | |
89 | writel(temp, rst_manager_base_addr + SOCFPGA_RSTMGR_CTRL); | |
66314223 DN |
90 | } |
91 | ||
cd871d51 DN |
92 | static void socfpga_arria10_restart(enum reboot_mode mode, const char *cmd) |
93 | { | |
94 | u32 temp; | |
95 | ||
96 | temp = readl(rst_manager_base_addr + SOCFPGA_A10_RSTMGR_CTRL); | |
97 | ||
98 | if (mode == REBOOT_HARD) | |
99 | temp |= RSTMGR_CTRL_SWCOLDRSTREQ; | |
100 | else | |
101 | temp |= RSTMGR_CTRL_SWWARMRSTREQ; | |
102 | writel(temp, rst_manager_base_addr + SOCFPGA_A10_RSTMGR_CTRL); | |
103 | } | |
104 | ||
66314223 DN |
105 | static const char *altera_dt_match[] = { |
106 | "altr,socfpga", | |
66314223 DN |
107 | NULL |
108 | }; | |
109 | ||
110 | DT_MACHINE_START(SOCFPGA, "Altera SOCFPGA") | |
8b5c18f0 RK |
111 | .l2c_aux_val = 0, |
112 | .l2c_aux_mask = ~0, | |
0529e315 | 113 | .init_irq = socfpga_init_irq, |
66314223 DN |
114 | .restart = socfpga_cyclone5_restart, |
115 | .dt_compat = altera_dt_match, | |
116 | MACHINE_END | |
cd871d51 DN |
117 | |
118 | static const char *altera_a10_dt_match[] = { | |
119 | "altr,socfpga-arria10", | |
120 | NULL | |
121 | }; | |
122 | ||
123 | DT_MACHINE_START(SOCFPGA_A10, "Altera SOCFPGA Arria10") | |
124 | .l2c_aux_val = 0, | |
125 | .l2c_aux_mask = ~0, | |
ff6fd147 | 126 | .init_irq = socfpga_arria10_init_irq, |
cd871d51 DN |
127 | .restart = socfpga_arria10_restart, |
128 | .dt_compat = altera_a10_dt_match, | |
129 | MACHINE_END |