[deliverable/linux.git] / arch / arm / mach-spear / spear3xx.c

/*
 * arch/arm/mach-spear3xx/spear3xx.c
 *
 * SPEAr3XX machines common source file
 *
 * Copyright (C) 2009-2012 ST Microelectronics
 * Viresh Kumar <vireshk@kernel.org>
 *
 * This file is licensed under the terms of the GNU General Public
 * License version 2. This program is licensed "as is" without any
 * warranty of any kind, whether express or implied.
 */

#define pr_fmt(fmt) "SPEAr3xx: " fmt

#include <linux/amba/pl022.h>
#include <linux/amba/pl080.h>
#include <linux/clk.h>
#include <linux/io.h>
#include <asm/mach/map.h>
#include "pl080.h"
#include "generic.h"
#include <mach/spear.h>
#include <mach/misc_regs.h>

/* ssp device registration */
struct pl022_ssp_controller pl022_plat_data = {
	.bus_id = 0,
	.enable_dma = 1,
	.dma_filter = pl08x_filter_id,
	.dma_tx_param = "ssp0_tx",
	.dma_rx_param = "ssp0_rx",
	/*
	 * This is number of spi devices that can be connected to spi. There are
	 * two type of chipselects on which slave devices can work. One is chip
	 * select provided by spi masters other is controlled through external
	 * gpio's. We can't use chipselect provided from spi master (because as
	 * soon as FIFO becomes empty, CS is disabled and transfer ends). So
	 * this number now depends on number of gpios available for spi. each
	 * slave on each master requires a separate gpio pin.
	 */
	.num_chipselect = 2,
};

/* dmac device registration */
struct pl08x_platform_data pl080_plat_data = {
	.memcpy_channel = {
		.bus_id = "memcpy",
		.cctl_memcpy =
			(PL080_BSIZE_16 << PL080_CONTROL_SB_SIZE_SHIFT | \
			PL080_BSIZE_16 << PL080_CONTROL_DB_SIZE_SHIFT | \
			PL080_WIDTH_32BIT << PL080_CONTROL_SWIDTH_SHIFT | \
			PL080_WIDTH_32BIT << PL080_CONTROL_DWIDTH_SHIFT | \
			PL080_CONTROL_PROT_BUFF | PL080_CONTROL_PROT_CACHE | \
			PL080_CONTROL_PROT_SYS),
	},
	.lli_buses = PL08X_AHB1,
	.mem_buses = PL08X_AHB1,
	.get_xfer_signal = pl080_get_signal,
	.put_xfer_signal = pl080_put_signal,
};

/*
 * Following will create 16MB static virtual/physical mappings
 * PHYSICAL		VIRTUAL
 * 0xD0000000		0xFD000000
 * 0xFC000000		0xFC000000
 */
struct map_desc spear3xx_io_desc[] __initdata = {
	{
		.virtual	= (unsigned long)VA_SPEAR_ICM1_2_BASE,
		.pfn		= __phys_to_pfn(SPEAR_ICM1_2_BASE),
		.length		= SZ_16M,
		.type		= MT_DEVICE
	}, {
		.virtual	= (unsigned long)VA_SPEAR_ICM3_SMI_CTRL_BASE,
		.pfn		= __phys_to_pfn(SPEAR_ICM3_SMI_CTRL_BASE),
		.length		= SZ_16M,
		.type		= MT_DEVICE
	},
};

/* This will create static memory mapping for selected devices */
void __init spear3xx_map_io(void)
{
	iotable_init(spear3xx_io_desc, ARRAY_SIZE(spear3xx_io_desc));
}

void __init spear3xx_timer_init(void)
{
	char pclk_name[] = "pll3_clk";
	struct clk *gpt_clk, *pclk;

	spear3xx_clk_init(MISC_BASE, VA_SPEAR320_SOC_CONFIG_BASE);

	/* get the system timer clock */
	gpt_clk = clk_get_sys("gpt0", NULL);
	if (IS_ERR(gpt_clk)) {
		pr_err("%s:couldn't get clk for gpt\n", __func__);
		BUG();
	}

	/* get the suitable parent clock for timer*/
	pclk = clk_get(NULL, pclk_name);
	if (IS_ERR(pclk)) {
		pr_err("%s:couldn't get %s as parent for gpt\n",
				__func__, pclk_name);
		BUG();
	}

	clk_set_parent(gpt_clk, pclk);
	clk_put(gpt_clk);
	clk_put(pclk);

	spear_setup_of_timer();
}
Commit	Line	Data
bc4e814e	1	/*
	2	* arch/arm/mach-spear3xx/spear3xx.c
	3	*
	4	* SPEAr3XX machines common source file
	5	*
c5fa4fdc	6	* Copyright (C) 2009-2012 ST Microelectronics
da89947b	7	* Viresh Kumar <vireshk@kernel.org>
bc4e814e	8	*
	9	* This file is licensed under the terms of the GNU General Public
	10	* License version 2. This program is licensed "as is" without any
	11	* warranty of any kind, whether express or implied.
	12	*/
	13
5fb00f96 VK	14	#define pr_fmt(fmt) "SPEAr3xx: " fmt
5fb00f96 VK	15
c5fa4fdc	16	#include <linux/amba/pl022.h>
54475210 AB	17	#include <linux/amba/pl080.h>
54475210 AB	18	#include <linux/clk.h>
bc4e814e	19	#include <linux/io.h>
54475210	20	#include <asm/mach/map.h>
2b9c613c AB	21	#include "pl080.h"
2b9c613c AB	22	#include "generic.h"
5019f0b1	23	#include <mach/spear.h>
d9909ebe	24	#include <mach/misc_regs.h>
bc4e814e	25
c5fa4fdc VK	26	/* ssp device registration */
	27	struct pl022_ssp_controller pl022_plat_data = {
	28	.bus_id = 0,
	29	.enable_dma = 1,
	30	.dma_filter = pl08x_filter_id,
	31	.dma_tx_param = "ssp0_tx",
	32	.dma_rx_param = "ssp0_rx",
	33	/*
	34	* This is number of spi devices that can be connected to spi. There are
	35	* two type of chipselects on which slave devices can work. One is chip
	36	* select provided by spi masters other is controlled through external
	37	* gpio's. We can't use chipselect provided from spi master (because as
	38	* soon as FIFO becomes empty, CS is disabled and transfer ends). So
	39	* this number now depends on number of gpios available for spi. each
	40	* slave on each master requires a separate gpio pin.
	41	*/
	42	.num_chipselect = 2,
	43	};
	44
0b7ee717 VK	45	/* dmac device registration */
	46	struct pl08x_platform_data pl080_plat_data = {
	47	.memcpy_channel = {
	48	.bus_id = "memcpy",
dc8d5f8d RK	49	.cctl_memcpy =
dc8d5f8d RK	50	(PL080_BSIZE_16 << PL080_CONTROL_SB_SIZE_SHIFT \| \
0b7ee717 VK	51	PL080_BSIZE_16 << PL080_CONTROL_DB_SIZE_SHIFT \| \
	52	PL080_WIDTH_32BIT << PL080_CONTROL_SWIDTH_SHIFT \| \
	53	PL080_WIDTH_32BIT << PL080_CONTROL_DWIDTH_SHIFT \| \
	54	PL080_CONTROL_PROT_BUFF \| PL080_CONTROL_PROT_CACHE \| \
	55	PL080_CONTROL_PROT_SYS),
	56	},
	57	.lli_buses = PL08X_AHB1,
	58	.mem_buses = PL08X_AHB1,
d7cabeed MB	59	.get_xfer_signal = pl080_get_signal,
d7cabeed MB	60	.put_xfer_signal = pl080_put_signal,
bc4e814e	61	};
bc4e814e	62
c5fa4fdc VK	63	/*
	64	* Following will create 16MB static virtual/physical mappings
	65	* PHYSICAL VIRTUAL
	66	* 0xD0000000 0xFD000000
	67	* 0xFC000000 0xFC000000
	68	*/
bc4e814e	69	struct map_desc spear3xx_io_desc[] __initdata = {
bc4e814e	70	{
d9909ebe	71	.virtual = (unsigned long)VA_SPEAR_ICM1_2_BASE,
d42799b7	72	.pfn = __phys_to_pfn(SPEAR_ICM1_2_BASE),
c5fa4fdc	73	.length = SZ_16M,
bc4e814e	74	.type = MT_DEVICE
bc4e814e	75	}, {
d9909ebe	76	.virtual = (unsigned long)VA_SPEAR_ICM3_SMI_CTRL_BASE,
d42799b7	77	.pfn = __phys_to_pfn(SPEAR_ICM3_SMI_CTRL_BASE),
c5fa4fdc	78	.length = SZ_16M,
bc4e814e	79	.type = MT_DEVICE
	80	},
	81	};
	82
	83	/* This will create static memory mapping for selected devices */
	84	void __init spear3xx_map_io(void)
	85	{
	86	iotable_init(spear3xx_io_desc, ARRAY_SIZE(spear3xx_io_desc));
bc4e814e	87	}
70f4c0bf	88
6bb27d73	89	void __init spear3xx_timer_init(void)
5c881d9a	90	{
5cfc545f	91	char pclk_name[] = "pll3_clk";
5c881d9a SH	92	struct clk gpt_clk, pclk;
5c881d9a SH	93
d9909ebe	94	spear3xx_clk_init(MISC_BASE, VA_SPEAR320_SOC_CONFIG_BASE);
5df33a62	95
5c881d9a SH	96	/* get the system timer clock */
	97	gpt_clk = clk_get_sys("gpt0", NULL);
	98	if (IS_ERR(gpt_clk)) {
	99	pr_err("%s:couldn't get clk for gpt\n", __func__);
	100	BUG();
	101	}
	102
	103	/* get the suitable parent clock for timer*/
	104	pclk = clk_get(NULL, pclk_name);
	105	if (IS_ERR(pclk)) {
	106	pr_err("%s:couldn't get %s as parent for gpt\n",
	107	__func__, pclk_name);
	108	BUG();
	109	}
	110
	111	clk_set_parent(gpt_clk, pclk);
	112	clk_put(gpt_clk);
	113	clk_put(pclk);
	114
30551c01	115	spear_setup_of_timer();
5c881d9a	116	}