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b31e2372 VK |
1 | /* |
2 | * arch/arm/mach-spear13xx/include/mach/dma.h | |
3 | * | |
4 | * DMA information for SPEAr13xx machine family | |
5 | * | |
6 | * Copyright (C) 2012 ST Microelectronics | |
10d8935f | 7 | * Viresh Kumar <viresh.linux@gmail.com> |
b31e2372 VK |
8 | * |
9 | * This file is licensed under the terms of the GNU General Public | |
10 | * License version 2. This program is licensed "as is" without any | |
11 | * warranty of any kind, whether express or implied. | |
12 | */ | |
13 | ||
14 | #ifndef __MACH_DMA_H | |
15 | #define __MACH_DMA_H | |
16 | ||
17 | /* request id of all the peripherals */ | |
18 | enum dma_master_info { | |
19 | /* Accessible from only one master */ | |
20 | DMA_MASTER_MCIF = 0, | |
21 | DMA_MASTER_FSMC = 1, | |
22 | /* Accessible from both 0 & 1 */ | |
23 | DMA_MASTER_MEMORY = 0, | |
24 | DMA_MASTER_ADC = 0, | |
25 | DMA_MASTER_UART0 = 0, | |
26 | DMA_MASTER_SSP0 = 0, | |
27 | DMA_MASTER_I2C0 = 0, | |
28 | ||
29 | #ifdef CONFIG_MACH_SPEAR1310 | |
30 | /* Accessible from only one master */ | |
31 | SPEAR1310_DMA_MASTER_JPEG = 1, | |
32 | ||
33 | /* Accessible from both 0 & 1 */ | |
34 | SPEAR1310_DMA_MASTER_I2S = 0, | |
35 | SPEAR1310_DMA_MASTER_UART1 = 0, | |
36 | SPEAR1310_DMA_MASTER_UART2 = 0, | |
37 | SPEAR1310_DMA_MASTER_UART3 = 0, | |
38 | SPEAR1310_DMA_MASTER_UART4 = 0, | |
39 | SPEAR1310_DMA_MASTER_UART5 = 0, | |
40 | SPEAR1310_DMA_MASTER_I2C1 = 0, | |
41 | SPEAR1310_DMA_MASTER_I2C2 = 0, | |
42 | SPEAR1310_DMA_MASTER_I2C3 = 0, | |
43 | SPEAR1310_DMA_MASTER_I2C4 = 0, | |
44 | SPEAR1310_DMA_MASTER_I2C5 = 0, | |
45 | SPEAR1310_DMA_MASTER_I2C6 = 0, | |
46 | SPEAR1310_DMA_MASTER_I2C7 = 0, | |
47 | SPEAR1310_DMA_MASTER_SSP1 = 0, | |
48 | #endif | |
49 | ||
50 | #ifdef CONFIG_MACH_SPEAR1340 | |
51 | /* Accessible from only one master */ | |
52 | SPEAR1340_DMA_MASTER_I2S_PLAY = 1, | |
53 | SPEAR1340_DMA_MASTER_I2S_REC = 1, | |
54 | SPEAR1340_DMA_MASTER_I2C1 = 1, | |
55 | SPEAR1340_DMA_MASTER_UART1 = 1, | |
56 | ||
57 | /* following are accessible from both master 0 & 1 */ | |
58 | SPEAR1340_DMA_MASTER_SPDIF = 0, | |
59 | SPEAR1340_DMA_MASTER_CAM = 1, | |
60 | SPEAR1340_DMA_MASTER_VIDEO_IN = 0, | |
61 | SPEAR1340_DMA_MASTER_MALI = 0, | |
62 | #endif | |
63 | }; | |
64 | ||
65 | enum request_id { | |
66 | DMA_REQ_ADC = 0, | |
67 | DMA_REQ_SSP0_TX = 4, | |
68 | DMA_REQ_SSP0_RX = 5, | |
69 | DMA_REQ_UART0_TX = 6, | |
70 | DMA_REQ_UART0_RX = 7, | |
71 | DMA_REQ_I2C0_TX = 8, | |
72 | DMA_REQ_I2C0_RX = 9, | |
73 | ||
74 | #ifdef CONFIG_MACH_SPEAR1310 | |
75 | SPEAR1310_DMA_REQ_FROM_JPEG = 2, | |
76 | SPEAR1310_DMA_REQ_TO_JPEG = 3, | |
77 | SPEAR1310_DMA_REQ_I2S_TX = 10, | |
78 | SPEAR1310_DMA_REQ_I2S_RX = 11, | |
79 | ||
80 | SPEAR1310_DMA_REQ_I2C1_RX = 0, | |
81 | SPEAR1310_DMA_REQ_I2C1_TX = 1, | |
82 | SPEAR1310_DMA_REQ_I2C2_RX = 2, | |
83 | SPEAR1310_DMA_REQ_I2C2_TX = 3, | |
84 | SPEAR1310_DMA_REQ_I2C3_RX = 4, | |
85 | SPEAR1310_DMA_REQ_I2C3_TX = 5, | |
86 | SPEAR1310_DMA_REQ_I2C4_RX = 6, | |
87 | SPEAR1310_DMA_REQ_I2C4_TX = 7, | |
88 | SPEAR1310_DMA_REQ_I2C5_RX = 8, | |
89 | SPEAR1310_DMA_REQ_I2C5_TX = 9, | |
90 | SPEAR1310_DMA_REQ_I2C6_RX = 10, | |
91 | SPEAR1310_DMA_REQ_I2C6_TX = 11, | |
92 | SPEAR1310_DMA_REQ_UART1_RX = 12, | |
93 | SPEAR1310_DMA_REQ_UART1_TX = 13, | |
94 | SPEAR1310_DMA_REQ_UART2_RX = 14, | |
95 | SPEAR1310_DMA_REQ_UART2_TX = 15, | |
96 | SPEAR1310_DMA_REQ_UART5_RX = 16, | |
97 | SPEAR1310_DMA_REQ_UART5_TX = 17, | |
98 | SPEAR1310_DMA_REQ_SSP1_RX = 18, | |
99 | SPEAR1310_DMA_REQ_SSP1_TX = 19, | |
100 | SPEAR1310_DMA_REQ_I2C7_RX = 20, | |
101 | SPEAR1310_DMA_REQ_I2C7_TX = 21, | |
102 | SPEAR1310_DMA_REQ_UART3_RX = 28, | |
103 | SPEAR1310_DMA_REQ_UART3_TX = 29, | |
104 | SPEAR1310_DMA_REQ_UART4_RX = 30, | |
105 | SPEAR1310_DMA_REQ_UART4_TX = 31, | |
106 | #endif | |
107 | ||
108 | #ifdef CONFIG_MACH_SPEAR1340 | |
109 | SPEAR1340_DMA_REQ_SPDIF_TX = 2, | |
110 | SPEAR1340_DMA_REQ_SPDIF_RX = 3, | |
111 | SPEAR1340_DMA_REQ_I2S_TX = 10, | |
112 | SPEAR1340_DMA_REQ_I2S_RX = 11, | |
113 | SPEAR1340_DMA_REQ_UART1_TX = 12, | |
114 | SPEAR1340_DMA_REQ_UART1_RX = 13, | |
115 | SPEAR1340_DMA_REQ_I2C1_TX = 14, | |
116 | SPEAR1340_DMA_REQ_I2C1_RX = 15, | |
117 | SPEAR1340_DMA_REQ_CAM0_EVEN = 0, | |
118 | SPEAR1340_DMA_REQ_CAM0_ODD = 1, | |
119 | SPEAR1340_DMA_REQ_CAM1_EVEN = 2, | |
120 | SPEAR1340_DMA_REQ_CAM1_ODD = 3, | |
121 | SPEAR1340_DMA_REQ_CAM2_EVEN = 4, | |
122 | SPEAR1340_DMA_REQ_CAM2_ODD = 5, | |
123 | SPEAR1340_DMA_REQ_CAM3_EVEN = 6, | |
124 | SPEAR1340_DMA_REQ_CAM3_ODD = 7, | |
125 | #endif | |
126 | }; | |
127 | ||
128 | #endif /* __MACH_DMA_H */ |