Commit | Line | Data |
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bc4e814e | 1 | /* |
2 | * arch/arm/mach-spear3xx/spear320.c | |
3 | * | |
4 | * SPEAr320 machine source file | |
5 | * | |
c5fa4fdc | 6 | * Copyright (C) 2009-2012 ST Microelectronics |
10d8935f | 7 | * Viresh Kumar <viresh.linux@gmail.com> |
bc4e814e | 8 | * |
9 | * This file is licensed under the terms of the GNU General Public | |
10 | * License version 2. This program is licensed "as is" without any | |
11 | * warranty of any kind, whether express or implied. | |
12 | */ | |
13 | ||
5fb00f96 VK |
14 | #define pr_fmt(fmt) "SPEAr320: " fmt |
15 | ||
c5fa4fdc VK |
16 | #include <linux/amba/pl022.h> |
17 | #include <linux/amba/pl08x.h> | |
18 | #include <linux/amba/serial.h> | |
19 | #include <linux/of_platform.h> | |
20 | #include <asm/hardware/vic.h> | |
21 | #include <asm/mach/arch.h> | |
410782be | 22 | #include <plat/shirq.h> |
bc4e814e | 23 | #include <mach/generic.h> |
5df33a62 | 24 | #include <mach/spear.h> |
bc4e814e | 25 | |
5019f0b1 AB |
26 | #define SPEAR320_UART1_BASE UL(0xA3000000) |
27 | #define SPEAR320_UART2_BASE UL(0xA4000000) | |
28 | #define SPEAR320_SSP0_BASE UL(0xA5000000) | |
29 | #define SPEAR320_SSP1_BASE UL(0xA6000000) | |
5019f0b1 AB |
30 | |
31 | /* Interrupt registers offsets and masks */ | |
32 | #define SPEAR320_INT_STS_MASK_REG 0x04 | |
33 | #define SPEAR320_INT_CLR_MASK_REG 0x04 | |
34 | #define SPEAR320_INT_ENB_MASK_REG 0x08 | |
35 | #define SPEAR320_GPIO_IRQ_MASK (1 << 0) | |
36 | #define SPEAR320_I2S_PLAY_IRQ_MASK (1 << 1) | |
37 | #define SPEAR320_I2S_REC_IRQ_MASK (1 << 2) | |
38 | #define SPEAR320_EMI_IRQ_MASK (1 << 7) | |
39 | #define SPEAR320_CLCD_IRQ_MASK (1 << 8) | |
40 | #define SPEAR320_SPP_IRQ_MASK (1 << 9) | |
41 | #define SPEAR320_SDHCI_IRQ_MASK (1 << 10) | |
42 | #define SPEAR320_CAN_U_IRQ_MASK (1 << 11) | |
43 | #define SPEAR320_CAN_L_IRQ_MASK (1 << 12) | |
44 | #define SPEAR320_UART1_IRQ_MASK (1 << 13) | |
45 | #define SPEAR320_UART2_IRQ_MASK (1 << 14) | |
46 | #define SPEAR320_SSP1_IRQ_MASK (1 << 15) | |
47 | #define SPEAR320_SSP2_IRQ_MASK (1 << 16) | |
48 | #define SPEAR320_SMII0_IRQ_MASK (1 << 17) | |
49 | #define SPEAR320_MII1_SMII1_IRQ_MASK (1 << 18) | |
50 | #define SPEAR320_WAKEUP_SMII0_IRQ_MASK (1 << 19) | |
51 | #define SPEAR320_WAKEUP_MII1_SMII1_IRQ_MASK (1 << 20) | |
52 | #define SPEAR320_I2C1_IRQ_MASK (1 << 21) | |
53 | ||
54 | #define SPEAR320_SHIRQ_RAS1_MASK 0x000380 | |
55 | #define SPEAR320_SHIRQ_RAS3_MASK 0x000007 | |
56 | #define SPEAR320_SHIRQ_INTRCOMM_RAS_MASK 0x3FF800 | |
57 | ||
58 | /* SPEAr320 Virtual irq definitions */ | |
59 | /* IRQs sharing IRQ_GEN_RAS_1 */ | |
60 | #define SPEAR320_VIRQ_EMI (SPEAR3XX_VIRQ_START + 0) | |
61 | #define SPEAR320_VIRQ_CLCD (SPEAR3XX_VIRQ_START + 1) | |
62 | #define SPEAR320_VIRQ_SPP (SPEAR3XX_VIRQ_START + 2) | |
63 | ||
64 | /* IRQs sharing IRQ_GEN_RAS_2 */ | |
65 | #define SPEAR320_IRQ_SDHCI SPEAR3XX_IRQ_GEN_RAS_2 | |
66 | ||
67 | /* IRQs sharing IRQ_GEN_RAS_3 */ | |
68 | #define SPEAR320_VIRQ_PLGPIO (SPEAR3XX_VIRQ_START + 3) | |
69 | #define SPEAR320_VIRQ_I2S_PLAY (SPEAR3XX_VIRQ_START + 4) | |
70 | #define SPEAR320_VIRQ_I2S_REC (SPEAR3XX_VIRQ_START + 5) | |
71 | ||
72 | /* IRQs sharing IRQ_INTRCOMM_RAS_ARM */ | |
73 | #define SPEAR320_VIRQ_CANU (SPEAR3XX_VIRQ_START + 6) | |
74 | #define SPEAR320_VIRQ_CANL (SPEAR3XX_VIRQ_START + 7) | |
75 | #define SPEAR320_VIRQ_UART1 (SPEAR3XX_VIRQ_START + 8) | |
76 | #define SPEAR320_VIRQ_UART2 (SPEAR3XX_VIRQ_START + 9) | |
77 | #define SPEAR320_VIRQ_SSP1 (SPEAR3XX_VIRQ_START + 10) | |
78 | #define SPEAR320_VIRQ_SSP2 (SPEAR3XX_VIRQ_START + 11) | |
79 | #define SPEAR320_VIRQ_SMII0 (SPEAR3XX_VIRQ_START + 12) | |
80 | #define SPEAR320_VIRQ_MII1_SMII1 (SPEAR3XX_VIRQ_START + 13) | |
81 | #define SPEAR320_VIRQ_WAKEUP_SMII0 (SPEAR3XX_VIRQ_START + 14) | |
82 | #define SPEAR320_VIRQ_WAKEUP_MII1_SMII1 (SPEAR3XX_VIRQ_START + 15) | |
83 | #define SPEAR320_VIRQ_I2C1 (SPEAR3XX_VIRQ_START + 16) | |
bc4e814e | 84 | |
4c18e77f | 85 | /* spear3xx shared irq */ |
f6558bf9 | 86 | static struct shirq_dev_config shirq_ras1_config[] = { |
4c18e77f | 87 | { |
61e72bca RM |
88 | .virq = SPEAR320_VIRQ_EMI, |
89 | .status_mask = SPEAR320_EMI_IRQ_MASK, | |
90 | .clear_mask = SPEAR320_EMI_IRQ_MASK, | |
4c18e77f | 91 | }, { |
61e72bca RM |
92 | .virq = SPEAR320_VIRQ_CLCD, |
93 | .status_mask = SPEAR320_CLCD_IRQ_MASK, | |
94 | .clear_mask = SPEAR320_CLCD_IRQ_MASK, | |
4c18e77f | 95 | }, { |
61e72bca RM |
96 | .virq = SPEAR320_VIRQ_SPP, |
97 | .status_mask = SPEAR320_SPP_IRQ_MASK, | |
98 | .clear_mask = SPEAR320_SPP_IRQ_MASK, | |
4c18e77f | 99 | }, |
100 | }; | |
101 | ||
f6558bf9 | 102 | static struct spear_shirq shirq_ras1 = { |
61e72bca | 103 | .irq = SPEAR3XX_IRQ_GEN_RAS_1, |
4c18e77f | 104 | .dev_config = shirq_ras1_config, |
105 | .dev_count = ARRAY_SIZE(shirq_ras1_config), | |
106 | .regs = { | |
107 | .enb_reg = -1, | |
61e72bca RM |
108 | .status_reg = SPEAR320_INT_STS_MASK_REG, |
109 | .status_reg_mask = SPEAR320_SHIRQ_RAS1_MASK, | |
110 | .clear_reg = SPEAR320_INT_CLR_MASK_REG, | |
4c18e77f | 111 | .reset_to_clear = 1, |
112 | }, | |
113 | }; | |
114 | ||
f6558bf9 | 115 | static struct shirq_dev_config shirq_ras3_config[] = { |
4c18e77f | 116 | { |
61e72bca RM |
117 | .virq = SPEAR320_VIRQ_PLGPIO, |
118 | .enb_mask = SPEAR320_GPIO_IRQ_MASK, | |
119 | .status_mask = SPEAR320_GPIO_IRQ_MASK, | |
120 | .clear_mask = SPEAR320_GPIO_IRQ_MASK, | |
4c18e77f | 121 | }, { |
61e72bca RM |
122 | .virq = SPEAR320_VIRQ_I2S_PLAY, |
123 | .enb_mask = SPEAR320_I2S_PLAY_IRQ_MASK, | |
124 | .status_mask = SPEAR320_I2S_PLAY_IRQ_MASK, | |
125 | .clear_mask = SPEAR320_I2S_PLAY_IRQ_MASK, | |
4c18e77f | 126 | }, { |
61e72bca RM |
127 | .virq = SPEAR320_VIRQ_I2S_REC, |
128 | .enb_mask = SPEAR320_I2S_REC_IRQ_MASK, | |
129 | .status_mask = SPEAR320_I2S_REC_IRQ_MASK, | |
130 | .clear_mask = SPEAR320_I2S_REC_IRQ_MASK, | |
4c18e77f | 131 | }, |
132 | }; | |
133 | ||
f6558bf9 | 134 | static struct spear_shirq shirq_ras3 = { |
61e72bca | 135 | .irq = SPEAR3XX_IRQ_GEN_RAS_3, |
4c18e77f | 136 | .dev_config = shirq_ras3_config, |
137 | .dev_count = ARRAY_SIZE(shirq_ras3_config), | |
138 | .regs = { | |
61e72bca | 139 | .enb_reg = SPEAR320_INT_ENB_MASK_REG, |
4c18e77f | 140 | .reset_to_enb = 1, |
61e72bca RM |
141 | .status_reg = SPEAR320_INT_STS_MASK_REG, |
142 | .status_reg_mask = SPEAR320_SHIRQ_RAS3_MASK, | |
143 | .clear_reg = SPEAR320_INT_CLR_MASK_REG, | |
4c18e77f | 144 | .reset_to_clear = 1, |
145 | }, | |
146 | }; | |
147 | ||
f6558bf9 | 148 | static struct shirq_dev_config shirq_intrcomm_ras_config[] = { |
4c18e77f | 149 | { |
61e72bca RM |
150 | .virq = SPEAR320_VIRQ_CANU, |
151 | .status_mask = SPEAR320_CAN_U_IRQ_MASK, | |
152 | .clear_mask = SPEAR320_CAN_U_IRQ_MASK, | |
4c18e77f | 153 | }, { |
61e72bca RM |
154 | .virq = SPEAR320_VIRQ_CANL, |
155 | .status_mask = SPEAR320_CAN_L_IRQ_MASK, | |
156 | .clear_mask = SPEAR320_CAN_L_IRQ_MASK, | |
4c18e77f | 157 | }, { |
61e72bca RM |
158 | .virq = SPEAR320_VIRQ_UART1, |
159 | .status_mask = SPEAR320_UART1_IRQ_MASK, | |
160 | .clear_mask = SPEAR320_UART1_IRQ_MASK, | |
4c18e77f | 161 | }, { |
61e72bca RM |
162 | .virq = SPEAR320_VIRQ_UART2, |
163 | .status_mask = SPEAR320_UART2_IRQ_MASK, | |
164 | .clear_mask = SPEAR320_UART2_IRQ_MASK, | |
4c18e77f | 165 | }, { |
61e72bca RM |
166 | .virq = SPEAR320_VIRQ_SSP1, |
167 | .status_mask = SPEAR320_SSP1_IRQ_MASK, | |
168 | .clear_mask = SPEAR320_SSP1_IRQ_MASK, | |
4c18e77f | 169 | }, { |
61e72bca RM |
170 | .virq = SPEAR320_VIRQ_SSP2, |
171 | .status_mask = SPEAR320_SSP2_IRQ_MASK, | |
172 | .clear_mask = SPEAR320_SSP2_IRQ_MASK, | |
4c18e77f | 173 | }, { |
61e72bca RM |
174 | .virq = SPEAR320_VIRQ_SMII0, |
175 | .status_mask = SPEAR320_SMII0_IRQ_MASK, | |
176 | .clear_mask = SPEAR320_SMII0_IRQ_MASK, | |
4c18e77f | 177 | }, { |
61e72bca RM |
178 | .virq = SPEAR320_VIRQ_MII1_SMII1, |
179 | .status_mask = SPEAR320_MII1_SMII1_IRQ_MASK, | |
180 | .clear_mask = SPEAR320_MII1_SMII1_IRQ_MASK, | |
4c18e77f | 181 | }, { |
61e72bca RM |
182 | .virq = SPEAR320_VIRQ_WAKEUP_SMII0, |
183 | .status_mask = SPEAR320_WAKEUP_SMII0_IRQ_MASK, | |
184 | .clear_mask = SPEAR320_WAKEUP_SMII0_IRQ_MASK, | |
4c18e77f | 185 | }, { |
61e72bca RM |
186 | .virq = SPEAR320_VIRQ_WAKEUP_MII1_SMII1, |
187 | .status_mask = SPEAR320_WAKEUP_MII1_SMII1_IRQ_MASK, | |
188 | .clear_mask = SPEAR320_WAKEUP_MII1_SMII1_IRQ_MASK, | |
4c18e77f | 189 | }, { |
61e72bca RM |
190 | .virq = SPEAR320_VIRQ_I2C1, |
191 | .status_mask = SPEAR320_I2C1_IRQ_MASK, | |
192 | .clear_mask = SPEAR320_I2C1_IRQ_MASK, | |
4c18e77f | 193 | }, |
194 | }; | |
195 | ||
f6558bf9 | 196 | static struct spear_shirq shirq_intrcomm_ras = { |
61e72bca | 197 | .irq = SPEAR3XX_IRQ_INTRCOMM_RAS_ARM, |
4c18e77f | 198 | .dev_config = shirq_intrcomm_ras_config, |
199 | .dev_count = ARRAY_SIZE(shirq_intrcomm_ras_config), | |
200 | .regs = { | |
201 | .enb_reg = -1, | |
61e72bca RM |
202 | .status_reg = SPEAR320_INT_STS_MASK_REG, |
203 | .status_reg_mask = SPEAR320_SHIRQ_INTRCOMM_RAS_MASK, | |
204 | .clear_reg = SPEAR320_INT_CLR_MASK_REG, | |
4c18e77f | 205 | .reset_to_clear = 1, |
206 | }, | |
207 | }; | |
208 | ||
0b7ee717 VK |
209 | /* DMAC platform data's slave info */ |
210 | struct pl08x_channel_data spear320_dma_info[] = { | |
211 | { | |
212 | .bus_id = "uart0_rx", | |
213 | .min_signal = 2, | |
214 | .max_signal = 2, | |
215 | .muxval = 0, | |
216 | .cctl = 0, | |
217 | .periph_buses = PL08X_AHB1, | |
218 | }, { | |
219 | .bus_id = "uart0_tx", | |
220 | .min_signal = 3, | |
221 | .max_signal = 3, | |
222 | .muxval = 0, | |
223 | .cctl = 0, | |
224 | .periph_buses = PL08X_AHB1, | |
225 | }, { | |
226 | .bus_id = "ssp0_rx", | |
227 | .min_signal = 8, | |
228 | .max_signal = 8, | |
229 | .muxval = 0, | |
230 | .cctl = 0, | |
231 | .periph_buses = PL08X_AHB1, | |
232 | }, { | |
233 | .bus_id = "ssp0_tx", | |
234 | .min_signal = 9, | |
235 | .max_signal = 9, | |
236 | .muxval = 0, | |
237 | .cctl = 0, | |
238 | .periph_buses = PL08X_AHB1, | |
239 | }, { | |
240 | .bus_id = "i2c0_rx", | |
241 | .min_signal = 10, | |
242 | .max_signal = 10, | |
243 | .muxval = 0, | |
244 | .cctl = 0, | |
245 | .periph_buses = PL08X_AHB1, | |
246 | }, { | |
247 | .bus_id = "i2c0_tx", | |
248 | .min_signal = 11, | |
249 | .max_signal = 11, | |
250 | .muxval = 0, | |
251 | .cctl = 0, | |
252 | .periph_buses = PL08X_AHB1, | |
253 | }, { | |
254 | .bus_id = "irda", | |
255 | .min_signal = 12, | |
256 | .max_signal = 12, | |
257 | .muxval = 0, | |
258 | .cctl = 0, | |
259 | .periph_buses = PL08X_AHB1, | |
260 | }, { | |
261 | .bus_id = "adc", | |
262 | .min_signal = 13, | |
263 | .max_signal = 13, | |
264 | .muxval = 0, | |
265 | .cctl = 0, | |
266 | .periph_buses = PL08X_AHB1, | |
267 | }, { | |
268 | .bus_id = "to_jpeg", | |
269 | .min_signal = 14, | |
270 | .max_signal = 14, | |
271 | .muxval = 0, | |
272 | .cctl = 0, | |
273 | .periph_buses = PL08X_AHB1, | |
274 | }, { | |
275 | .bus_id = "from_jpeg", | |
276 | .min_signal = 15, | |
277 | .max_signal = 15, | |
278 | .muxval = 0, | |
279 | .cctl = 0, | |
280 | .periph_buses = PL08X_AHB1, | |
281 | }, { | |
282 | .bus_id = "ssp1_rx", | |
283 | .min_signal = 0, | |
284 | .max_signal = 0, | |
285 | .muxval = 1, | |
286 | .cctl = 0, | |
287 | .periph_buses = PL08X_AHB2, | |
288 | }, { | |
289 | .bus_id = "ssp1_tx", | |
290 | .min_signal = 1, | |
291 | .max_signal = 1, | |
292 | .muxval = 1, | |
293 | .cctl = 0, | |
294 | .periph_buses = PL08X_AHB2, | |
295 | }, { | |
296 | .bus_id = "ssp2_rx", | |
297 | .min_signal = 2, | |
298 | .max_signal = 2, | |
299 | .muxval = 1, | |
300 | .cctl = 0, | |
301 | .periph_buses = PL08X_AHB2, | |
302 | }, { | |
303 | .bus_id = "ssp2_tx", | |
304 | .min_signal = 3, | |
305 | .max_signal = 3, | |
306 | .muxval = 1, | |
307 | .cctl = 0, | |
308 | .periph_buses = PL08X_AHB2, | |
309 | }, { | |
310 | .bus_id = "uart1_rx", | |
311 | .min_signal = 4, | |
312 | .max_signal = 4, | |
313 | .muxval = 1, | |
314 | .cctl = 0, | |
315 | .periph_buses = PL08X_AHB2, | |
316 | }, { | |
317 | .bus_id = "uart1_tx", | |
318 | .min_signal = 5, | |
319 | .max_signal = 5, | |
320 | .muxval = 1, | |
321 | .cctl = 0, | |
322 | .periph_buses = PL08X_AHB2, | |
323 | }, { | |
324 | .bus_id = "uart2_rx", | |
325 | .min_signal = 6, | |
326 | .max_signal = 6, | |
327 | .muxval = 1, | |
328 | .cctl = 0, | |
329 | .periph_buses = PL08X_AHB2, | |
330 | }, { | |
331 | .bus_id = "uart2_tx", | |
332 | .min_signal = 7, | |
333 | .max_signal = 7, | |
334 | .muxval = 1, | |
335 | .cctl = 0, | |
336 | .periph_buses = PL08X_AHB2, | |
337 | }, { | |
338 | .bus_id = "i2c1_rx", | |
339 | .min_signal = 8, | |
340 | .max_signal = 8, | |
341 | .muxval = 1, | |
342 | .cctl = 0, | |
343 | .periph_buses = PL08X_AHB2, | |
344 | }, { | |
345 | .bus_id = "i2c1_tx", | |
346 | .min_signal = 9, | |
347 | .max_signal = 9, | |
348 | .muxval = 1, | |
349 | .cctl = 0, | |
350 | .periph_buses = PL08X_AHB2, | |
351 | }, { | |
352 | .bus_id = "i2c2_rx", | |
353 | .min_signal = 10, | |
354 | .max_signal = 10, | |
355 | .muxval = 1, | |
356 | .cctl = 0, | |
357 | .periph_buses = PL08X_AHB2, | |
358 | }, { | |
359 | .bus_id = "i2c2_tx", | |
360 | .min_signal = 11, | |
361 | .max_signal = 11, | |
362 | .muxval = 1, | |
363 | .cctl = 0, | |
364 | .periph_buses = PL08X_AHB2, | |
365 | }, { | |
366 | .bus_id = "i2s_rx", | |
367 | .min_signal = 12, | |
368 | .max_signal = 12, | |
369 | .muxval = 1, | |
370 | .cctl = 0, | |
371 | .periph_buses = PL08X_AHB2, | |
372 | }, { | |
373 | .bus_id = "i2s_tx", | |
374 | .min_signal = 13, | |
375 | .max_signal = 13, | |
376 | .muxval = 1, | |
377 | .cctl = 0, | |
378 | .periph_buses = PL08X_AHB2, | |
379 | }, { | |
380 | .bus_id = "rs485_rx", | |
381 | .min_signal = 14, | |
382 | .max_signal = 14, | |
383 | .muxval = 1, | |
384 | .cctl = 0, | |
385 | .periph_buses = PL08X_AHB2, | |
386 | }, { | |
387 | .bus_id = "rs485_tx", | |
388 | .min_signal = 15, | |
389 | .max_signal = 15, | |
390 | .muxval = 1, | |
391 | .cctl = 0, | |
392 | .periph_buses = PL08X_AHB2, | |
393 | }, | |
394 | }; | |
395 | ||
c5fa4fdc VK |
396 | static struct pl022_ssp_controller spear320_ssp_data[] = { |
397 | { | |
398 | .bus_id = 1, | |
399 | .enable_dma = 1, | |
400 | .dma_filter = pl08x_filter_id, | |
401 | .dma_tx_param = "ssp1_tx", | |
402 | .dma_rx_param = "ssp1_rx", | |
403 | .num_chipselect = 2, | |
404 | }, { | |
405 | .bus_id = 2, | |
406 | .enable_dma = 1, | |
407 | .dma_filter = pl08x_filter_id, | |
408 | .dma_tx_param = "ssp2_tx", | |
409 | .dma_rx_param = "ssp2_rx", | |
410 | .num_chipselect = 2, | |
411 | } | |
412 | }; | |
413 | ||
414 | static struct amba_pl011_data spear320_uart_data[] = { | |
415 | { | |
416 | .dma_filter = pl08x_filter_id, | |
417 | .dma_tx_param = "uart1_tx", | |
418 | .dma_rx_param = "uart1_rx", | |
419 | }, { | |
420 | .dma_filter = pl08x_filter_id, | |
421 | .dma_tx_param = "uart2_tx", | |
422 | .dma_rx_param = "uart2_rx", | |
423 | }, | |
424 | }; | |
c2c07831 | 425 | |
c5fa4fdc VK |
426 | /* Add SPEAr310 auxdata to pass platform data */ |
427 | static struct of_dev_auxdata spear320_auxdata_lookup[] __initdata = { | |
428 | OF_DEV_AUXDATA("arm,pl022", SPEAR3XX_ICM1_SSP_BASE, NULL, | |
429 | &pl022_plat_data), | |
0b7ee717 VK |
430 | OF_DEV_AUXDATA("arm,pl080", SPEAR3XX_ICM3_DMA_BASE, NULL, |
431 | &pl080_plat_data), | |
c5fa4fdc VK |
432 | OF_DEV_AUXDATA("arm,pl022", SPEAR320_SSP0_BASE, NULL, |
433 | &spear320_ssp_data[0]), | |
434 | OF_DEV_AUXDATA("arm,pl022", SPEAR320_SSP1_BASE, NULL, | |
435 | &spear320_ssp_data[1]), | |
436 | OF_DEV_AUXDATA("arm,pl011", SPEAR320_UART1_BASE, NULL, | |
437 | &spear320_uart_data[0]), | |
438 | OF_DEV_AUXDATA("arm,pl011", SPEAR320_UART2_BASE, NULL, | |
439 | &spear320_uart_data[1]), | |
440 | {} | |
441 | }; | |
442 | ||
443 | static void __init spear320_dt_init(void) | |
bc4e814e | 444 | { |
4c18e77f | 445 | void __iomem *base; |
8076dd1b | 446 | int ret; |
4c18e77f | 447 | |
0b7ee717 VK |
448 | pl080_plat_data.slave_channels = spear320_dma_info; |
449 | pl080_plat_data.num_slave_channels = ARRAY_SIZE(spear320_dma_info); | |
4c18e77f | 450 | |
c5fa4fdc VK |
451 | of_platform_populate(NULL, of_default_bus_match_table, |
452 | spear320_auxdata_lookup, NULL); | |
4c18e77f | 453 | |
b595076a | 454 | /* shared irq registration */ |
53821162 | 455 | base = ioremap(SPEAR320_SOC_CONFIG_BASE, SZ_4K); |
4c18e77f | 456 | if (base) { |
457 | /* shirq 1 */ | |
458 | shirq_ras1.regs.base = base; | |
459 | ret = spear_shirq_register(&shirq_ras1); | |
460 | if (ret) | |
5fb00f96 | 461 | pr_err("Error registering Shared IRQ 1\n"); |
4c18e77f | 462 | |
463 | /* shirq 3 */ | |
464 | shirq_ras3.regs.base = base; | |
465 | ret = spear_shirq_register(&shirq_ras3); | |
466 | if (ret) | |
5fb00f96 | 467 | pr_err("Error registering Shared IRQ 3\n"); |
4c18e77f | 468 | |
469 | /* shirq 4 */ | |
470 | shirq_intrcomm_ras.regs.base = base; | |
471 | ret = spear_shirq_register(&shirq_intrcomm_ras); | |
472 | if (ret) | |
5fb00f96 | 473 | pr_err("Error registering Shared IRQ 4\n"); |
4c18e77f | 474 | } |
70f4c0bf | 475 | } |
70f4c0bf | 476 | |
c5fa4fdc VK |
477 | static const char * const spear320_dt_board_compat[] = { |
478 | "st,spear320", | |
479 | "st,spear320-evb", | |
480 | NULL, | |
481 | }; | |
6618c3ad | 482 | |
66a2886d AB |
483 | struct map_desc spear320_io_desc[] __initdata = { |
484 | { | |
485 | .virtual = VA_SPEAR320_SOC_CONFIG_BASE, | |
486 | .pfn = __phys_to_pfn(SPEAR320_SOC_CONFIG_BASE), | |
487 | .length = SZ_16M, | |
488 | .type = MT_DEVICE | |
489 | }, | |
490 | }; | |
491 | ||
c5fa4fdc VK |
492 | static void __init spear320_map_io(void) |
493 | { | |
66a2886d | 494 | iotable_init(spear320_io_desc, ARRAY_SIZE(spear320_io_desc)); |
c5fa4fdc | 495 | spear3xx_map_io(); |
70f4c0bf | 496 | } |
c5fa4fdc VK |
497 | |
498 | DT_MACHINE_START(SPEAR320_DT, "ST SPEAr320 SoC with Flattened Device Tree") | |
499 | .map_io = spear320_map_io, | |
500 | .init_irq = spear3xx_dt_init_irq, | |
501 | .handle_irq = vic_handle_irq, | |
502 | .timer = &spear3xx_timer, | |
503 | .init_machine = spear320_dt_init, | |
504 | .restart = spear_restart, | |
505 | .dt_compat = spear320_dt_board_compat, | |
506 | MACHINE_END |