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SPEAr: Update defconfigs
[deliverable/linux.git] / arch / arm / mach-spear3xx / spear320.c
CommitLineData
bc4e814e 1/*
2 * arch/arm/mach-spear3xx/spear320.c
3 *
4 * SPEAr320 machine source file
5 *
c5fa4fdc
VK		 6 * Copyright (C) 2009-2012 ST Microelectronics
7 * Viresh Kumar <viresh.kumar@st.com>
bc4e814e 8 *
9 * This file is licensed under the terms of the GNU General Public
10 * License version 2. This program is licensed "as is" without any
11 * warranty of any kind, whether express or implied.
12 */
13
5fb00f96
VK		 14#define pr_fmt(fmt) "SPEAr320: " fmt
15
c5fa4fdc
VK		 16#include <linux/amba/pl022.h>
17#include <linux/amba/pl08x.h>
18#include <linux/amba/serial.h>
19#include <linux/of_platform.h>
20#include <asm/hardware/vic.h>
21#include <asm/mach/arch.h>
410782be 22#include <plat/shirq.h>
bc4e814e 23#include <mach/generic.h>
02aa06bc 24#include <mach/hardware.h>
bc4e814e 25
70f4c0bf 26/* pad multiplexing support */
27/* muxing registers */
28#define PAD_MUX_CONFIG_REG 0x0C
29#define MODE_CONFIG_REG 0x10
30
31/* modes */
32#define AUTO_NET_SMII_MODE (1 << 0)
33#define AUTO_NET_MII_MODE (1 << 1)
34#define AUTO_EXP_MODE (1 << 2)
35#define SMALL_PRINTERS_MODE (1 << 3)
36#define ALL_MODES 0xF
37
6618c3ad 38struct pmx_mode spear320_auto_net_smii_mode = {
70f4c0bf 39 .id = AUTO_NET_SMII_MODE,
40 .name = "Automation Networking SMII Mode",
41 .mask = 0x00,
42};
43
6618c3ad 44struct pmx_mode spear320_auto_net_mii_mode = {
70f4c0bf 45 .id = AUTO_NET_MII_MODE,
46 .name = "Automation Networking MII Mode",
47 .mask = 0x01,
48};
49
6618c3ad 50struct pmx_mode spear320_auto_exp_mode = {
70f4c0bf 51 .id = AUTO_EXP_MODE,
52 .name = "Automation Expanded Mode",
53 .mask = 0x02,
54};
55
6618c3ad 56struct pmx_mode spear320_small_printers_mode = {
70f4c0bf 57 .id = SMALL_PRINTERS_MODE,
58 .name = "Small Printers Mode",
59 .mask = 0x03,
60};
61
62/* devices */
6618c3ad 63static struct pmx_dev_mode pmx_clcd_modes[] = {
70f4c0bf 64 {
65 .ids = AUTO_NET_SMII_MODE,
66 .mask = 0x0,
67 },
68};
69
6618c3ad 70struct pmx_dev spear320_pmx_clcd = {
70f4c0bf 71 .name = "clcd",
72 .modes = pmx_clcd_modes,
73 .mode_count = ARRAY_SIZE(pmx_clcd_modes),
74 .enb_on_reset = 1,
75};
76
6618c3ad 77static struct pmx_dev_mode pmx_emi_modes[] = {
70f4c0bf 78 {
79 .ids = AUTO_EXP_MODE,
80 .mask = PMX_TIMER_1_2_MASK | PMX_TIMER_3_4_MASK,
81 },
82};
83
6618c3ad 84struct pmx_dev spear320_pmx_emi = {
70f4c0bf 85 .name = "emi",
86 .modes = pmx_emi_modes,
87 .mode_count = ARRAY_SIZE(pmx_emi_modes),
88 .enb_on_reset = 1,
89};
90
6618c3ad 91static struct pmx_dev_mode pmx_fsmc_modes[] = {
70f4c0bf 92 {
93 .ids = ALL_MODES,
94 .mask = 0x0,
95 },
96};
97
6618c3ad 98struct pmx_dev spear320_pmx_fsmc = {
70f4c0bf 99 .name = "fsmc",
100 .modes = pmx_fsmc_modes,
101 .mode_count = ARRAY_SIZE(pmx_fsmc_modes),
102 .enb_on_reset = 1,
103};
104
6618c3ad 105static struct pmx_dev_mode pmx_spp_modes[] = {
70f4c0bf 106 {
107 .ids = SMALL_PRINTERS_MODE,
108 .mask = 0x0,
109 },
110};
111
6618c3ad 112struct pmx_dev spear320_pmx_spp = {
70f4c0bf 113 .name = "spp",
114 .modes = pmx_spp_modes,
115 .mode_count = ARRAY_SIZE(pmx_spp_modes),
116 .enb_on_reset = 1,
117};
118
6618c3ad 119static struct pmx_dev_mode pmx_sdhci_modes[] = {
70f4c0bf 120 {
121 .ids = AUTO_NET_SMII_MODE | AUTO_NET_MII_MODE |
122 SMALL_PRINTERS_MODE,
123 .mask = PMX_TIMER_1_2_MASK | PMX_TIMER_3_4_MASK,
124 },
125};
126
6618c3ad 127struct pmx_dev spear320_pmx_sdhci = {
069580b8 128 .name = "sdhci",
129 .modes = pmx_sdhci_modes,
130 .mode_count = ARRAY_SIZE(pmx_sdhci_modes),
70f4c0bf 131 .enb_on_reset = 1,
132};
133
6618c3ad 134static struct pmx_dev_mode pmx_i2s_modes[] = {
70f4c0bf 135 {
136 .ids = AUTO_NET_SMII_MODE | AUTO_NET_MII_MODE,
137 .mask = PMX_UART0_MODEM_MASK,
138 },
139};
140
6618c3ad 141struct pmx_dev spear320_pmx_i2s = {
70f4c0bf 142 .name = "i2s",
143 .modes = pmx_i2s_modes,
144 .mode_count = ARRAY_SIZE(pmx_i2s_modes),
145 .enb_on_reset = 1,
146};
147
6618c3ad 148static struct pmx_dev_mode pmx_uart1_modes[] = {
70f4c0bf 149 {
150 .ids = ALL_MODES,
151 .mask = PMX_GPIO_PIN0_MASK | PMX_GPIO_PIN1_MASK,
152 },
153};
154
6618c3ad 155struct pmx_dev spear320_pmx_uart1 = {
70f4c0bf 156 .name = "uart1",
157 .modes = pmx_uart1_modes,
158 .mode_count = ARRAY_SIZE(pmx_uart1_modes),
159 .enb_on_reset = 1,
160};
161
6618c3ad 162static struct pmx_dev_mode pmx_uart1_modem_modes[] = {
70f4c0bf 163 {
164 .ids = AUTO_EXP_MODE,
165 .mask = PMX_TIMER_1_2_MASK | PMX_TIMER_3_4_MASK |
166 PMX_SSP_CS_MASK,
167 }, {
168 .ids = SMALL_PRINTERS_MODE,
169 .mask = PMX_GPIO_PIN3_MASK | PMX_GPIO_PIN4_MASK |
170 PMX_GPIO_PIN5_MASK | PMX_SSP_CS_MASK,
171 },
172};
173
6618c3ad 174struct pmx_dev spear320_pmx_uart1_modem = {
70f4c0bf 175 .name = "uart1_modem",
176 .modes = pmx_uart1_modem_modes,
177 .mode_count = ARRAY_SIZE(pmx_uart1_modem_modes),
178 .enb_on_reset = 1,
179};
180
6618c3ad 181static struct pmx_dev_mode pmx_uart2_modes[] = {
70f4c0bf 182 {
183 .ids = ALL_MODES,
184 .mask = PMX_FIRDA_MASK,
185 },
186};
187
6618c3ad 188struct pmx_dev spear320_pmx_uart2 = {
70f4c0bf 189 .name = "uart2",
190 .modes = pmx_uart2_modes,
191 .mode_count = ARRAY_SIZE(pmx_uart2_modes),
192 .enb_on_reset = 1,
193};
194
6618c3ad 195static struct pmx_dev_mode pmx_touchscreen_modes[] = {
70f4c0bf 196 {
197 .ids = AUTO_NET_SMII_MODE,
198 .mask = PMX_SSP_CS_MASK,
199 },
200};
201
6618c3ad 202struct pmx_dev spear320_pmx_touchscreen = {
70f4c0bf 203 .name = "touchscreen",
204 .modes = pmx_touchscreen_modes,
205 .mode_count = ARRAY_SIZE(pmx_touchscreen_modes),
206 .enb_on_reset = 1,
207};
208
6618c3ad 209static struct pmx_dev_mode pmx_can_modes[] = {
70f4c0bf 210 {
211 .ids = AUTO_NET_SMII_MODE | AUTO_NET_MII_MODE | AUTO_EXP_MODE,
212 .mask = PMX_GPIO_PIN2_MASK | PMX_GPIO_PIN3_MASK |
213 PMX_GPIO_PIN4_MASK | PMX_GPIO_PIN5_MASK,
214 },
215};
216
6618c3ad 217struct pmx_dev spear320_pmx_can = {
70f4c0bf 218 .name = "can",
219 .modes = pmx_can_modes,
220 .mode_count = ARRAY_SIZE(pmx_can_modes),
221 .enb_on_reset = 1,
222};
223
6618c3ad 224static struct pmx_dev_mode pmx_sdhci_led_modes[] = {
70f4c0bf 225 {
226 .ids = AUTO_NET_SMII_MODE | AUTO_NET_MII_MODE,
227 .mask = PMX_SSP_CS_MASK,
228 },
229};
230
6618c3ad 231struct pmx_dev spear320_pmx_sdhci_led = {
069580b8 232 .name = "sdhci_led",
233 .modes = pmx_sdhci_led_modes,
234 .mode_count = ARRAY_SIZE(pmx_sdhci_led_modes),
70f4c0bf 235 .enb_on_reset = 1,
236};
237
6618c3ad 238static struct pmx_dev_mode pmx_pwm0_modes[] = {
70f4c0bf 239 {
240 .ids = AUTO_NET_SMII_MODE | AUTO_NET_MII_MODE,
241 .mask = PMX_UART0_MODEM_MASK,
242 }, {
243 .ids = AUTO_EXP_MODE | SMALL_PRINTERS_MODE,
244 .mask = PMX_MII_MASK,
245 },
246};
247
6618c3ad 248struct pmx_dev spear320_pmx_pwm0 = {
70f4c0bf 249 .name = "pwm0",
250 .modes = pmx_pwm0_modes,
251 .mode_count = ARRAY_SIZE(pmx_pwm0_modes),
252 .enb_on_reset = 1,
253};
254
6618c3ad 255static struct pmx_dev_mode pmx_pwm1_modes[] = {
70f4c0bf 256 {
257 .ids = AUTO_NET_SMII_MODE | AUTO_NET_MII_MODE,
258 .mask = PMX_UART0_MODEM_MASK,
259 }, {
260 .ids = AUTO_EXP_MODE | SMALL_PRINTERS_MODE,
261 .mask = PMX_MII_MASK,
262 },
263};
264
6618c3ad 265struct pmx_dev spear320_pmx_pwm1 = {
70f4c0bf 266 .name = "pwm1",
267 .modes = pmx_pwm1_modes,
268 .mode_count = ARRAY_SIZE(pmx_pwm1_modes),
269 .enb_on_reset = 1,
270};
271
6618c3ad 272static struct pmx_dev_mode pmx_pwm2_modes[] = {
70f4c0bf 273 {
274 .ids = AUTO_NET_SMII_MODE | AUTO_NET_MII_MODE,
275 .mask = PMX_SSP_CS_MASK,
276 }, {
277 .ids = AUTO_EXP_MODE | SMALL_PRINTERS_MODE,
278 .mask = PMX_MII_MASK,
279 },
280};
281
6618c3ad 282struct pmx_dev spear320_pmx_pwm2 = {
70f4c0bf 283 .name = "pwm2",
284 .modes = pmx_pwm2_modes,
285 .mode_count = ARRAY_SIZE(pmx_pwm2_modes),
286 .enb_on_reset = 1,
287};
288
6618c3ad 289static struct pmx_dev_mode pmx_pwm3_modes[] = {
70f4c0bf 290 {
291 .ids = AUTO_EXP_MODE | SMALL_PRINTERS_MODE | AUTO_NET_SMII_MODE,
292 .mask = PMX_MII_MASK,
293 },
294};
295
6618c3ad 296struct pmx_dev spear320_pmx_pwm3 = {
70f4c0bf 297 .name = "pwm3",
298 .modes = pmx_pwm3_modes,
299 .mode_count = ARRAY_SIZE(pmx_pwm3_modes),
300 .enb_on_reset = 1,
301};
302
6618c3ad 303static struct pmx_dev_mode pmx_ssp1_modes[] = {
70f4c0bf 304 {
305 .ids = SMALL_PRINTERS_MODE | AUTO_NET_SMII_MODE,
306 .mask = PMX_MII_MASK,
307 },
308};
309
6618c3ad 310struct pmx_dev spear320_pmx_ssp1 = {
70f4c0bf 311 .name = "ssp1",
312 .modes = pmx_ssp1_modes,
313 .mode_count = ARRAY_SIZE(pmx_ssp1_modes),
314 .enb_on_reset = 1,
315};
316
6618c3ad 317static struct pmx_dev_mode pmx_ssp2_modes[] = {
70f4c0bf 318 {
319 .ids = AUTO_NET_SMII_MODE,
320 .mask = PMX_MII_MASK,
321 },
322};
323
6618c3ad 324struct pmx_dev spear320_pmx_ssp2 = {
70f4c0bf 325 .name = "ssp2",
326 .modes = pmx_ssp2_modes,
327 .mode_count = ARRAY_SIZE(pmx_ssp2_modes),
328 .enb_on_reset = 1,
329};
330
6618c3ad 331static struct pmx_dev_mode pmx_mii1_modes[] = {
70f4c0bf 332 {
333 .ids = AUTO_NET_MII_MODE,
334 .mask = 0x0,
335 },
336};
337
6618c3ad 338struct pmx_dev spear320_pmx_mii1 = {
70f4c0bf 339 .name = "mii1",
340 .modes = pmx_mii1_modes,
341 .mode_count = ARRAY_SIZE(pmx_mii1_modes),
342 .enb_on_reset = 1,
343};
344
6618c3ad 345static struct pmx_dev_mode pmx_smii0_modes[] = {
70f4c0bf 346 {
347 .ids = AUTO_NET_SMII_MODE | AUTO_EXP_MODE | SMALL_PRINTERS_MODE,
348 .mask = PMX_MII_MASK,
349 },
350};
351
6618c3ad 352struct pmx_dev spear320_pmx_smii0 = {
70f4c0bf 353 .name = "smii0",
354 .modes = pmx_smii0_modes,
355 .mode_count = ARRAY_SIZE(pmx_smii0_modes),
356 .enb_on_reset = 1,
357};
358
6618c3ad 359static struct pmx_dev_mode pmx_smii1_modes[] = {
70f4c0bf 360 {
361 .ids = AUTO_NET_SMII_MODE | SMALL_PRINTERS_MODE,
362 .mask = PMX_MII_MASK,
363 },
364};
365
6618c3ad 366struct pmx_dev spear320_pmx_smii1 = {
70f4c0bf 367 .name = "smii1",
368 .modes = pmx_smii1_modes,
369 .mode_count = ARRAY_SIZE(pmx_smii1_modes),
370 .enb_on_reset = 1,
371};
372
6618c3ad 373static struct pmx_dev_mode pmx_i2c1_modes[] = {
70f4c0bf 374 {
375 .ids = AUTO_EXP_MODE,
376 .mask = 0x0,
377 },
378};
379
6618c3ad 380struct pmx_dev spear320_pmx_i2c1 = {
70f4c0bf 381 .name = "i2c1",
382 .modes = pmx_i2c1_modes,
383 .mode_count = ARRAY_SIZE(pmx_i2c1_modes),
384 .enb_on_reset = 1,
385};
386
387/* pmx driver structure */
6618c3ad 388static struct pmx_driver pmx_driver = {
70f4c0bf 389 .mode_reg = {.offset = MODE_CONFIG_REG, .mask = 0x00000007},
390 .mux_reg = {.offset = PAD_MUX_CONFIG_REG, .mask = 0x00007fff},
391};
392
4c18e77f 393/* spear3xx shared irq */
f6558bf9 394static struct shirq_dev_config shirq_ras1_config[] = {
4c18e77f 395 {
61e72bca
RM		 396 .virq = SPEAR320_VIRQ_EMI,
397 .status_mask = SPEAR320_EMI_IRQ_MASK,
398 .clear_mask = SPEAR320_EMI_IRQ_MASK,
4c18e77f 399 }, {
61e72bca
RM		 400 .virq = SPEAR320_VIRQ_CLCD,
401 .status_mask = SPEAR320_CLCD_IRQ_MASK,
402 .clear_mask = SPEAR320_CLCD_IRQ_MASK,
4c18e77f 403 }, {
61e72bca
RM		 404 .virq = SPEAR320_VIRQ_SPP,
405 .status_mask = SPEAR320_SPP_IRQ_MASK,
406 .clear_mask = SPEAR320_SPP_IRQ_MASK,
4c18e77f 407 },
408};
409
f6558bf9 410static struct spear_shirq shirq_ras1 = {
61e72bca 411 .irq = SPEAR3XX_IRQ_GEN_RAS_1,
4c18e77f 412 .dev_config = shirq_ras1_config,
413 .dev_count = ARRAY_SIZE(shirq_ras1_config),
414 .regs = {
415 .enb_reg = -1,
61e72bca
RM		 416 .status_reg = SPEAR320_INT_STS_MASK_REG,
417 .status_reg_mask = SPEAR320_SHIRQ_RAS1_MASK,
418 .clear_reg = SPEAR320_INT_CLR_MASK_REG,
4c18e77f 419 .reset_to_clear = 1,
420 },
421};
422
f6558bf9 423static struct shirq_dev_config shirq_ras3_config[] = {
4c18e77f 424 {
61e72bca
RM		 425 .virq = SPEAR320_VIRQ_PLGPIO,
426 .enb_mask = SPEAR320_GPIO_IRQ_MASK,
427 .status_mask = SPEAR320_GPIO_IRQ_MASK,
428 .clear_mask = SPEAR320_GPIO_IRQ_MASK,
4c18e77f 429 }, {
61e72bca
RM		 430 .virq = SPEAR320_VIRQ_I2S_PLAY,
431 .enb_mask = SPEAR320_I2S_PLAY_IRQ_MASK,
432 .status_mask = SPEAR320_I2S_PLAY_IRQ_MASK,
433 .clear_mask = SPEAR320_I2S_PLAY_IRQ_MASK,
4c18e77f 434 }, {
61e72bca
RM		 435 .virq = SPEAR320_VIRQ_I2S_REC,
436 .enb_mask = SPEAR320_I2S_REC_IRQ_MASK,
437 .status_mask = SPEAR320_I2S_REC_IRQ_MASK,
438 .clear_mask = SPEAR320_I2S_REC_IRQ_MASK,
4c18e77f 439 },
440};
441
f6558bf9 442static struct spear_shirq shirq_ras3 = {
61e72bca 443 .irq = SPEAR3XX_IRQ_GEN_RAS_3,
4c18e77f 444 .dev_config = shirq_ras3_config,
445 .dev_count = ARRAY_SIZE(shirq_ras3_config),
446 .regs = {
61e72bca 447 .enb_reg = SPEAR320_INT_ENB_MASK_REG,
4c18e77f 448 .reset_to_enb = 1,
61e72bca
RM		 449 .status_reg = SPEAR320_INT_STS_MASK_REG,
450 .status_reg_mask = SPEAR320_SHIRQ_RAS3_MASK,
451 .clear_reg = SPEAR320_INT_CLR_MASK_REG,
4c18e77f 452 .reset_to_clear = 1,
453 },
454};
455
f6558bf9 456static struct shirq_dev_config shirq_intrcomm_ras_config[] = {
4c18e77f 457 {
61e72bca
RM		 458 .virq = SPEAR320_VIRQ_CANU,
459 .status_mask = SPEAR320_CAN_U_IRQ_MASK,
460 .clear_mask = SPEAR320_CAN_U_IRQ_MASK,
4c18e77f 461 }, {
61e72bca
RM		 462 .virq = SPEAR320_VIRQ_CANL,
463 .status_mask = SPEAR320_CAN_L_IRQ_MASK,
464 .clear_mask = SPEAR320_CAN_L_IRQ_MASK,
4c18e77f 465 }, {
61e72bca
RM		 466 .virq = SPEAR320_VIRQ_UART1,
467 .status_mask = SPEAR320_UART1_IRQ_MASK,
468 .clear_mask = SPEAR320_UART1_IRQ_MASK,
4c18e77f 469 }, {
61e72bca
RM		 470 .virq = SPEAR320_VIRQ_UART2,
471 .status_mask = SPEAR320_UART2_IRQ_MASK,
472 .clear_mask = SPEAR320_UART2_IRQ_MASK,
4c18e77f 473 }, {
61e72bca
RM		 474 .virq = SPEAR320_VIRQ_SSP1,
475 .status_mask = SPEAR320_SSP1_IRQ_MASK,
476 .clear_mask = SPEAR320_SSP1_IRQ_MASK,
4c18e77f 477 }, {
61e72bca
RM		 478 .virq = SPEAR320_VIRQ_SSP2,
479 .status_mask = SPEAR320_SSP2_IRQ_MASK,
480 .clear_mask = SPEAR320_SSP2_IRQ_MASK,
4c18e77f 481 }, {
61e72bca
RM		 482 .virq = SPEAR320_VIRQ_SMII0,
483 .status_mask = SPEAR320_SMII0_IRQ_MASK,
484 .clear_mask = SPEAR320_SMII0_IRQ_MASK,
4c18e77f 485 }, {
61e72bca
RM		 486 .virq = SPEAR320_VIRQ_MII1_SMII1,
487 .status_mask = SPEAR320_MII1_SMII1_IRQ_MASK,
488 .clear_mask = SPEAR320_MII1_SMII1_IRQ_MASK,
4c18e77f 489 }, {
61e72bca
RM		 490 .virq = SPEAR320_VIRQ_WAKEUP_SMII0,
491 .status_mask = SPEAR320_WAKEUP_SMII0_IRQ_MASK,
492 .clear_mask = SPEAR320_WAKEUP_SMII0_IRQ_MASK,
4c18e77f 493 }, {
61e72bca
RM		 494 .virq = SPEAR320_VIRQ_WAKEUP_MII1_SMII1,
495 .status_mask = SPEAR320_WAKEUP_MII1_SMII1_IRQ_MASK,
496 .clear_mask = SPEAR320_WAKEUP_MII1_SMII1_IRQ_MASK,
4c18e77f 497 }, {
61e72bca
RM		 498 .virq = SPEAR320_VIRQ_I2C1,
499 .status_mask = SPEAR320_I2C1_IRQ_MASK,
500 .clear_mask = SPEAR320_I2C1_IRQ_MASK,
4c18e77f 501 },
502};
503
f6558bf9 504static struct spear_shirq shirq_intrcomm_ras = {
61e72bca 505 .irq = SPEAR3XX_IRQ_INTRCOMM_RAS_ARM,
4c18e77f 506 .dev_config = shirq_intrcomm_ras_config,
507 .dev_count = ARRAY_SIZE(shirq_intrcomm_ras_config),
508 .regs = {
509 .enb_reg = -1,
61e72bca
RM		 510 .status_reg = SPEAR320_INT_STS_MASK_REG,
511 .status_reg_mask = SPEAR320_SHIRQ_INTRCOMM_RAS_MASK,
512 .clear_reg = SPEAR320_INT_CLR_MASK_REG,
4c18e77f 513 .reset_to_clear = 1,
514 },
515};
516
c5fa4fdc
VK		 517/* padmux devices to enable */
518static struct pmx_dev *spear320_evb_pmx_devs[] = {
519 /* spear3xx specific devices */
520 &spear3xx_pmx_i2c,
521 &spear3xx_pmx_ssp,
522 &spear3xx_pmx_mii,
523 &spear3xx_pmx_uart0,
524
525 /* spear320 specific devices */
526 &spear320_pmx_fsmc,
527 &spear320_pmx_sdhci,
528 &spear320_pmx_i2s,
529 &spear320_pmx_uart1,
530 &spear320_pmx_uart2,
531 &spear320_pmx_can,
532 &spear320_pmx_pwm0,
533 &spear320_pmx_pwm1,
534 &spear320_pmx_pwm2,
535 &spear320_pmx_mii1,
536};
537
0b7ee717
VK		 538/* DMAC platform data's slave info */
539struct pl08x_channel_data spear320_dma_info[] = {
540 {
541 .bus_id = "uart0_rx",
542 .min_signal = 2,
543 .max_signal = 2,
544 .muxval = 0,
545 .cctl = 0,
546 .periph_buses = PL08X_AHB1,
547 }, {
548 .bus_id = "uart0_tx",
549 .min_signal = 3,
550 .max_signal = 3,
551 .muxval = 0,
552 .cctl = 0,
553 .periph_buses = PL08X_AHB1,
554 }, {
555 .bus_id = "ssp0_rx",
556 .min_signal = 8,
557 .max_signal = 8,
558 .muxval = 0,
559 .cctl = 0,
560 .periph_buses = PL08X_AHB1,
561 }, {
562 .bus_id = "ssp0_tx",
563 .min_signal = 9,
564 .max_signal = 9,
565 .muxval = 0,
566 .cctl = 0,
567 .periph_buses = PL08X_AHB1,
568 }, {
569 .bus_id = "i2c0_rx",
570 .min_signal = 10,
571 .max_signal = 10,
572 .muxval = 0,
573 .cctl = 0,
574 .periph_buses = PL08X_AHB1,
575 }, {
576 .bus_id = "i2c0_tx",
577 .min_signal = 11,
578 .max_signal = 11,
579 .muxval = 0,
580 .cctl = 0,
581 .periph_buses = PL08X_AHB1,
582 }, {
583 .bus_id = "irda",
584 .min_signal = 12,
585 .max_signal = 12,
586 .muxval = 0,
587 .cctl = 0,
588 .periph_buses = PL08X_AHB1,
589 }, {
590 .bus_id = "adc",
591 .min_signal = 13,
592 .max_signal = 13,
593 .muxval = 0,
594 .cctl = 0,
595 .periph_buses = PL08X_AHB1,
596 }, {
597 .bus_id = "to_jpeg",
598 .min_signal = 14,
599 .max_signal = 14,
600 .muxval = 0,
601 .cctl = 0,
602 .periph_buses = PL08X_AHB1,
603 }, {
604 .bus_id = "from_jpeg",
605 .min_signal = 15,
606 .max_signal = 15,
607 .muxval = 0,
608 .cctl = 0,
609 .periph_buses = PL08X_AHB1,
610 }, {
611 .bus_id = "ssp1_rx",
612 .min_signal = 0,
613 .max_signal = 0,
614 .muxval = 1,
615 .cctl = 0,
616 .periph_buses = PL08X_AHB2,
617 }, {
618 .bus_id = "ssp1_tx",
619 .min_signal = 1,
620 .max_signal = 1,
621 .muxval = 1,
622 .cctl = 0,
623 .periph_buses = PL08X_AHB2,
624 }, {
625 .bus_id = "ssp2_rx",
626 .min_signal = 2,
627 .max_signal = 2,
628 .muxval = 1,
629 .cctl = 0,
630 .periph_buses = PL08X_AHB2,
631 }, {
632 .bus_id = "ssp2_tx",
633 .min_signal = 3,
634 .max_signal = 3,
635 .muxval = 1,
636 .cctl = 0,
637 .periph_buses = PL08X_AHB2,
638 }, {
639 .bus_id = "uart1_rx",
640 .min_signal = 4,
641 .max_signal = 4,
642 .muxval = 1,
643 .cctl = 0,
644 .periph_buses = PL08X_AHB2,
645 }, {
646 .bus_id = "uart1_tx",
647 .min_signal = 5,
648 .max_signal = 5,
649 .muxval = 1,
650 .cctl = 0,
651 .periph_buses = PL08X_AHB2,
652 }, {
653 .bus_id = "uart2_rx",
654 .min_signal = 6,
655 .max_signal = 6,
656 .muxval = 1,
657 .cctl = 0,
658 .periph_buses = PL08X_AHB2,
659 }, {
660 .bus_id = "uart2_tx",
661 .min_signal = 7,
662 .max_signal = 7,
663 .muxval = 1,
664 .cctl = 0,
665 .periph_buses = PL08X_AHB2,
666 }, {
667 .bus_id = "i2c1_rx",
668 .min_signal = 8,
669 .max_signal = 8,
670 .muxval = 1,
671 .cctl = 0,
672 .periph_buses = PL08X_AHB2,
673 }, {
674 .bus_id = "i2c1_tx",
675 .min_signal = 9,
676 .max_signal = 9,
677 .muxval = 1,
678 .cctl = 0,
679 .periph_buses = PL08X_AHB2,
680 }, {
681 .bus_id = "i2c2_rx",
682 .min_signal = 10,
683 .max_signal = 10,
684 .muxval = 1,
685 .cctl = 0,
686 .periph_buses = PL08X_AHB2,
687 }, {
688 .bus_id = "i2c2_tx",
689 .min_signal = 11,
690 .max_signal = 11,
691 .muxval = 1,
692 .cctl = 0,
693 .periph_buses = PL08X_AHB2,
694 }, {
695 .bus_id = "i2s_rx",
696 .min_signal = 12,
697 .max_signal = 12,
698 .muxval = 1,
699 .cctl = 0,
700 .periph_buses = PL08X_AHB2,
701 }, {
702 .bus_id = "i2s_tx",
703 .min_signal = 13,
704 .max_signal = 13,
705 .muxval = 1,
706 .cctl = 0,
707 .periph_buses = PL08X_AHB2,
708 }, {
709 .bus_id = "rs485_rx",
710 .min_signal = 14,
711 .max_signal = 14,
712 .muxval = 1,
713 .cctl = 0,
714 .periph_buses = PL08X_AHB2,
715 }, {
716 .bus_id = "rs485_tx",
717 .min_signal = 15,
718 .max_signal = 15,
719 .muxval = 1,
720 .cctl = 0,
721 .periph_buses = PL08X_AHB2,
722 },
723};
724
c5fa4fdc
VK		 725static struct pl022_ssp_controller spear320_ssp_data[] = {
726 {
727 .bus_id = 1,
728 .enable_dma = 1,
729 .dma_filter = pl08x_filter_id,
730 .dma_tx_param = "ssp1_tx",
731 .dma_rx_param = "ssp1_rx",
732 .num_chipselect = 2,
733 }, {
734 .bus_id = 2,
735 .enable_dma = 1,
736 .dma_filter = pl08x_filter_id,
737 .dma_tx_param = "ssp2_tx",
738 .dma_rx_param = "ssp2_rx",
739 .num_chipselect = 2,
740 }
741};
742
743static struct amba_pl011_data spear320_uart_data[] = {
744 {
745 .dma_filter = pl08x_filter_id,
746 .dma_tx_param = "uart1_tx",
747 .dma_rx_param = "uart1_rx",
748 }, {
749 .dma_filter = pl08x_filter_id,
750 .dma_tx_param = "uart2_tx",
751 .dma_rx_param = "uart2_rx",
752 },
753};
c2c07831 754
c5fa4fdc
VK		 755/* Add SPEAr310 auxdata to pass platform data */
756static struct of_dev_auxdata spear320_auxdata_lookup[] __initdata = {
757 OF_DEV_AUXDATA("arm,pl022", SPEAR3XX_ICM1_SSP_BASE, NULL,
758 &pl022_plat_data),
0b7ee717
VK		 759 OF_DEV_AUXDATA("arm,pl080", SPEAR3XX_ICM3_DMA_BASE, NULL,
760 &pl080_plat_data),
c5fa4fdc
VK		 761 OF_DEV_AUXDATA("arm,pl022", SPEAR320_SSP0_BASE, NULL,
762 &spear320_ssp_data[0]),
763 OF_DEV_AUXDATA("arm,pl022", SPEAR320_SSP1_BASE, NULL,
764 &spear320_ssp_data[1]),
765 OF_DEV_AUXDATA("arm,pl011", SPEAR320_UART1_BASE, NULL,
766 &spear320_uart_data[0]),
767 OF_DEV_AUXDATA("arm,pl011", SPEAR320_UART2_BASE, NULL,
768 &spear320_uart_data[1]),
769 {}
770};
771
772static void __init spear320_dt_init(void)
bc4e814e 773{
4c18e77f 774 void __iomem *base;
775 int ret = 0;
776
0b7ee717
VK		 777 pl080_plat_data.slave_channels = spear320_dma_info;
778 pl080_plat_data.num_slave_channels = ARRAY_SIZE(spear320_dma_info);
779
c5fa4fdc
VK		 780 of_platform_populate(NULL, of_default_bus_match_table,
781 spear320_auxdata_lookup, NULL);
4c18e77f 782
b595076a 783 /* shared irq registration */
53821162 784 base = ioremap(SPEAR320_SOC_CONFIG_BASE, SZ_4K);
4c18e77f 785 if (base) {
786 /* shirq 1 */
787 shirq_ras1.regs.base = base;
788 ret = spear_shirq_register(&shirq_ras1);
789 if (ret)
5fb00f96 790 pr_err("Error registering Shared IRQ 1\n");
4c18e77f 791
792 /* shirq 3 */
793 shirq_ras3.regs.base = base;
794 ret = spear_shirq_register(&shirq_ras3);
795 if (ret)
5fb00f96 796 pr_err("Error registering Shared IRQ 3\n");
4c18e77f 797
798 /* shirq 4 */
799 shirq_intrcomm_ras.regs.base = base;
800 ret = spear_shirq_register(&shirq_intrcomm_ras);
801 if (ret)
5fb00f96 802 pr_err("Error registering Shared IRQ 4\n");
4c18e77f 803 }
70f4c0bf 804
c5fa4fdc
VK		 805 if (of_machine_is_compatible("st,spear320-evb")) {
806 /* pmx initialization */
807 pmx_driver.base = base;
808 pmx_driver.mode = &spear320_auto_net_mii_mode;
809 pmx_driver.devs = spear320_evb_pmx_devs;
810 pmx_driver.devs_count = ARRAY_SIZE(spear320_evb_pmx_devs);
6618c3ad 811
c5fa4fdc
VK		 812 ret = pmx_register(&pmx_driver);
813 if (ret)
814 pr_err("padmux: registration failed. err no: %d\n",
815 ret);
816 }
70f4c0bf 817}
c5fa4fdc
VK		 818
819static const char * const spear320_dt_board_compat[] = {
820 "st,spear320",
821 "st,spear320-evb",
822 NULL,
823};
824
825static void __init spear320_map_io(void)
826{
827 spear3xx_map_io();
828 spear320_clk_init();
829}
830
831DT_MACHINE_START(SPEAR320_DT, "ST SPEAr320 SoC with Flattened Device Tree")
832 .map_io = spear320_map_io,
833 .init_irq = spear3xx_dt_init_irq,
834 .handle_irq = vic_handle_irq,
835 .timer = &spear3xx_timer,
836 .init_machine = spear320_dt_init,
837 .restart = spear_restart,
838 .dt_compat = spear320_dt_board_compat,
839MACHINE_END
Linux kernel - Deliverables
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