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bc4e814e | 1 | /* |
2 | * arch/arm/mach-spear3xx/spear3xx.c | |
3 | * | |
4 | * SPEAr3XX machines common source file | |
5 | * | |
6 | * Copyright (C) 2009 ST Microelectronics | |
7 | * Viresh Kumar<viresh.kumar@st.com> | |
8 | * | |
9 | * This file is licensed under the terms of the GNU General Public | |
10 | * License version 2. This program is licensed "as is" without any | |
11 | * warranty of any kind, whether express or implied. | |
12 | */ | |
13 | ||
14 | #include <linux/types.h> | |
15 | #include <linux/amba/pl061.h> | |
16 | #include <linux/ptrace.h> | |
17 | #include <linux/io.h> | |
18 | #include <asm/hardware/vic.h> | |
19 | #include <asm/irq.h> | |
20 | #include <asm/mach/arch.h> | |
21 | #include <mach/generic.h> | |
02aa06bc | 22 | #include <mach/hardware.h> |
bc4e814e | 23 | |
24 | /* Add spear3xx machines common devices here */ | |
b595076a | 25 | /* gpio device registration */ |
bc4e814e | 26 | static struct pl061_platform_data gpio_plat_data = { |
27 | .gpio_base = 0, | |
61e72bca | 28 | .irq_base = SPEAR3XX_GPIO_INT_BASE, |
bc4e814e | 29 | }; |
30 | ||
b5b654f2 RK |
31 | AMBA_APB_DEVICE(spear3xx_gpio, "gpio", 0, SPEAR3XX_ICM3_GPIO_BASE, |
32 | {SPEAR3XX_IRQ_BASIC_GPIO}, &gpio_plat_data); | |
bc4e814e | 33 | |
b595076a | 34 | /* uart device registration */ |
b5b654f2 RK |
35 | AMBA_APB_DEVICE(spear3xx_uart, "uart", 0, SPEAR3XX_ICM1_UART_BASE, |
36 | {SPEAR3XX_IRQ_UART}, NULL); | |
bc4e814e | 37 | |
38 | /* Do spear3xx familiy common initialization part here */ | |
39 | void __init spear3xx_init(void) | |
40 | { | |
41 | /* nothing to do for now */ | |
42 | } | |
43 | ||
44 | /* This will initialize vic */ | |
45 | void __init spear3xx_init_irq(void) | |
46 | { | |
47 | vic_init((void __iomem *)VA_SPEAR3XX_ML1_VIC_BASE, 0, ~0, 0); | |
48 | } | |
49 | ||
50 | /* Following will create static virtual/physical mappings */ | |
51 | struct map_desc spear3xx_io_desc[] __initdata = { | |
52 | { | |
53 | .virtual = VA_SPEAR3XX_ICM1_UART_BASE, | |
54 | .pfn = __phys_to_pfn(SPEAR3XX_ICM1_UART_BASE), | |
53821162 | 55 | .length = SZ_4K, |
bc4e814e | 56 | .type = MT_DEVICE |
57 | }, { | |
58 | .virtual = VA_SPEAR3XX_ML1_VIC_BASE, | |
59 | .pfn = __phys_to_pfn(SPEAR3XX_ML1_VIC_BASE), | |
53821162 | 60 | .length = SZ_4K, |
bc4e814e | 61 | .type = MT_DEVICE |
62 | }, { | |
63 | .virtual = VA_SPEAR3XX_ICM3_SYS_CTRL_BASE, | |
64 | .pfn = __phys_to_pfn(SPEAR3XX_ICM3_SYS_CTRL_BASE), | |
53821162 | 65 | .length = SZ_4K, |
bc4e814e | 66 | .type = MT_DEVICE |
67 | }, { | |
68 | .virtual = VA_SPEAR3XX_ICM3_MISC_REG_BASE, | |
69 | .pfn = __phys_to_pfn(SPEAR3XX_ICM3_MISC_REG_BASE), | |
53821162 | 70 | .length = SZ_4K, |
bc4e814e | 71 | .type = MT_DEVICE |
72 | }, | |
73 | }; | |
74 | ||
75 | /* This will create static memory mapping for selected devices */ | |
76 | void __init spear3xx_map_io(void) | |
77 | { | |
78 | iotable_init(spear3xx_io_desc, ARRAY_SIZE(spear3xx_io_desc)); | |
79 | ||
80 | /* This will initialize clock framework */ | |
b997f6e2 | 81 | spear3xx_clk_init(); |
bc4e814e | 82 | } |
70f4c0bf | 83 | |
84 | /* pad multiplexing support */ | |
85 | /* devices */ | |
6618c3ad | 86 | static struct pmx_dev_mode pmx_firda_modes[] = { |
70f4c0bf | 87 | { |
88 | .ids = 0xffffffff, | |
89 | .mask = PMX_FIRDA_MASK, | |
90 | }, | |
91 | }; | |
92 | ||
6618c3ad | 93 | struct pmx_dev spear3xx_pmx_firda = { |
70f4c0bf | 94 | .name = "firda", |
95 | .modes = pmx_firda_modes, | |
96 | .mode_count = ARRAY_SIZE(pmx_firda_modes), | |
97 | .enb_on_reset = 0, | |
98 | }; | |
99 | ||
6618c3ad | 100 | static struct pmx_dev_mode pmx_i2c_modes[] = { |
70f4c0bf | 101 | { |
102 | .ids = 0xffffffff, | |
103 | .mask = PMX_I2C_MASK, | |
104 | }, | |
105 | }; | |
106 | ||
6618c3ad | 107 | struct pmx_dev spear3xx_pmx_i2c = { |
70f4c0bf | 108 | .name = "i2c", |
109 | .modes = pmx_i2c_modes, | |
110 | .mode_count = ARRAY_SIZE(pmx_i2c_modes), | |
111 | .enb_on_reset = 0, | |
112 | }; | |
113 | ||
6618c3ad | 114 | static struct pmx_dev_mode pmx_ssp_cs_modes[] = { |
70f4c0bf | 115 | { |
116 | .ids = 0xffffffff, | |
117 | .mask = PMX_SSP_CS_MASK, | |
118 | }, | |
119 | }; | |
120 | ||
6618c3ad | 121 | struct pmx_dev spear3xx_pmx_ssp_cs = { |
70f4c0bf | 122 | .name = "ssp_chip_selects", |
123 | .modes = pmx_ssp_cs_modes, | |
124 | .mode_count = ARRAY_SIZE(pmx_ssp_cs_modes), | |
125 | .enb_on_reset = 0, | |
126 | }; | |
127 | ||
6618c3ad | 128 | static struct pmx_dev_mode pmx_ssp_modes[] = { |
70f4c0bf | 129 | { |
130 | .ids = 0xffffffff, | |
131 | .mask = PMX_SSP_MASK, | |
132 | }, | |
133 | }; | |
134 | ||
6618c3ad | 135 | struct pmx_dev spear3xx_pmx_ssp = { |
70f4c0bf | 136 | .name = "ssp", |
137 | .modes = pmx_ssp_modes, | |
138 | .mode_count = ARRAY_SIZE(pmx_ssp_modes), | |
139 | .enb_on_reset = 0, | |
140 | }; | |
141 | ||
6618c3ad | 142 | static struct pmx_dev_mode pmx_mii_modes[] = { |
70f4c0bf | 143 | { |
144 | .ids = 0xffffffff, | |
145 | .mask = PMX_MII_MASK, | |
146 | }, | |
147 | }; | |
148 | ||
6618c3ad | 149 | struct pmx_dev spear3xx_pmx_mii = { |
70f4c0bf | 150 | .name = "mii", |
151 | .modes = pmx_mii_modes, | |
152 | .mode_count = ARRAY_SIZE(pmx_mii_modes), | |
153 | .enb_on_reset = 0, | |
154 | }; | |
155 | ||
6618c3ad | 156 | static struct pmx_dev_mode pmx_gpio_pin0_modes[] = { |
70f4c0bf | 157 | { |
158 | .ids = 0xffffffff, | |
159 | .mask = PMX_GPIO_PIN0_MASK, | |
160 | }, | |
161 | }; | |
162 | ||
6618c3ad | 163 | struct pmx_dev spear3xx_pmx_gpio_pin0 = { |
70f4c0bf | 164 | .name = "gpio_pin0", |
165 | .modes = pmx_gpio_pin0_modes, | |
166 | .mode_count = ARRAY_SIZE(pmx_gpio_pin0_modes), | |
167 | .enb_on_reset = 0, | |
168 | }; | |
169 | ||
6618c3ad | 170 | static struct pmx_dev_mode pmx_gpio_pin1_modes[] = { |
70f4c0bf | 171 | { |
172 | .ids = 0xffffffff, | |
173 | .mask = PMX_GPIO_PIN1_MASK, | |
174 | }, | |
175 | }; | |
176 | ||
6618c3ad | 177 | struct pmx_dev spear3xx_pmx_gpio_pin1 = { |
70f4c0bf | 178 | .name = "gpio_pin1", |
179 | .modes = pmx_gpio_pin1_modes, | |
180 | .mode_count = ARRAY_SIZE(pmx_gpio_pin1_modes), | |
181 | .enb_on_reset = 0, | |
182 | }; | |
183 | ||
6618c3ad | 184 | static struct pmx_dev_mode pmx_gpio_pin2_modes[] = { |
70f4c0bf | 185 | { |
186 | .ids = 0xffffffff, | |
187 | .mask = PMX_GPIO_PIN2_MASK, | |
188 | }, | |
189 | }; | |
190 | ||
6618c3ad | 191 | struct pmx_dev spear3xx_pmx_gpio_pin2 = { |
70f4c0bf | 192 | .name = "gpio_pin2", |
193 | .modes = pmx_gpio_pin2_modes, | |
194 | .mode_count = ARRAY_SIZE(pmx_gpio_pin2_modes), | |
195 | .enb_on_reset = 0, | |
196 | }; | |
197 | ||
6618c3ad | 198 | static struct pmx_dev_mode pmx_gpio_pin3_modes[] = { |
70f4c0bf | 199 | { |
200 | .ids = 0xffffffff, | |
201 | .mask = PMX_GPIO_PIN3_MASK, | |
202 | }, | |
203 | }; | |
204 | ||
6618c3ad | 205 | struct pmx_dev spear3xx_pmx_gpio_pin3 = { |
70f4c0bf | 206 | .name = "gpio_pin3", |
207 | .modes = pmx_gpio_pin3_modes, | |
208 | .mode_count = ARRAY_SIZE(pmx_gpio_pin3_modes), | |
209 | .enb_on_reset = 0, | |
210 | }; | |
211 | ||
6618c3ad | 212 | static struct pmx_dev_mode pmx_gpio_pin4_modes[] = { |
70f4c0bf | 213 | { |
214 | .ids = 0xffffffff, | |
215 | .mask = PMX_GPIO_PIN4_MASK, | |
216 | }, | |
217 | }; | |
218 | ||
6618c3ad | 219 | struct pmx_dev spear3xx_pmx_gpio_pin4 = { |
70f4c0bf | 220 | .name = "gpio_pin4", |
221 | .modes = pmx_gpio_pin4_modes, | |
222 | .mode_count = ARRAY_SIZE(pmx_gpio_pin4_modes), | |
223 | .enb_on_reset = 0, | |
224 | }; | |
225 | ||
6618c3ad | 226 | static struct pmx_dev_mode pmx_gpio_pin5_modes[] = { |
70f4c0bf | 227 | { |
228 | .ids = 0xffffffff, | |
229 | .mask = PMX_GPIO_PIN5_MASK, | |
230 | }, | |
231 | }; | |
232 | ||
6618c3ad | 233 | struct pmx_dev spear3xx_pmx_gpio_pin5 = { |
70f4c0bf | 234 | .name = "gpio_pin5", |
235 | .modes = pmx_gpio_pin5_modes, | |
236 | .mode_count = ARRAY_SIZE(pmx_gpio_pin5_modes), | |
237 | .enb_on_reset = 0, | |
238 | }; | |
239 | ||
6618c3ad | 240 | static struct pmx_dev_mode pmx_uart0_modem_modes[] = { |
70f4c0bf | 241 | { |
242 | .ids = 0xffffffff, | |
243 | .mask = PMX_UART0_MODEM_MASK, | |
244 | }, | |
245 | }; | |
246 | ||
6618c3ad | 247 | struct pmx_dev spear3xx_pmx_uart0_modem = { |
70f4c0bf | 248 | .name = "uart0_modem", |
249 | .modes = pmx_uart0_modem_modes, | |
250 | .mode_count = ARRAY_SIZE(pmx_uart0_modem_modes), | |
251 | .enb_on_reset = 0, | |
252 | }; | |
253 | ||
6618c3ad | 254 | static struct pmx_dev_mode pmx_uart0_modes[] = { |
70f4c0bf | 255 | { |
256 | .ids = 0xffffffff, | |
257 | .mask = PMX_UART0_MASK, | |
258 | }, | |
259 | }; | |
260 | ||
6618c3ad | 261 | struct pmx_dev spear3xx_pmx_uart0 = { |
70f4c0bf | 262 | .name = "uart0", |
263 | .modes = pmx_uart0_modes, | |
264 | .mode_count = ARRAY_SIZE(pmx_uart0_modes), | |
265 | .enb_on_reset = 0, | |
266 | }; | |
267 | ||
6618c3ad | 268 | static struct pmx_dev_mode pmx_timer_3_4_modes[] = { |
70f4c0bf | 269 | { |
270 | .ids = 0xffffffff, | |
271 | .mask = PMX_TIMER_3_4_MASK, | |
272 | }, | |
273 | }; | |
274 | ||
6618c3ad | 275 | struct pmx_dev spear3xx_pmx_timer_3_4 = { |
70f4c0bf | 276 | .name = "timer_3_4", |
277 | .modes = pmx_timer_3_4_modes, | |
278 | .mode_count = ARRAY_SIZE(pmx_timer_3_4_modes), | |
279 | .enb_on_reset = 0, | |
280 | }; | |
281 | ||
6618c3ad | 282 | static struct pmx_dev_mode pmx_timer_1_2_modes[] = { |
70f4c0bf | 283 | { |
284 | .ids = 0xffffffff, | |
285 | .mask = PMX_TIMER_1_2_MASK, | |
286 | }, | |
287 | }; | |
288 | ||
6618c3ad | 289 | struct pmx_dev spear3xx_pmx_timer_1_2 = { |
70f4c0bf | 290 | .name = "timer_1_2", |
291 | .modes = pmx_timer_1_2_modes, | |
292 | .mode_count = ARRAY_SIZE(pmx_timer_1_2_modes), | |
293 | .enb_on_reset = 0, | |
294 | }; | |
295 | ||
296 | #if defined(CONFIG_MACH_SPEAR310) || defined(CONFIG_MACH_SPEAR320) | |
297 | /* plgpios devices */ | |
6618c3ad | 298 | static struct pmx_dev_mode pmx_plgpio_0_1_modes[] = { |
70f4c0bf | 299 | { |
300 | .ids = 0x00, | |
301 | .mask = PMX_FIRDA_MASK, | |
302 | }, | |
303 | }; | |
304 | ||
6618c3ad | 305 | struct pmx_dev spear3xx_pmx_plgpio_0_1 = { |
70f4c0bf | 306 | .name = "plgpio 0 and 1", |
307 | .modes = pmx_plgpio_0_1_modes, | |
308 | .mode_count = ARRAY_SIZE(pmx_plgpio_0_1_modes), | |
309 | .enb_on_reset = 1, | |
310 | }; | |
311 | ||
6618c3ad | 312 | static struct pmx_dev_mode pmx_plgpio_2_3_modes[] = { |
70f4c0bf | 313 | { |
314 | .ids = 0x00, | |
315 | .mask = PMX_UART0_MASK, | |
316 | }, | |
317 | }; | |
318 | ||
6618c3ad | 319 | struct pmx_dev spear3xx_pmx_plgpio_2_3 = { |
70f4c0bf | 320 | .name = "plgpio 2 and 3", |
321 | .modes = pmx_plgpio_2_3_modes, | |
322 | .mode_count = ARRAY_SIZE(pmx_plgpio_2_3_modes), | |
323 | .enb_on_reset = 1, | |
324 | }; | |
325 | ||
6618c3ad | 326 | static struct pmx_dev_mode pmx_plgpio_4_5_modes[] = { |
70f4c0bf | 327 | { |
328 | .ids = 0x00, | |
329 | .mask = PMX_I2C_MASK, | |
330 | }, | |
331 | }; | |
332 | ||
6618c3ad | 333 | struct pmx_dev spear3xx_pmx_plgpio_4_5 = { |
70f4c0bf | 334 | .name = "plgpio 4 and 5", |
335 | .modes = pmx_plgpio_4_5_modes, | |
336 | .mode_count = ARRAY_SIZE(pmx_plgpio_4_5_modes), | |
337 | .enb_on_reset = 1, | |
338 | }; | |
339 | ||
6618c3ad | 340 | static struct pmx_dev_mode pmx_plgpio_6_9_modes[] = { |
70f4c0bf | 341 | { |
342 | .ids = 0x00, | |
343 | .mask = PMX_SSP_MASK, | |
344 | }, | |
345 | }; | |
346 | ||
6618c3ad | 347 | struct pmx_dev spear3xx_pmx_plgpio_6_9 = { |
70f4c0bf | 348 | .name = "plgpio 6 to 9", |
349 | .modes = pmx_plgpio_6_9_modes, | |
350 | .mode_count = ARRAY_SIZE(pmx_plgpio_6_9_modes), | |
351 | .enb_on_reset = 1, | |
352 | }; | |
353 | ||
6618c3ad | 354 | static struct pmx_dev_mode pmx_plgpio_10_27_modes[] = { |
70f4c0bf | 355 | { |
356 | .ids = 0x00, | |
357 | .mask = PMX_MII_MASK, | |
358 | }, | |
359 | }; | |
360 | ||
6618c3ad | 361 | struct pmx_dev spear3xx_pmx_plgpio_10_27 = { |
70f4c0bf | 362 | .name = "plgpio 10 to 27", |
363 | .modes = pmx_plgpio_10_27_modes, | |
364 | .mode_count = ARRAY_SIZE(pmx_plgpio_10_27_modes), | |
365 | .enb_on_reset = 1, | |
366 | }; | |
367 | ||
6618c3ad | 368 | static struct pmx_dev_mode pmx_plgpio_28_modes[] = { |
70f4c0bf | 369 | { |
370 | .ids = 0x00, | |
371 | .mask = PMX_GPIO_PIN0_MASK, | |
372 | }, | |
373 | }; | |
374 | ||
6618c3ad | 375 | struct pmx_dev spear3xx_pmx_plgpio_28 = { |
70f4c0bf | 376 | .name = "plgpio 28", |
377 | .modes = pmx_plgpio_28_modes, | |
378 | .mode_count = ARRAY_SIZE(pmx_plgpio_28_modes), | |
379 | .enb_on_reset = 1, | |
380 | }; | |
381 | ||
6618c3ad | 382 | static struct pmx_dev_mode pmx_plgpio_29_modes[] = { |
70f4c0bf | 383 | { |
384 | .ids = 0x00, | |
385 | .mask = PMX_GPIO_PIN1_MASK, | |
386 | }, | |
387 | }; | |
388 | ||
6618c3ad | 389 | struct pmx_dev spear3xx_pmx_plgpio_29 = { |
70f4c0bf | 390 | .name = "plgpio 29", |
391 | .modes = pmx_plgpio_29_modes, | |
392 | .mode_count = ARRAY_SIZE(pmx_plgpio_29_modes), | |
393 | .enb_on_reset = 1, | |
394 | }; | |
395 | ||
6618c3ad | 396 | static struct pmx_dev_mode pmx_plgpio_30_modes[] = { |
70f4c0bf | 397 | { |
398 | .ids = 0x00, | |
399 | .mask = PMX_GPIO_PIN2_MASK, | |
400 | }, | |
401 | }; | |
402 | ||
6618c3ad | 403 | struct pmx_dev spear3xx_pmx_plgpio_30 = { |
70f4c0bf | 404 | .name = "plgpio 30", |
405 | .modes = pmx_plgpio_30_modes, | |
406 | .mode_count = ARRAY_SIZE(pmx_plgpio_30_modes), | |
407 | .enb_on_reset = 1, | |
408 | }; | |
409 | ||
6618c3ad | 410 | static struct pmx_dev_mode pmx_plgpio_31_modes[] = { |
70f4c0bf | 411 | { |
412 | .ids = 0x00, | |
413 | .mask = PMX_GPIO_PIN3_MASK, | |
414 | }, | |
415 | }; | |
416 | ||
6618c3ad | 417 | struct pmx_dev spear3xx_pmx_plgpio_31 = { |
70f4c0bf | 418 | .name = "plgpio 31", |
419 | .modes = pmx_plgpio_31_modes, | |
420 | .mode_count = ARRAY_SIZE(pmx_plgpio_31_modes), | |
421 | .enb_on_reset = 1, | |
422 | }; | |
423 | ||
6618c3ad | 424 | static struct pmx_dev_mode pmx_plgpio_32_modes[] = { |
70f4c0bf | 425 | { |
426 | .ids = 0x00, | |
427 | .mask = PMX_GPIO_PIN4_MASK, | |
428 | }, | |
429 | }; | |
430 | ||
6618c3ad | 431 | struct pmx_dev spear3xx_pmx_plgpio_32 = { |
70f4c0bf | 432 | .name = "plgpio 32", |
433 | .modes = pmx_plgpio_32_modes, | |
434 | .mode_count = ARRAY_SIZE(pmx_plgpio_32_modes), | |
435 | .enb_on_reset = 1, | |
436 | }; | |
437 | ||
6618c3ad | 438 | static struct pmx_dev_mode pmx_plgpio_33_modes[] = { |
70f4c0bf | 439 | { |
440 | .ids = 0x00, | |
441 | .mask = PMX_GPIO_PIN5_MASK, | |
442 | }, | |
443 | }; | |
444 | ||
6618c3ad | 445 | struct pmx_dev spear3xx_pmx_plgpio_33 = { |
70f4c0bf | 446 | .name = "plgpio 33", |
447 | .modes = pmx_plgpio_33_modes, | |
448 | .mode_count = ARRAY_SIZE(pmx_plgpio_33_modes), | |
449 | .enb_on_reset = 1, | |
450 | }; | |
451 | ||
6618c3ad | 452 | static struct pmx_dev_mode pmx_plgpio_34_36_modes[] = { |
70f4c0bf | 453 | { |
454 | .ids = 0x00, | |
455 | .mask = PMX_SSP_CS_MASK, | |
456 | }, | |
457 | }; | |
458 | ||
6618c3ad | 459 | struct pmx_dev spear3xx_pmx_plgpio_34_36 = { |
70f4c0bf | 460 | .name = "plgpio 34 to 36", |
461 | .modes = pmx_plgpio_34_36_modes, | |
462 | .mode_count = ARRAY_SIZE(pmx_plgpio_34_36_modes), | |
463 | .enb_on_reset = 1, | |
464 | }; | |
465 | ||
6618c3ad | 466 | static struct pmx_dev_mode pmx_plgpio_37_42_modes[] = { |
70f4c0bf | 467 | { |
468 | .ids = 0x00, | |
469 | .mask = PMX_UART0_MODEM_MASK, | |
470 | }, | |
471 | }; | |
472 | ||
6618c3ad | 473 | struct pmx_dev spear3xx_pmx_plgpio_37_42 = { |
70f4c0bf | 474 | .name = "plgpio 37 to 42", |
475 | .modes = pmx_plgpio_37_42_modes, | |
476 | .mode_count = ARRAY_SIZE(pmx_plgpio_37_42_modes), | |
477 | .enb_on_reset = 1, | |
478 | }; | |
479 | ||
6618c3ad | 480 | static struct pmx_dev_mode pmx_plgpio_43_44_47_48_modes[] = { |
70f4c0bf | 481 | { |
482 | .ids = 0x00, | |
483 | .mask = PMX_TIMER_1_2_MASK, | |
484 | }, | |
485 | }; | |
486 | ||
6618c3ad | 487 | struct pmx_dev spear3xx_pmx_plgpio_43_44_47_48 = { |
70f4c0bf | 488 | .name = "plgpio 43, 44, 47 and 48", |
489 | .modes = pmx_plgpio_43_44_47_48_modes, | |
490 | .mode_count = ARRAY_SIZE(pmx_plgpio_43_44_47_48_modes), | |
491 | .enb_on_reset = 1, | |
492 | }; | |
493 | ||
6618c3ad | 494 | static struct pmx_dev_mode pmx_plgpio_45_46_49_50_modes[] = { |
70f4c0bf | 495 | { |
496 | .ids = 0x00, | |
497 | .mask = PMX_TIMER_3_4_MASK, | |
498 | }, | |
499 | }; | |
500 | ||
6618c3ad | 501 | struct pmx_dev spear3xx_pmx_plgpio_45_46_49_50 = { |
70f4c0bf | 502 | .name = "plgpio 45, 46, 49 and 50", |
503 | .modes = pmx_plgpio_45_46_49_50_modes, | |
504 | .mode_count = ARRAY_SIZE(pmx_plgpio_45_46_49_50_modes), | |
505 | .enb_on_reset = 1, | |
506 | }; | |
5c881d9a | 507 | #endif /* CONFIG_MACH_SPEAR310 || CONFIG_MACH_SPEAR320 */ |
70f4c0bf | 508 | |
5c881d9a SH |
509 | static void __init spear3xx_timer_init(void) |
510 | { | |
511 | char pclk_name[] = "pll3_48m_clk"; | |
512 | struct clk *gpt_clk, *pclk; | |
513 | ||
514 | /* get the system timer clock */ | |
515 | gpt_clk = clk_get_sys("gpt0", NULL); | |
516 | if (IS_ERR(gpt_clk)) { | |
517 | pr_err("%s:couldn't get clk for gpt\n", __func__); | |
518 | BUG(); | |
519 | } | |
520 | ||
521 | /* get the suitable parent clock for timer*/ | |
522 | pclk = clk_get(NULL, pclk_name); | |
523 | if (IS_ERR(pclk)) { | |
524 | pr_err("%s:couldn't get %s as parent for gpt\n", | |
525 | __func__, pclk_name); | |
526 | BUG(); | |
527 | } | |
528 | ||
529 | clk_set_parent(gpt_clk, pclk); | |
530 | clk_put(gpt_clk); | |
531 | clk_put(pclk); | |
532 | ||
533 | spear_setup_timer(); | |
534 | } | |
535 | ||
536 | struct sys_timer spear3xx_timer = { | |
537 | .init = spear3xx_timer_init, | |
538 | }; |