Commit | Line | Data |
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bc4e814e | 1 | /* |
2 | * arch/arm/mach-spear3xx/spear3xx.c | |
3 | * | |
4 | * SPEAr3XX machines common source file | |
5 | * | |
c5fa4fdc VK |
6 | * Copyright (C) 2009-2012 ST Microelectronics |
7 | * Viresh Kumar <viresh.kumar@st.com> | |
bc4e814e | 8 | * |
9 | * This file is licensed under the terms of the GNU General Public | |
10 | * License version 2. This program is licensed "as is" without any | |
11 | * warranty of any kind, whether express or implied. | |
12 | */ | |
13 | ||
5fb00f96 VK |
14 | #define pr_fmt(fmt) "SPEAr3xx: " fmt |
15 | ||
c5fa4fdc VK |
16 | #include <linux/amba/pl022.h> |
17 | #include <linux/amba/pl08x.h> | |
18 | #include <linux/of_irq.h> | |
bc4e814e | 19 | #include <linux/io.h> |
0b7ee717 | 20 | #include <asm/hardware/pl080.h> |
bc4e814e | 21 | #include <asm/hardware/vic.h> |
0b7ee717 | 22 | #include <plat/pl080.h> |
bc4e814e | 23 | #include <mach/generic.h> |
02aa06bc | 24 | #include <mach/hardware.h> |
bc4e814e | 25 | |
70f4c0bf | 26 | /* pad multiplexing support */ |
27 | /* devices */ | |
6618c3ad | 28 | static struct pmx_dev_mode pmx_firda_modes[] = { |
70f4c0bf | 29 | { |
30 | .ids = 0xffffffff, | |
31 | .mask = PMX_FIRDA_MASK, | |
32 | }, | |
33 | }; | |
34 | ||
6618c3ad | 35 | struct pmx_dev spear3xx_pmx_firda = { |
70f4c0bf | 36 | .name = "firda", |
37 | .modes = pmx_firda_modes, | |
38 | .mode_count = ARRAY_SIZE(pmx_firda_modes), | |
39 | .enb_on_reset = 0, | |
40 | }; | |
41 | ||
6618c3ad | 42 | static struct pmx_dev_mode pmx_i2c_modes[] = { |
70f4c0bf | 43 | { |
44 | .ids = 0xffffffff, | |
45 | .mask = PMX_I2C_MASK, | |
46 | }, | |
47 | }; | |
48 | ||
6618c3ad | 49 | struct pmx_dev spear3xx_pmx_i2c = { |
70f4c0bf | 50 | .name = "i2c", |
51 | .modes = pmx_i2c_modes, | |
52 | .mode_count = ARRAY_SIZE(pmx_i2c_modes), | |
53 | .enb_on_reset = 0, | |
54 | }; | |
55 | ||
6618c3ad | 56 | static struct pmx_dev_mode pmx_ssp_cs_modes[] = { |
70f4c0bf | 57 | { |
58 | .ids = 0xffffffff, | |
59 | .mask = PMX_SSP_CS_MASK, | |
60 | }, | |
61 | }; | |
62 | ||
6618c3ad | 63 | struct pmx_dev spear3xx_pmx_ssp_cs = { |
70f4c0bf | 64 | .name = "ssp_chip_selects", |
65 | .modes = pmx_ssp_cs_modes, | |
66 | .mode_count = ARRAY_SIZE(pmx_ssp_cs_modes), | |
67 | .enb_on_reset = 0, | |
68 | }; | |
69 | ||
6618c3ad | 70 | static struct pmx_dev_mode pmx_ssp_modes[] = { |
70f4c0bf | 71 | { |
72 | .ids = 0xffffffff, | |
73 | .mask = PMX_SSP_MASK, | |
74 | }, | |
75 | }; | |
76 | ||
6618c3ad | 77 | struct pmx_dev spear3xx_pmx_ssp = { |
70f4c0bf | 78 | .name = "ssp", |
79 | .modes = pmx_ssp_modes, | |
80 | .mode_count = ARRAY_SIZE(pmx_ssp_modes), | |
81 | .enb_on_reset = 0, | |
82 | }; | |
83 | ||
6618c3ad | 84 | static struct pmx_dev_mode pmx_mii_modes[] = { |
70f4c0bf | 85 | { |
86 | .ids = 0xffffffff, | |
87 | .mask = PMX_MII_MASK, | |
88 | }, | |
89 | }; | |
90 | ||
6618c3ad | 91 | struct pmx_dev spear3xx_pmx_mii = { |
70f4c0bf | 92 | .name = "mii", |
93 | .modes = pmx_mii_modes, | |
94 | .mode_count = ARRAY_SIZE(pmx_mii_modes), | |
95 | .enb_on_reset = 0, | |
96 | }; | |
97 | ||
6618c3ad | 98 | static struct pmx_dev_mode pmx_gpio_pin0_modes[] = { |
70f4c0bf | 99 | { |
100 | .ids = 0xffffffff, | |
101 | .mask = PMX_GPIO_PIN0_MASK, | |
102 | }, | |
103 | }; | |
104 | ||
6618c3ad | 105 | struct pmx_dev spear3xx_pmx_gpio_pin0 = { |
70f4c0bf | 106 | .name = "gpio_pin0", |
107 | .modes = pmx_gpio_pin0_modes, | |
108 | .mode_count = ARRAY_SIZE(pmx_gpio_pin0_modes), | |
109 | .enb_on_reset = 0, | |
110 | }; | |
111 | ||
6618c3ad | 112 | static struct pmx_dev_mode pmx_gpio_pin1_modes[] = { |
70f4c0bf | 113 | { |
114 | .ids = 0xffffffff, | |
115 | .mask = PMX_GPIO_PIN1_MASK, | |
116 | }, | |
117 | }; | |
118 | ||
6618c3ad | 119 | struct pmx_dev spear3xx_pmx_gpio_pin1 = { |
70f4c0bf | 120 | .name = "gpio_pin1", |
121 | .modes = pmx_gpio_pin1_modes, | |
122 | .mode_count = ARRAY_SIZE(pmx_gpio_pin1_modes), | |
123 | .enb_on_reset = 0, | |
124 | }; | |
125 | ||
6618c3ad | 126 | static struct pmx_dev_mode pmx_gpio_pin2_modes[] = { |
70f4c0bf | 127 | { |
128 | .ids = 0xffffffff, | |
129 | .mask = PMX_GPIO_PIN2_MASK, | |
130 | }, | |
131 | }; | |
132 | ||
6618c3ad | 133 | struct pmx_dev spear3xx_pmx_gpio_pin2 = { |
70f4c0bf | 134 | .name = "gpio_pin2", |
135 | .modes = pmx_gpio_pin2_modes, | |
136 | .mode_count = ARRAY_SIZE(pmx_gpio_pin2_modes), | |
137 | .enb_on_reset = 0, | |
138 | }; | |
139 | ||
6618c3ad | 140 | static struct pmx_dev_mode pmx_gpio_pin3_modes[] = { |
70f4c0bf | 141 | { |
142 | .ids = 0xffffffff, | |
143 | .mask = PMX_GPIO_PIN3_MASK, | |
144 | }, | |
145 | }; | |
146 | ||
6618c3ad | 147 | struct pmx_dev spear3xx_pmx_gpio_pin3 = { |
70f4c0bf | 148 | .name = "gpio_pin3", |
149 | .modes = pmx_gpio_pin3_modes, | |
150 | .mode_count = ARRAY_SIZE(pmx_gpio_pin3_modes), | |
151 | .enb_on_reset = 0, | |
152 | }; | |
153 | ||
6618c3ad | 154 | static struct pmx_dev_mode pmx_gpio_pin4_modes[] = { |
70f4c0bf | 155 | { |
156 | .ids = 0xffffffff, | |
157 | .mask = PMX_GPIO_PIN4_MASK, | |
158 | }, | |
159 | }; | |
160 | ||
6618c3ad | 161 | struct pmx_dev spear3xx_pmx_gpio_pin4 = { |
70f4c0bf | 162 | .name = "gpio_pin4", |
163 | .modes = pmx_gpio_pin4_modes, | |
164 | .mode_count = ARRAY_SIZE(pmx_gpio_pin4_modes), | |
165 | .enb_on_reset = 0, | |
166 | }; | |
167 | ||
6618c3ad | 168 | static struct pmx_dev_mode pmx_gpio_pin5_modes[] = { |
70f4c0bf | 169 | { |
170 | .ids = 0xffffffff, | |
171 | .mask = PMX_GPIO_PIN5_MASK, | |
172 | }, | |
173 | }; | |
174 | ||
6618c3ad | 175 | struct pmx_dev spear3xx_pmx_gpio_pin5 = { |
70f4c0bf | 176 | .name = "gpio_pin5", |
177 | .modes = pmx_gpio_pin5_modes, | |
178 | .mode_count = ARRAY_SIZE(pmx_gpio_pin5_modes), | |
179 | .enb_on_reset = 0, | |
180 | }; | |
181 | ||
6618c3ad | 182 | static struct pmx_dev_mode pmx_uart0_modem_modes[] = { |
70f4c0bf | 183 | { |
184 | .ids = 0xffffffff, | |
185 | .mask = PMX_UART0_MODEM_MASK, | |
186 | }, | |
187 | }; | |
188 | ||
6618c3ad | 189 | struct pmx_dev spear3xx_pmx_uart0_modem = { |
70f4c0bf | 190 | .name = "uart0_modem", |
191 | .modes = pmx_uart0_modem_modes, | |
192 | .mode_count = ARRAY_SIZE(pmx_uart0_modem_modes), | |
193 | .enb_on_reset = 0, | |
194 | }; | |
195 | ||
6618c3ad | 196 | static struct pmx_dev_mode pmx_uart0_modes[] = { |
70f4c0bf | 197 | { |
198 | .ids = 0xffffffff, | |
199 | .mask = PMX_UART0_MASK, | |
200 | }, | |
201 | }; | |
202 | ||
6618c3ad | 203 | struct pmx_dev spear3xx_pmx_uart0 = { |
70f4c0bf | 204 | .name = "uart0", |
205 | .modes = pmx_uart0_modes, | |
206 | .mode_count = ARRAY_SIZE(pmx_uart0_modes), | |
207 | .enb_on_reset = 0, | |
208 | }; | |
209 | ||
6618c3ad | 210 | static struct pmx_dev_mode pmx_timer_3_4_modes[] = { |
70f4c0bf | 211 | { |
212 | .ids = 0xffffffff, | |
213 | .mask = PMX_TIMER_3_4_MASK, | |
214 | }, | |
215 | }; | |
216 | ||
6618c3ad | 217 | struct pmx_dev spear3xx_pmx_timer_3_4 = { |
70f4c0bf | 218 | .name = "timer_3_4", |
219 | .modes = pmx_timer_3_4_modes, | |
220 | .mode_count = ARRAY_SIZE(pmx_timer_3_4_modes), | |
221 | .enb_on_reset = 0, | |
222 | }; | |
223 | ||
6618c3ad | 224 | static struct pmx_dev_mode pmx_timer_1_2_modes[] = { |
70f4c0bf | 225 | { |
226 | .ids = 0xffffffff, | |
227 | .mask = PMX_TIMER_1_2_MASK, | |
228 | }, | |
229 | }; | |
230 | ||
6618c3ad | 231 | struct pmx_dev spear3xx_pmx_timer_1_2 = { |
70f4c0bf | 232 | .name = "timer_1_2", |
233 | .modes = pmx_timer_1_2_modes, | |
234 | .mode_count = ARRAY_SIZE(pmx_timer_1_2_modes), | |
235 | .enb_on_reset = 0, | |
236 | }; | |
237 | ||
238 | #if defined(CONFIG_MACH_SPEAR310) || defined(CONFIG_MACH_SPEAR320) | |
239 | /* plgpios devices */ | |
6618c3ad | 240 | static struct pmx_dev_mode pmx_plgpio_0_1_modes[] = { |
70f4c0bf | 241 | { |
242 | .ids = 0x00, | |
243 | .mask = PMX_FIRDA_MASK, | |
244 | }, | |
245 | }; | |
246 | ||
6618c3ad | 247 | struct pmx_dev spear3xx_pmx_plgpio_0_1 = { |
70f4c0bf | 248 | .name = "plgpio 0 and 1", |
249 | .modes = pmx_plgpio_0_1_modes, | |
250 | .mode_count = ARRAY_SIZE(pmx_plgpio_0_1_modes), | |
251 | .enb_on_reset = 1, | |
252 | }; | |
253 | ||
6618c3ad | 254 | static struct pmx_dev_mode pmx_plgpio_2_3_modes[] = { |
70f4c0bf | 255 | { |
256 | .ids = 0x00, | |
257 | .mask = PMX_UART0_MASK, | |
258 | }, | |
259 | }; | |
260 | ||
6618c3ad | 261 | struct pmx_dev spear3xx_pmx_plgpio_2_3 = { |
70f4c0bf | 262 | .name = "plgpio 2 and 3", |
263 | .modes = pmx_plgpio_2_3_modes, | |
264 | .mode_count = ARRAY_SIZE(pmx_plgpio_2_3_modes), | |
265 | .enb_on_reset = 1, | |
266 | }; | |
267 | ||
6618c3ad | 268 | static struct pmx_dev_mode pmx_plgpio_4_5_modes[] = { |
70f4c0bf | 269 | { |
270 | .ids = 0x00, | |
271 | .mask = PMX_I2C_MASK, | |
272 | }, | |
273 | }; | |
274 | ||
6618c3ad | 275 | struct pmx_dev spear3xx_pmx_plgpio_4_5 = { |
70f4c0bf | 276 | .name = "plgpio 4 and 5", |
277 | .modes = pmx_plgpio_4_5_modes, | |
278 | .mode_count = ARRAY_SIZE(pmx_plgpio_4_5_modes), | |
279 | .enb_on_reset = 1, | |
280 | }; | |
281 | ||
6618c3ad | 282 | static struct pmx_dev_mode pmx_plgpio_6_9_modes[] = { |
70f4c0bf | 283 | { |
284 | .ids = 0x00, | |
285 | .mask = PMX_SSP_MASK, | |
286 | }, | |
287 | }; | |
288 | ||
6618c3ad | 289 | struct pmx_dev spear3xx_pmx_plgpio_6_9 = { |
70f4c0bf | 290 | .name = "plgpio 6 to 9", |
291 | .modes = pmx_plgpio_6_9_modes, | |
292 | .mode_count = ARRAY_SIZE(pmx_plgpio_6_9_modes), | |
293 | .enb_on_reset = 1, | |
294 | }; | |
295 | ||
6618c3ad | 296 | static struct pmx_dev_mode pmx_plgpio_10_27_modes[] = { |
70f4c0bf | 297 | { |
298 | .ids = 0x00, | |
299 | .mask = PMX_MII_MASK, | |
300 | }, | |
301 | }; | |
302 | ||
6618c3ad | 303 | struct pmx_dev spear3xx_pmx_plgpio_10_27 = { |
70f4c0bf | 304 | .name = "plgpio 10 to 27", |
305 | .modes = pmx_plgpio_10_27_modes, | |
306 | .mode_count = ARRAY_SIZE(pmx_plgpio_10_27_modes), | |
307 | .enb_on_reset = 1, | |
308 | }; | |
309 | ||
6618c3ad | 310 | static struct pmx_dev_mode pmx_plgpio_28_modes[] = { |
70f4c0bf | 311 | { |
312 | .ids = 0x00, | |
313 | .mask = PMX_GPIO_PIN0_MASK, | |
314 | }, | |
315 | }; | |
316 | ||
6618c3ad | 317 | struct pmx_dev spear3xx_pmx_plgpio_28 = { |
70f4c0bf | 318 | .name = "plgpio 28", |
319 | .modes = pmx_plgpio_28_modes, | |
320 | .mode_count = ARRAY_SIZE(pmx_plgpio_28_modes), | |
321 | .enb_on_reset = 1, | |
322 | }; | |
323 | ||
6618c3ad | 324 | static struct pmx_dev_mode pmx_plgpio_29_modes[] = { |
70f4c0bf | 325 | { |
326 | .ids = 0x00, | |
327 | .mask = PMX_GPIO_PIN1_MASK, | |
328 | }, | |
329 | }; | |
330 | ||
6618c3ad | 331 | struct pmx_dev spear3xx_pmx_plgpio_29 = { |
70f4c0bf | 332 | .name = "plgpio 29", |
333 | .modes = pmx_plgpio_29_modes, | |
334 | .mode_count = ARRAY_SIZE(pmx_plgpio_29_modes), | |
335 | .enb_on_reset = 1, | |
336 | }; | |
337 | ||
6618c3ad | 338 | static struct pmx_dev_mode pmx_plgpio_30_modes[] = { |
70f4c0bf | 339 | { |
340 | .ids = 0x00, | |
341 | .mask = PMX_GPIO_PIN2_MASK, | |
342 | }, | |
343 | }; | |
344 | ||
6618c3ad | 345 | struct pmx_dev spear3xx_pmx_plgpio_30 = { |
70f4c0bf | 346 | .name = "plgpio 30", |
347 | .modes = pmx_plgpio_30_modes, | |
348 | .mode_count = ARRAY_SIZE(pmx_plgpio_30_modes), | |
349 | .enb_on_reset = 1, | |
350 | }; | |
351 | ||
6618c3ad | 352 | static struct pmx_dev_mode pmx_plgpio_31_modes[] = { |
70f4c0bf | 353 | { |
354 | .ids = 0x00, | |
355 | .mask = PMX_GPIO_PIN3_MASK, | |
356 | }, | |
357 | }; | |
358 | ||
6618c3ad | 359 | struct pmx_dev spear3xx_pmx_plgpio_31 = { |
70f4c0bf | 360 | .name = "plgpio 31", |
361 | .modes = pmx_plgpio_31_modes, | |
362 | .mode_count = ARRAY_SIZE(pmx_plgpio_31_modes), | |
363 | .enb_on_reset = 1, | |
364 | }; | |
365 | ||
6618c3ad | 366 | static struct pmx_dev_mode pmx_plgpio_32_modes[] = { |
70f4c0bf | 367 | { |
368 | .ids = 0x00, | |
369 | .mask = PMX_GPIO_PIN4_MASK, | |
370 | }, | |
371 | }; | |
372 | ||
6618c3ad | 373 | struct pmx_dev spear3xx_pmx_plgpio_32 = { |
70f4c0bf | 374 | .name = "plgpio 32", |
375 | .modes = pmx_plgpio_32_modes, | |
376 | .mode_count = ARRAY_SIZE(pmx_plgpio_32_modes), | |
377 | .enb_on_reset = 1, | |
378 | }; | |
379 | ||
6618c3ad | 380 | static struct pmx_dev_mode pmx_plgpio_33_modes[] = { |
70f4c0bf | 381 | { |
382 | .ids = 0x00, | |
383 | .mask = PMX_GPIO_PIN5_MASK, | |
384 | }, | |
385 | }; | |
386 | ||
6618c3ad | 387 | struct pmx_dev spear3xx_pmx_plgpio_33 = { |
70f4c0bf | 388 | .name = "plgpio 33", |
389 | .modes = pmx_plgpio_33_modes, | |
390 | .mode_count = ARRAY_SIZE(pmx_plgpio_33_modes), | |
391 | .enb_on_reset = 1, | |
392 | }; | |
393 | ||
6618c3ad | 394 | static struct pmx_dev_mode pmx_plgpio_34_36_modes[] = { |
70f4c0bf | 395 | { |
396 | .ids = 0x00, | |
397 | .mask = PMX_SSP_CS_MASK, | |
398 | }, | |
399 | }; | |
400 | ||
6618c3ad | 401 | struct pmx_dev spear3xx_pmx_plgpio_34_36 = { |
70f4c0bf | 402 | .name = "plgpio 34 to 36", |
403 | .modes = pmx_plgpio_34_36_modes, | |
404 | .mode_count = ARRAY_SIZE(pmx_plgpio_34_36_modes), | |
405 | .enb_on_reset = 1, | |
406 | }; | |
407 | ||
6618c3ad | 408 | static struct pmx_dev_mode pmx_plgpio_37_42_modes[] = { |
70f4c0bf | 409 | { |
410 | .ids = 0x00, | |
411 | .mask = PMX_UART0_MODEM_MASK, | |
412 | }, | |
413 | }; | |
414 | ||
6618c3ad | 415 | struct pmx_dev spear3xx_pmx_plgpio_37_42 = { |
70f4c0bf | 416 | .name = "plgpio 37 to 42", |
417 | .modes = pmx_plgpio_37_42_modes, | |
418 | .mode_count = ARRAY_SIZE(pmx_plgpio_37_42_modes), | |
419 | .enb_on_reset = 1, | |
420 | }; | |
421 | ||
6618c3ad | 422 | static struct pmx_dev_mode pmx_plgpio_43_44_47_48_modes[] = { |
70f4c0bf | 423 | { |
424 | .ids = 0x00, | |
425 | .mask = PMX_TIMER_1_2_MASK, | |
426 | }, | |
427 | }; | |
428 | ||
6618c3ad | 429 | struct pmx_dev spear3xx_pmx_plgpio_43_44_47_48 = { |
70f4c0bf | 430 | .name = "plgpio 43, 44, 47 and 48", |
431 | .modes = pmx_plgpio_43_44_47_48_modes, | |
432 | .mode_count = ARRAY_SIZE(pmx_plgpio_43_44_47_48_modes), | |
433 | .enb_on_reset = 1, | |
434 | }; | |
435 | ||
6618c3ad | 436 | static struct pmx_dev_mode pmx_plgpio_45_46_49_50_modes[] = { |
70f4c0bf | 437 | { |
438 | .ids = 0x00, | |
439 | .mask = PMX_TIMER_3_4_MASK, | |
440 | }, | |
441 | }; | |
442 | ||
6618c3ad | 443 | struct pmx_dev spear3xx_pmx_plgpio_45_46_49_50 = { |
70f4c0bf | 444 | .name = "plgpio 45, 46, 49 and 50", |
445 | .modes = pmx_plgpio_45_46_49_50_modes, | |
446 | .mode_count = ARRAY_SIZE(pmx_plgpio_45_46_49_50_modes), | |
447 | .enb_on_reset = 1, | |
448 | }; | |
5c881d9a | 449 | #endif /* CONFIG_MACH_SPEAR310 || CONFIG_MACH_SPEAR320 */ |
70f4c0bf | 450 | |
c5fa4fdc VK |
451 | /* ssp device registration */ |
452 | struct pl022_ssp_controller pl022_plat_data = { | |
453 | .bus_id = 0, | |
454 | .enable_dma = 1, | |
455 | .dma_filter = pl08x_filter_id, | |
456 | .dma_tx_param = "ssp0_tx", | |
457 | .dma_rx_param = "ssp0_rx", | |
458 | /* | |
459 | * This is number of spi devices that can be connected to spi. There are | |
460 | * two type of chipselects on which slave devices can work. One is chip | |
461 | * select provided by spi masters other is controlled through external | |
462 | * gpio's. We can't use chipselect provided from spi master (because as | |
463 | * soon as FIFO becomes empty, CS is disabled and transfer ends). So | |
464 | * this number now depends on number of gpios available for spi. each | |
465 | * slave on each master requires a separate gpio pin. | |
466 | */ | |
467 | .num_chipselect = 2, | |
468 | }; | |
469 | ||
0b7ee717 VK |
470 | /* dmac device registration */ |
471 | struct pl08x_platform_data pl080_plat_data = { | |
472 | .memcpy_channel = { | |
473 | .bus_id = "memcpy", | |
474 | .cctl = (PL080_BSIZE_16 << PL080_CONTROL_SB_SIZE_SHIFT | \ | |
475 | PL080_BSIZE_16 << PL080_CONTROL_DB_SIZE_SHIFT | \ | |
476 | PL080_WIDTH_32BIT << PL080_CONTROL_SWIDTH_SHIFT | \ | |
477 | PL080_WIDTH_32BIT << PL080_CONTROL_DWIDTH_SHIFT | \ | |
478 | PL080_CONTROL_PROT_BUFF | PL080_CONTROL_PROT_CACHE | \ | |
479 | PL080_CONTROL_PROT_SYS), | |
480 | }, | |
481 | .lli_buses = PL08X_AHB1, | |
482 | .mem_buses = PL08X_AHB1, | |
483 | .get_signal = pl080_get_signal, | |
484 | .put_signal = pl080_put_signal, | |
485 | }; | |
486 | ||
c5fa4fdc VK |
487 | /* |
488 | * Following will create 16MB static virtual/physical mappings | |
489 | * PHYSICAL VIRTUAL | |
490 | * 0xD0000000 0xFD000000 | |
491 | * 0xFC000000 0xFC000000 | |
492 | */ | |
493 | struct map_desc spear3xx_io_desc[] __initdata = { | |
494 | { | |
495 | .virtual = VA_SPEAR3XX_ICM1_2_BASE, | |
496 | .pfn = __phys_to_pfn(SPEAR3XX_ICM1_2_BASE), | |
497 | .length = SZ_16M, | |
498 | .type = MT_DEVICE | |
499 | }, { | |
500 | .virtual = VA_SPEAR3XX_ICM3_SMI_CTRL_BASE, | |
501 | .pfn = __phys_to_pfn(SPEAR3XX_ICM3_SMI_CTRL_BASE), | |
502 | .length = SZ_16M, | |
503 | .type = MT_DEVICE | |
504 | }, | |
505 | }; | |
506 | ||
507 | /* This will create static memory mapping for selected devices */ | |
508 | void __init spear3xx_map_io(void) | |
509 | { | |
510 | iotable_init(spear3xx_io_desc, ARRAY_SIZE(spear3xx_io_desc)); | |
511 | } | |
512 | ||
5c881d9a SH |
513 | static void __init spear3xx_timer_init(void) |
514 | { | |
515 | char pclk_name[] = "pll3_48m_clk"; | |
516 | struct clk *gpt_clk, *pclk; | |
517 | ||
518 | /* get the system timer clock */ | |
519 | gpt_clk = clk_get_sys("gpt0", NULL); | |
520 | if (IS_ERR(gpt_clk)) { | |
521 | pr_err("%s:couldn't get clk for gpt\n", __func__); | |
522 | BUG(); | |
523 | } | |
524 | ||
525 | /* get the suitable parent clock for timer*/ | |
526 | pclk = clk_get(NULL, pclk_name); | |
527 | if (IS_ERR(pclk)) { | |
528 | pr_err("%s:couldn't get %s as parent for gpt\n", | |
529 | __func__, pclk_name); | |
530 | BUG(); | |
531 | } | |
532 | ||
533 | clk_set_parent(gpt_clk, pclk); | |
534 | clk_put(gpt_clk); | |
535 | clk_put(pclk); | |
536 | ||
537 | spear_setup_timer(); | |
538 | } | |
539 | ||
540 | struct sys_timer spear3xx_timer = { | |
541 | .init = spear3xx_timer_init, | |
542 | }; | |
c5fa4fdc VK |
543 | |
544 | static const struct of_device_id vic_of_match[] __initconst = { | |
545 | { .compatible = "arm,pl190-vic", .data = vic_of_init, }, | |
546 | { /* Sentinel */ } | |
547 | }; | |
548 | ||
549 | void __init spear3xx_dt_init_irq(void) | |
550 | { | |
551 | of_irq_init(vic_of_match); | |
552 | } |