[deliverable/linux.git] / arch / arm / mach-sunxi / sunxi.c

/*
 * Device Tree support for Allwinner A1X SoCs
 *
 * Copyright (C) 2012 Maxime Ripard
 *
 * Maxime Ripard <maxime.ripard@free-electrons.com>
 *
 * This file is licensed under the terms of the GNU General Public
 * License version 2.  This program is licensed "as is" without any
 * warranty of any kind, whether express or implied.
 */

#include <linux/delay.h>
#include <linux/kernel.h>
#include <linux/init.h>
#include <linux/of_address.h>
#include <linux/of_irq.h>
#include <linux/of_platform.h>
#include <linux/io.h>
#include <linux/sunxi_timer.h>

#include <linux/irqchip/sunxi.h>

#include <asm/mach/arch.h>
#include <asm/mach/map.h>

#include "sunxi.h"

#define WATCHDOG_CTRL_REG	0x00
#define WATCHDOG_CTRL_RESTART		(1 << 0)
#define WATCHDOG_MODE_REG	0x04
#define WATCHDOG_MODE_ENABLE		(1 << 0)
#define WATCHDOG_MODE_RESET_ENABLE	(1 << 1)

static void __iomem *wdt_base;

static void sunxi_setup_restart(void)
{
	struct device_node *np = of_find_compatible_node(NULL, NULL,
						"allwinner,sunxi-wdt");
	if (WARN(!np, "unable to setup watchdog restart"))
		return;

	wdt_base = of_iomap(np, 0);
	WARN(!wdt_base, "failed to map watchdog base address");
}

static void sunxi_restart(char mode, const char *cmd)
{
	if (!wdt_base)
		return;

	/* Enable timer and set reset bit in the watchdog */
	writel(WATCHDOG_MODE_ENABLE | WATCHDOG_MODE_RESET_ENABLE,
		wdt_base + WATCHDOG_MODE_REG);

	/*
	 * Restart the watchdog. The default (and lowest) interval
	 * value for the watchdog is 0.5s.
	 */
	writel(WATCHDOG_CTRL_RESTART, wdt_base + WATCHDOG_CTRL_REG);

	while (1) {
		mdelay(5);
		writel(WATCHDOG_MODE_ENABLE | WATCHDOG_MODE_RESET_ENABLE,
			wdt_base + WATCHDOG_MODE_REG);
	}
}

static struct map_desc sunxi_io_desc[] __initdata = {
	{
		.virtual	= (unsigned long) SUNXI_REGS_VIRT_BASE,
		.pfn		= __phys_to_pfn(SUNXI_REGS_PHYS_BASE),
		.length		= SUNXI_REGS_SIZE,
		.type		= MT_DEVICE,
	},
};

void __init sunxi_map_io(void)
{
	iotable_init(sunxi_io_desc, ARRAY_SIZE(sunxi_io_desc));
}

static void __init sunxi_dt_init(void)
{
	sunxi_setup_restart();

	of_platform_populate(NULL, of_default_bus_match_table, NULL, NULL);
}

static const char * const sunxi_board_dt_compat[] = {
	"allwinner,sun4i-a10",
	"allwinner,sun5i-a13",
	NULL,
};

DT_MACHINE_START(SUNXI_DT, "Allwinner A1X (Device Tree)")
	.init_machine	= sunxi_dt_init,
	.map_io		= sunxi_map_io,
	.init_irq	= sunxi_init_irq,
	.handle_irq	= sunxi_handle_irq,
	.restart	= sunxi_restart,
	.init_time	= &sunxi_timer_init,
	.dt_compat	= sunxi_board_dt_compat,
MACHINE_END
Commit	Line	Data
3b52634f MR	1	/*
	2	* Device Tree support for Allwinner A1X SoCs
	3	*
	4	* Copyright (C) 2012 Maxime Ripard
	5	*
	6	* Maxime Ripard <maxime.ripard@free-electrons.com>
	7	*
	8	* This file is licensed under the terms of the GNU General Public
	9	* License version 2. This program is licensed "as is" without any
	10	* warranty of any kind, whether express or implied.
	11	*/
	12
5e51651d	13	#include <linux/delay.h>
3b52634f MR	14	#include <linux/kernel.h>
3b52634f MR	15	#include <linux/init.h>
67bea88d	16	#include <linux/of_address.h>
3b52634f MR	17	#include <linux/of_irq.h>
	18	#include <linux/of_platform.h>
	19	#include <linux/io.h>
	20	#include <linux/sunxi_timer.h>
	21
	22	#include <linux/irqchip/sunxi.h>
	23
3b52634f MR	24	#include <asm/mach/arch.h>
	25	#include <asm/mach/map.h>
	26
	27	#include "sunxi.h"
	28
67bea88d	29	#define WATCHDOG_CTRL_REG 0x00
b60decad	30	#define WATCHDOG_CTRL_RESTART (1 << 0)
67bea88d	31	#define WATCHDOG_MODE_REG 0x04
b60decad MR	32	#define WATCHDOG_MODE_ENABLE (1 << 0)
b60decad MR	33	#define WATCHDOG_MODE_RESET_ENABLE (1 << 1)
67bea88d MR	34
	35	static void __iomem *wdt_base;
	36
	37	static void sunxi_setup_restart(void)
	38	{
	39	struct device_node *np = of_find_compatible_node(NULL, NULL,
	40	"allwinner,sunxi-wdt");
	41	if (WARN(!np, "unable to setup watchdog restart"))
	42	return;
	43
	44	wdt_base = of_iomap(np, 0);
	45	WARN(!wdt_base, "failed to map watchdog base address");
	46	}
	47
	48	static void sunxi_restart(char mode, const char *cmd)
	49	{
	50	if (!wdt_base)
	51	return;
	52
	53	/* Enable timer and set reset bit in the watchdog */
b60decad MR	54	writel(WATCHDOG_MODE_ENABLE \| WATCHDOG_MODE_RESET_ENABLE,
	55	wdt_base + WATCHDOG_MODE_REG);
	56
	57	/*
	58	* Restart the watchdog. The default (and lowest) interval
	59	* value for the watchdog is 0.5s.
	60	*/
	61	writel(WATCHDOG_CTRL_RESTART, wdt_base + WATCHDOG_CTRL_REG);
	62
	63	while (1) {
67bea88d	64	mdelay(5);
b60decad MR	65	writel(WATCHDOG_MODE_ENABLE \| WATCHDOG_MODE_RESET_ENABLE,
b60decad MR	66	wdt_base + WATCHDOG_MODE_REG);
67bea88d MR	67	}
	68	}
	69
3b52634f MR	70	static struct map_desc sunxi_io_desc[] __initdata = {
	71	{
	72	.virtual = (unsigned long) SUNXI_REGS_VIRT_BASE,
	73	.pfn = __phys_to_pfn(SUNXI_REGS_PHYS_BASE),
	74	.length = SUNXI_REGS_SIZE,
	75	.type = MT_DEVICE,
	76	},
	77	};
	78
	79	void __init sunxi_map_io(void)
	80	{
	81	iotable_init(sunxi_io_desc, ARRAY_SIZE(sunxi_io_desc));
	82	}
	83
	84	static void __init sunxi_dt_init(void)
	85	{
67bea88d MR	86	sunxi_setup_restart();
67bea88d MR	87
3b52634f MR	88	of_platform_populate(NULL, of_default_bus_match_table, NULL, NULL);
	89	}
	90
	91	static const char * const sunxi_board_dt_compat[] = {
43880f70 MR	92	"allwinner,sun4i-a10",
43880f70 MR	93	"allwinner,sun5i-a13",
3b52634f MR	94	NULL,
	95	};
	96
	97	DT_MACHINE_START(SUNXI_DT, "Allwinner A1X (Device Tree)")
	98	.init_machine = sunxi_dt_init,
	99	.map_io = sunxi_map_io,
	100	.init_irq = sunxi_init_irq,
	101	.handle_irq = sunxi_handle_irq,
67bea88d	102	.restart = sunxi_restart,
1c2584c3	103	.init_time = &sunxi_timer_init,
3b52634f MR	104	.dt_compat = sunxi_board_dt_compat,
3b52634f MR	105	MACHINE_END