[deliverable/linux.git] / arch / arm / mach-sunxi / sunxi.c

/*
 * Device Tree support for Allwinner A1X SoCs
 *
 * Copyright (C) 2012 Maxime Ripard
 *
 * Maxime Ripard <maxime.ripard@free-electrons.com>
 *
 * This file is licensed under the terms of the GNU General Public
 * License version 2.  This program is licensed "as is" without any
 * warranty of any kind, whether express or implied.
 */

#include <linux/clocksource.h>
#include <linux/delay.h>
#include <linux/kernel.h>
#include <linux/init.h>
#include <linux/of_address.h>
#include <linux/of_irq.h>
#include <linux/of_platform.h>
#include <linux/io.h>
#include <linux/reboot.h>

#include <linux/clk/sunxi.h>

#include <asm/mach/arch.h>
#include <asm/mach/map.h>
#include <asm/system_misc.h>

#define SUN4I_WATCHDOG_CTRL_REG		0x00
#define SUN4I_WATCHDOG_CTRL_RESTART		BIT(0)
#define SUN4I_WATCHDOG_MODE_REG		0x04
#define SUN4I_WATCHDOG_MODE_ENABLE		BIT(0)
#define SUN4I_WATCHDOG_MODE_RESET_ENABLE	BIT(1)

#define SUN6I_WATCHDOG1_IRQ_REG		0x00
#define SUN6I_WATCHDOG1_CTRL_REG	0x10
#define SUN6I_WATCHDOG1_CTRL_RESTART		BIT(0)
#define SUN6I_WATCHDOG1_CONFIG_REG	0x14
#define SUN6I_WATCHDOG1_CONFIG_RESTART		BIT(0)
#define SUN6I_WATCHDOG1_CONFIG_IRQ		BIT(1)
#define SUN6I_WATCHDOG1_MODE_REG	0x18
#define SUN6I_WATCHDOG1_MODE_ENABLE		BIT(0)

static void __iomem *wdt_base;

static void sun4i_restart(enum reboot_mode mode, const char *cmd)
{
	if (!wdt_base)
		return;

	/* Enable timer and set reset bit in the watchdog */
	writel(SUN4I_WATCHDOG_MODE_ENABLE | SUN4I_WATCHDOG_MODE_RESET_ENABLE,
	       wdt_base + SUN4I_WATCHDOG_MODE_REG);

	/*
	 * Restart the watchdog. The default (and lowest) interval
	 * value for the watchdog is 0.5s.
	 */
	writel(SUN4I_WATCHDOG_CTRL_RESTART, wdt_base + SUN4I_WATCHDOG_CTRL_REG);

	while (1) {
		mdelay(5);
		writel(SUN4I_WATCHDOG_MODE_ENABLE | SUN4I_WATCHDOG_MODE_RESET_ENABLE,
		       wdt_base + SUN4I_WATCHDOG_MODE_REG);
	}
}

static void sun6i_restart(enum reboot_mode mode, const char *cmd)
{
	if (!wdt_base)
		return;

	/* Disable interrupts */
	writel(0, wdt_base + SUN6I_WATCHDOG1_IRQ_REG);

	/* We want to disable the IRQ and just reset the whole system */
	writel(SUN6I_WATCHDOG1_CONFIG_RESTART,
		wdt_base + SUN6I_WATCHDOG1_CONFIG_REG);

	/* Enable timer. The default and lowest interval value is 0.5s */
	writel(SUN6I_WATCHDOG1_MODE_ENABLE,
		wdt_base + SUN6I_WATCHDOG1_MODE_REG);

	/* Restart the watchdog. */
	writel(SUN6I_WATCHDOG1_CTRL_RESTART,
		wdt_base + SUN6I_WATCHDOG1_CTRL_REG);

	while (1) {
		mdelay(5);
		writel(SUN6I_WATCHDOG1_MODE_ENABLE,
			wdt_base + SUN6I_WATCHDOG1_MODE_REG);
	}
}

static struct of_device_id sunxi_restart_ids[] = {
	{ .compatible = "allwinner,sun4i-wdt", .data = sun4i_restart },
	{ .compatible = "allwinner,sun6i-wdt", .data = sun6i_restart },
	{ /*sentinel*/ }
};

static void sunxi_setup_restart(void)
{
	const struct of_device_id *of_id;
	struct device_node *np;

	np = of_find_matching_node(NULL, sunxi_restart_ids);
	if (WARN(!np, "unable to setup watchdog restart"))
		return;

	wdt_base = of_iomap(np, 0);
	WARN(!wdt_base, "failed to map watchdog base address");

	of_id = of_match_node(sunxi_restart_ids, np);
	WARN(!of_id, "restart function not available");

	arm_pm_restart = of_id->data;
}

static void __init sunxi_timer_init(void)
{
	sunxi_init_clocks();
	clocksource_of_init();
}

static void __init sunxi_dt_init(void)
{
	sunxi_setup_restart();

	of_platform_populate(NULL, of_default_bus_match_table, NULL, NULL);
}

static const char * const sunxi_board_dt_compat[] = {
	"allwinner,sun4i-a10",
	"allwinner,sun5i-a10s",
	"allwinner,sun5i-a13",
	"allwinner,sun6i-a31",
	"allwinner,sun7i-a20",
	NULL,
};

DT_MACHINE_START(SUNXI_DT, "Allwinner A1X (Device Tree)")
	.init_machine	= sunxi_dt_init,
	.init_time	= sunxi_timer_init,
	.dt_compat	= sunxi_board_dt_compat,
MACHINE_END
Commit	Line	Data
3b52634f MR	1	/*
	2	* Device Tree support for Allwinner A1X SoCs
	3	*
	4	* Copyright (C) 2012 Maxime Ripard
	5	*
	6	* Maxime Ripard <maxime.ripard@free-electrons.com>
	7	*
	8	* This file is licensed under the terms of the GNU General Public
	9	* License version 2. This program is licensed "as is" without any
	10	* warranty of any kind, whether express or implied.
	11	*/
	12
ea71d9a6	13	#include <linux/clocksource.h>
5e51651d	14	#include <linux/delay.h>
3b52634f MR	15	#include <linux/kernel.h>
3b52634f MR	16	#include <linux/init.h>
67bea88d	17	#include <linux/of_address.h>
3b52634f MR	18	#include <linux/of_irq.h>
	19	#include <linux/of_platform.h>
	20	#include <linux/io.h>
7b6d864b	21	#include <linux/reboot.h>
3b52634f	22
ea71d9a6	23	#include <linux/clk/sunxi.h>
3b52634f	24
3b52634f MR	25	#include <asm/mach/arch.h>
3b52634f MR	26	#include <asm/mach/map.h>
bc34b5f2	27	#include <asm/system_misc.h>
3b52634f	28
bc34b5f2	29	#define SUN4I_WATCHDOG_CTRL_REG 0x00
06d71bcf	30	#define SUN4I_WATCHDOG_CTRL_RESTART BIT(0)
bc34b5f2	31	#define SUN4I_WATCHDOG_MODE_REG 0x04
06d71bcf MR	32	#define SUN4I_WATCHDOG_MODE_ENABLE BIT(0)
	33	#define SUN4I_WATCHDOG_MODE_RESET_ENABLE BIT(1)
	34
	35	#define SUN6I_WATCHDOG1_IRQ_REG 0x00
	36	#define SUN6I_WATCHDOG1_CTRL_REG 0x10
	37	#define SUN6I_WATCHDOG1_CTRL_RESTART BIT(0)
	38	#define SUN6I_WATCHDOG1_CONFIG_REG 0x14
	39	#define SUN6I_WATCHDOG1_CONFIG_RESTART BIT(0)
	40	#define SUN6I_WATCHDOG1_CONFIG_IRQ BIT(1)
	41	#define SUN6I_WATCHDOG1_MODE_REG 0x18
	42	#define SUN6I_WATCHDOG1_MODE_ENABLE BIT(0)
67bea88d MR	43
	44	static void __iomem *wdt_base;
	45
7b6d864b	46	static void sun4i_restart(enum reboot_mode mode, const char *cmd)
67bea88d MR	47	{
	48	if (!wdt_base)
	49	return;
	50
	51	/* Enable timer and set reset bit in the watchdog */
bc34b5f2 MR	52	writel(SUN4I_WATCHDOG_MODE_ENABLE \| SUN4I_WATCHDOG_MODE_RESET_ENABLE,
bc34b5f2 MR	53	wdt_base + SUN4I_WATCHDOG_MODE_REG);
b60decad MR	54
	55	/*
	56	* Restart the watchdog. The default (and lowest) interval
	57	* value for the watchdog is 0.5s.
	58	*/
bc34b5f2	59	writel(SUN4I_WATCHDOG_CTRL_RESTART, wdt_base + SUN4I_WATCHDOG_CTRL_REG);
b60decad MR	60
b60decad MR	61	while (1) {
67bea88d	62	mdelay(5);
bc34b5f2 MR	63	writel(SUN4I_WATCHDOG_MODE_ENABLE \| SUN4I_WATCHDOG_MODE_RESET_ENABLE,
bc34b5f2 MR	64	wdt_base + SUN4I_WATCHDOG_MODE_REG);
67bea88d MR	65	}
	66	}
	67
06d71bcf MR	68	static void sun6i_restart(enum reboot_mode mode, const char *cmd)
	69	{
	70	if (!wdt_base)
	71	return;
	72
	73	/* Disable interrupts */
	74	writel(0, wdt_base + SUN6I_WATCHDOG1_IRQ_REG);
	75
	76	/* We want to disable the IRQ and just reset the whole system */
	77	writel(SUN6I_WATCHDOG1_CONFIG_RESTART,
	78	wdt_base + SUN6I_WATCHDOG1_CONFIG_REG);
	79
	80	/* Enable timer. The default and lowest interval value is 0.5s */
	81	writel(SUN6I_WATCHDOG1_MODE_ENABLE,
	82	wdt_base + SUN6I_WATCHDOG1_MODE_REG);
	83
	84	/* Restart the watchdog. */
	85	writel(SUN6I_WATCHDOG1_CTRL_RESTART,
	86	wdt_base + SUN6I_WATCHDOG1_CTRL_REG);
	87
	88	while (1) {
	89	mdelay(5);
	90	writel(SUN6I_WATCHDOG1_MODE_ENABLE,
	91	wdt_base + SUN6I_WATCHDOG1_MODE_REG);
	92	}
	93	}
	94
bc34b5f2 MR	95	static struct of_device_id sunxi_restart_ids[] = {
bc34b5f2 MR	96	{ .compatible = "allwinner,sun4i-wdt", .data = sun4i_restart },
06d71bcf	97	{ .compatible = "allwinner,sun6i-wdt", .data = sun6i_restart },
bc34b5f2 MR	98	{ /sentinel/ }
	99	};
	100
	101	static void sunxi_setup_restart(void)
	102	{
	103	const struct of_device_id *of_id;
	104	struct device_node *np;
	105
	106	np = of_find_matching_node(NULL, sunxi_restart_ids);
	107	if (WARN(!np, "unable to setup watchdog restart"))
	108	return;
	109
	110	wdt_base = of_iomap(np, 0);
	111	WARN(!wdt_base, "failed to map watchdog base address");
	112
	113	of_id = of_match_node(sunxi_restart_ids, np);
	114	WARN(!of_id, "restart function not available");
	115
	116	arm_pm_restart = of_id->data;
	117	}
	118
ea71d9a6 MR	119	static void __init sunxi_timer_init(void)
	120	{
	121	sunxi_init_clocks();
	122	clocksource_of_init();
	123	}
	124
3b52634f MR	125	static void __init sunxi_dt_init(void)
3b52634f MR	126	{
67bea88d MR	127	sunxi_setup_restart();
67bea88d MR	128
3b52634f MR	129	of_platform_populate(NULL, of_default_bus_match_table, NULL, NULL);
	130	}
	131
	132	static const char * const sunxi_board_dt_compat[] = {
43880f70	133	"allwinner,sun4i-a10",
81265dfb	134	"allwinner,sun5i-a10s",
43880f70	135	"allwinner,sun5i-a13",
2d794510	136	"allwinner,sun6i-a31",
d18fd944	137	"allwinner,sun7i-a20",
3b52634f MR	138	NULL,
	139	};
	140
	141	DT_MACHINE_START(SUNXI_DT, "Allwinner A1X (Device Tree)")
	142	.init_machine = sunxi_dt_init,
ea71d9a6	143	.init_time = sunxi_timer_init,
3b52634f MR	144	.dt_compat = sunxi_board_dt_compat,
3b52634f MR	145	MACHINE_END