Commit | Line | Data |
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3b52634f MR |
1 | /* |
2 | * Device Tree support for Allwinner A1X SoCs | |
3 | * | |
4 | * Copyright (C) 2012 Maxime Ripard | |
5 | * | |
6 | * Maxime Ripard <maxime.ripard@free-electrons.com> | |
7 | * | |
8 | * This file is licensed under the terms of the GNU General Public | |
9 | * License version 2. This program is licensed "as is" without any | |
10 | * warranty of any kind, whether express or implied. | |
11 | */ | |
12 | ||
ea71d9a6 | 13 | #include <linux/clocksource.h> |
5e51651d | 14 | #include <linux/delay.h> |
3b52634f MR |
15 | #include <linux/kernel.h> |
16 | #include <linux/init.h> | |
67bea88d | 17 | #include <linux/of_address.h> |
3b52634f MR |
18 | #include <linux/of_irq.h> |
19 | #include <linux/of_platform.h> | |
20 | #include <linux/io.h> | |
7b6d864b | 21 | #include <linux/reboot.h> |
3b52634f | 22 | |
ea71d9a6 | 23 | #include <linux/clk/sunxi.h> |
3b52634f | 24 | |
3b52634f MR |
25 | #include <asm/mach/arch.h> |
26 | #include <asm/mach/map.h> | |
bc34b5f2 | 27 | #include <asm/system_misc.h> |
3b52634f | 28 | |
bc34b5f2 MR |
29 | #define SUN4I_WATCHDOG_CTRL_REG 0x00 |
30 | #define SUN4I_WATCHDOG_CTRL_RESTART (1 << 0) | |
31 | #define SUN4I_WATCHDOG_MODE_REG 0x04 | |
32 | #define SUN4I_WATCHDOG_MODE_ENABLE (1 << 0) | |
33 | #define SUN4I_WATCHDOG_MODE_RESET_ENABLE (1 << 1) | |
67bea88d MR |
34 | |
35 | static void __iomem *wdt_base; | |
36 | ||
7b6d864b | 37 | static void sun4i_restart(enum reboot_mode mode, const char *cmd) |
67bea88d MR |
38 | { |
39 | if (!wdt_base) | |
40 | return; | |
41 | ||
42 | /* Enable timer and set reset bit in the watchdog */ | |
bc34b5f2 MR |
43 | writel(SUN4I_WATCHDOG_MODE_ENABLE | SUN4I_WATCHDOG_MODE_RESET_ENABLE, |
44 | wdt_base + SUN4I_WATCHDOG_MODE_REG); | |
b60decad MR |
45 | |
46 | /* | |
47 | * Restart the watchdog. The default (and lowest) interval | |
48 | * value for the watchdog is 0.5s. | |
49 | */ | |
bc34b5f2 | 50 | writel(SUN4I_WATCHDOG_CTRL_RESTART, wdt_base + SUN4I_WATCHDOG_CTRL_REG); |
b60decad MR |
51 | |
52 | while (1) { | |
67bea88d | 53 | mdelay(5); |
bc34b5f2 MR |
54 | writel(SUN4I_WATCHDOG_MODE_ENABLE | SUN4I_WATCHDOG_MODE_RESET_ENABLE, |
55 | wdt_base + SUN4I_WATCHDOG_MODE_REG); | |
67bea88d MR |
56 | } |
57 | } | |
58 | ||
bc34b5f2 MR |
59 | static struct of_device_id sunxi_restart_ids[] = { |
60 | { .compatible = "allwinner,sun4i-wdt", .data = sun4i_restart }, | |
61 | { /*sentinel*/ } | |
62 | }; | |
63 | ||
64 | static void sunxi_setup_restart(void) | |
65 | { | |
66 | const struct of_device_id *of_id; | |
67 | struct device_node *np; | |
68 | ||
69 | np = of_find_matching_node(NULL, sunxi_restart_ids); | |
70 | if (WARN(!np, "unable to setup watchdog restart")) | |
71 | return; | |
72 | ||
73 | wdt_base = of_iomap(np, 0); | |
74 | WARN(!wdt_base, "failed to map watchdog base address"); | |
75 | ||
76 | of_id = of_match_node(sunxi_restart_ids, np); | |
77 | WARN(!of_id, "restart function not available"); | |
78 | ||
79 | arm_pm_restart = of_id->data; | |
80 | } | |
81 | ||
ea71d9a6 MR |
82 | static void __init sunxi_timer_init(void) |
83 | { | |
84 | sunxi_init_clocks(); | |
85 | clocksource_of_init(); | |
86 | } | |
87 | ||
3b52634f MR |
88 | static void __init sunxi_dt_init(void) |
89 | { | |
67bea88d MR |
90 | sunxi_setup_restart(); |
91 | ||
3b52634f MR |
92 | of_platform_populate(NULL, of_default_bus_match_table, NULL, NULL); |
93 | } | |
94 | ||
95 | static const char * const sunxi_board_dt_compat[] = { | |
43880f70 | 96 | "allwinner,sun4i-a10", |
81265dfb | 97 | "allwinner,sun5i-a10s", |
43880f70 | 98 | "allwinner,sun5i-a13", |
2d794510 | 99 | "allwinner,sun6i-a31", |
3b52634f MR |
100 | NULL, |
101 | }; | |
102 | ||
103 | DT_MACHINE_START(SUNXI_DT, "Allwinner A1X (Device Tree)") | |
104 | .init_machine = sunxi_dt_init, | |
ea71d9a6 | 105 | .init_time = sunxi_timer_init, |
3b52634f MR |
106 | .dt_compat = sunxi_board_dt_compat, |
107 | MACHINE_END |