Commit | Line | Data |
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3b52634f MR |
1 | /* |
2 | * Device Tree support for Allwinner A1X SoCs | |
3 | * | |
4 | * Copyright (C) 2012 Maxime Ripard | |
5 | * | |
6 | * Maxime Ripard <maxime.ripard@free-electrons.com> | |
7 | * | |
8 | * This file is licensed under the terms of the GNU General Public | |
9 | * License version 2. This program is licensed "as is" without any | |
10 | * warranty of any kind, whether express or implied. | |
11 | */ | |
12 | ||
5e51651d | 13 | #include <linux/delay.h> |
3b52634f MR |
14 | #include <linux/kernel.h> |
15 | #include <linux/init.h> | |
67bea88d | 16 | #include <linux/of_address.h> |
3b52634f MR |
17 | #include <linux/of_irq.h> |
18 | #include <linux/of_platform.h> | |
19 | #include <linux/io.h> | |
7b6d864b | 20 | #include <linux/reboot.h> |
3b52634f | 21 | |
3b52634f MR |
22 | #include <asm/mach/arch.h> |
23 | #include <asm/mach/map.h> | |
bc34b5f2 | 24 | #include <asm/system_misc.h> |
3b52634f | 25 | |
bc34b5f2 | 26 | #define SUN4I_WATCHDOG_CTRL_REG 0x00 |
06d71bcf | 27 | #define SUN4I_WATCHDOG_CTRL_RESTART BIT(0) |
bc34b5f2 | 28 | #define SUN4I_WATCHDOG_MODE_REG 0x04 |
06d71bcf MR |
29 | #define SUN4I_WATCHDOG_MODE_ENABLE BIT(0) |
30 | #define SUN4I_WATCHDOG_MODE_RESET_ENABLE BIT(1) | |
31 | ||
32 | #define SUN6I_WATCHDOG1_IRQ_REG 0x00 | |
33 | #define SUN6I_WATCHDOG1_CTRL_REG 0x10 | |
34 | #define SUN6I_WATCHDOG1_CTRL_RESTART BIT(0) | |
35 | #define SUN6I_WATCHDOG1_CONFIG_REG 0x14 | |
36 | #define SUN6I_WATCHDOG1_CONFIG_RESTART BIT(0) | |
37 | #define SUN6I_WATCHDOG1_CONFIG_IRQ BIT(1) | |
38 | #define SUN6I_WATCHDOG1_MODE_REG 0x18 | |
39 | #define SUN6I_WATCHDOG1_MODE_ENABLE BIT(0) | |
67bea88d MR |
40 | |
41 | static void __iomem *wdt_base; | |
42 | ||
7b6d864b | 43 | static void sun4i_restart(enum reboot_mode mode, const char *cmd) |
67bea88d MR |
44 | { |
45 | if (!wdt_base) | |
46 | return; | |
47 | ||
48 | /* Enable timer and set reset bit in the watchdog */ | |
bc34b5f2 MR |
49 | writel(SUN4I_WATCHDOG_MODE_ENABLE | SUN4I_WATCHDOG_MODE_RESET_ENABLE, |
50 | wdt_base + SUN4I_WATCHDOG_MODE_REG); | |
b60decad MR |
51 | |
52 | /* | |
53 | * Restart the watchdog. The default (and lowest) interval | |
54 | * value for the watchdog is 0.5s. | |
55 | */ | |
bc34b5f2 | 56 | writel(SUN4I_WATCHDOG_CTRL_RESTART, wdt_base + SUN4I_WATCHDOG_CTRL_REG); |
b60decad MR |
57 | |
58 | while (1) { | |
67bea88d | 59 | mdelay(5); |
bc34b5f2 MR |
60 | writel(SUN4I_WATCHDOG_MODE_ENABLE | SUN4I_WATCHDOG_MODE_RESET_ENABLE, |
61 | wdt_base + SUN4I_WATCHDOG_MODE_REG); | |
67bea88d MR |
62 | } |
63 | } | |
64 | ||
06d71bcf MR |
65 | static void sun6i_restart(enum reboot_mode mode, const char *cmd) |
66 | { | |
67 | if (!wdt_base) | |
68 | return; | |
69 | ||
70 | /* Disable interrupts */ | |
71 | writel(0, wdt_base + SUN6I_WATCHDOG1_IRQ_REG); | |
72 | ||
73 | /* We want to disable the IRQ and just reset the whole system */ | |
74 | writel(SUN6I_WATCHDOG1_CONFIG_RESTART, | |
75 | wdt_base + SUN6I_WATCHDOG1_CONFIG_REG); | |
76 | ||
77 | /* Enable timer. The default and lowest interval value is 0.5s */ | |
78 | writel(SUN6I_WATCHDOG1_MODE_ENABLE, | |
79 | wdt_base + SUN6I_WATCHDOG1_MODE_REG); | |
80 | ||
81 | /* Restart the watchdog. */ | |
82 | writel(SUN6I_WATCHDOG1_CTRL_RESTART, | |
83 | wdt_base + SUN6I_WATCHDOG1_CTRL_REG); | |
84 | ||
85 | while (1) { | |
86 | mdelay(5); | |
87 | writel(SUN6I_WATCHDOG1_MODE_ENABLE, | |
88 | wdt_base + SUN6I_WATCHDOG1_MODE_REG); | |
89 | } | |
90 | } | |
91 | ||
bc34b5f2 | 92 | static struct of_device_id sunxi_restart_ids[] = { |
53ea6887 MR |
93 | { .compatible = "allwinner,sun4i-wdt" }, |
94 | { .compatible = "allwinner,sun6i-wdt" }, | |
bc34b5f2 MR |
95 | { /*sentinel*/ } |
96 | }; | |
97 | ||
98 | static void sunxi_setup_restart(void) | |
99 | { | |
bc34b5f2 MR |
100 | struct device_node *np; |
101 | ||
102 | np = of_find_matching_node(NULL, sunxi_restart_ids); | |
103 | if (WARN(!np, "unable to setup watchdog restart")) | |
104 | return; | |
105 | ||
106 | wdt_base = of_iomap(np, 0); | |
107 | WARN(!wdt_base, "failed to map watchdog base address"); | |
bc34b5f2 MR |
108 | } |
109 | ||
3b52634f MR |
110 | static void __init sunxi_dt_init(void) |
111 | { | |
67bea88d MR |
112 | sunxi_setup_restart(); |
113 | ||
3b52634f MR |
114 | of_platform_populate(NULL, of_default_bus_match_table, NULL, NULL); |
115 | } | |
116 | ||
117 | static const char * const sunxi_board_dt_compat[] = { | |
43880f70 | 118 | "allwinner,sun4i-a10", |
81265dfb | 119 | "allwinner,sun5i-a10s", |
43880f70 | 120 | "allwinner,sun5i-a13", |
3b52634f MR |
121 | NULL, |
122 | }; | |
123 | ||
124 | DT_MACHINE_START(SUNXI_DT, "Allwinner A1X (Device Tree)") | |
125 | .init_machine = sunxi_dt_init, | |
3b52634f | 126 | .dt_compat = sunxi_board_dt_compat, |
53ea6887 | 127 | .restart = sun4i_restart, |
3b52634f | 128 | MACHINE_END |
91a31977 MR |
129 | |
130 | static const char * const sun6i_board_dt_compat[] = { | |
131 | "allwinner,sun6i-a31", | |
132 | NULL, | |
133 | }; | |
134 | ||
135 | DT_MACHINE_START(SUN6I_DT, "Allwinner sun6i (A31) Family") | |
136 | .init_machine = sunxi_dt_init, | |
91a31977 | 137 | .dt_compat = sun6i_board_dt_compat, |
53ea6887 | 138 | .restart = sun6i_restart, |
91a31977 MR |
139 | MACHINE_END |
140 | ||
141 | static const char * const sun7i_board_dt_compat[] = { | |
142 | "allwinner,sun7i-a20", | |
143 | NULL, | |
144 | }; | |
145 | ||
146 | DT_MACHINE_START(SUN7I_DT, "Allwinner sun7i (A20) Family") | |
147 | .init_machine = sunxi_dt_init, | |
91a31977 | 148 | .dt_compat = sun7i_board_dt_compat, |
53ea6887 | 149 | .restart = sun4i_restart, |
3b52634f | 150 | MACHINE_END |