projects / deliverable / linux.git / blame
| Commit | Line | Data |
|---|---|---|
| 2aea73ce HK |
1 | /* |
| 2 | * Copyright (C) 2009 Hans J. Koch <hjk@linutronix.de> | |
| 3 | * | |
| 4 | * This program is free software; you can redistribute it and/or modify | |
| 5 | * it under the terms of the GNU General Public License version 2 as | |
| 6 | * published by the Free Software Foundation. | |
| 7 | */ | |
| 8 | ||
| 85922e54 | 9 | #include <linux/delay.h> |
| 2aea73ce HK |
10 | #include <linux/init.h> |
| 11 | #include <linux/kernel.h> | |
| 12 | #include <linux/platform_device.h> | |
| 13 | ||
| 14 | #include <asm/mach-types.h> | |
| 15 | ||
| 16 | #include <asm/mach/arch.h> | |
| 17 | #include <asm/mach/map.h> | |
| 18 | #include <asm/mach/time.h> | |
| 19 | ||
| 20 | #include <mach/clock.h> | |
| 30d91355 | 21 | #include <mach/tcc-nand.h> |
| 85922e54 | 22 | #include <mach/tcc8k-regs.h> |
| 2aea73ce HK |
23 | |
| 24 | #include "common.h" | |
| 25 | ||
| 26 | #define XI_FREQUENCY 12000000 | |
| 27 | #define XTI_FREQUENCY 32768 | |
| 28 | ||
| 29 | #ifdef CONFIG_MTD_NAND_TCC | |
| 30 | /* NAND */ | |
| 31 | static struct tcc_nand_platform_data tcc8k_sdk_nand_data = { | |
| 32 | .width = 1, | |
| 33 | .hw_ecc = 0, | |
| 34 | }; | |
| 35 | #endif | |
| 36 | ||
| 37 | static void __init tcc8k_init(void) | |
| 38 | { | |
| 39 | #ifdef CONFIG_MTD_NAND_TCC | |
| 40 | tcc_nand_device.dev.platform_data = &tcc8k_sdk_nand_data; | |
| 41 | platform_device_register(&tcc_nand_device); | |
| 42 | #endif | |
| 43 | } | |
| 44 | ||
| 45 | static void __init tcc8k_init_timer(void) | |
| 46 | { | |
| 47 | tcc_clocks_init(XI_FREQUENCY, XTI_FREQUENCY); | |
| 48 | } | |
| 49 | ||
| 50 | static struct sys_timer tcc8k_timer = { | |
| 51 | .init = tcc8k_init_timer, | |
| 52 | }; | |
| 53 | ||
| 54 | static void __init tcc8k_map_io(void) | |
| 55 | { | |
| 56 | tcc8k_map_common_io(); | |
| 85922e54 OS |
57 | |
| 58 | /* set PLL0 clock to 96MHz, adapt UART0 divisor */ | |
| 59 | __raw_writel(0x00026003, CKC_BASE + PLL0CFG_OFFS); | |
| 60 | __raw_writel(0x10000001, CKC_BASE + ACLKUART0_OFFS); | |
| 61 | ||
| 62 | /* set PLL1 clock to 192MHz */ | |
| 63 | __raw_writel(0x00016003, CKC_BASE + PLL1CFG_OFFS); | |
| 64 | ||
| 65 | /* set PLL2 clock to 48MHz */ | |
| 66 | __raw_writel(0x00036003, CKC_BASE + PLL2CFG_OFFS); | |
| 67 | ||
| 68 | /* with CPU freq higher than 150 MHz, need extra DTCM wait */ | |
| 69 | __raw_writel(0x00000001, SCFG_BASE + DTCMWAIT_OFFS); | |
| 70 | ||
| 71 | /* PLL locking time as specified */ | |
| 72 | udelay(300); | |
| 2aea73ce HK |
73 | } |
| 74 | ||
| 75 | MACHINE_START(TCC8000_SDK, "Telechips TCC8000-SDK Demo Board") | |
| b75c178a | 76 | .boot_params = PLAT_PHYS_OFFSET + 0x00000100, |
| 2aea73ce HK |
77 | .map_io = tcc8k_map_io, |
| 78 | .init_irq = tcc8k_init_irq, | |
| 79 | .init_machine = tcc8k_init, | |
| 80 | .timer = &tcc8k_timer, | |
| 81 | MACHINE_END |