projects / deliverable / linux.git / blame
| Commit | Line | Data |
|---|---|---|
| 21278aea | 1 | menuconfig ARCH_TEGRA |
| 90027225 | 2 | bool "NVIDIA Tegra" if ARCH_MULTI_V7 |
| 90027225 | 3 | select ARCH_REQUIRE_GPIOLIB |
| 1a5de3ae | 4 | select ARCH_SUPPORTS_TRUSTED_FOUNDATIONS |
| bd968d59 | 5 | select ARM_AMBA |
| 20984c44 | 6 | select ARM_GIC |
| 90027225 | 7 | select CLKSRC_MMIO |
| 4c3ffffd | 8 | select HAVE_ARM_SCU if SMP |
| a894fcc2 | 9 | select HAVE_ARM_TWD if SMP |
| 20984c44 | 10 | select PINCTRL |
| fa63aa3d | 11 | select PM_OPP |
| e0421468 SW |
12 | select ARCH_HAS_RESET_CONTROLLER |
| 13 | select RESET_CONTROLLER | |
| 90027225 | 14 | select SOC_BUS |
| 20984c44 SW |
15 | select USB_ULPI if USB_PHY |
| 16 | select USB_ULPI_VIEWPORT if USB_PHY | |
| 90027225 SW |
17 | help |
| 18 | This enables support for NVIDIA Tegra based systems. | |
| c5f80065 | 19 | |
| 21278aea | 20 | if ARCH_TEGRA |
| c5f80065 | 21 | |
| c5f80065 | 22 | config ARCH_TEGRA_2x_SOC |
| 44107d8b | 23 | bool "Enable support for Tegra20 family" |
| 1d328606 | 24 | select ARCH_NEEDS_CPU_IDLE_COUPLED if SMP |
| f35b431d | 25 | select ARM_ERRATA_720789 |
| 45c9e592 | 26 | select ARM_ERRATA_754327 if SMP |
| 8f90cce5 | 27 | select ARM_ERRATA_764369 if SMP |
| b1b3f49c | 28 | select PINCTRL_TEGRA20 |
| f35b431d SW |
29 | select PL310_ERRATA_727915 if CACHE_L2X0 |
| 30 | select PL310_ERRATA_769419 if CACHE_L2X0 | |
| 910978e7 | 31 | select TEGRA_TIMER |
| c5f80065 EG |
32 | help |
| 33 | Support for NVIDIA Tegra AP20 and T20 processors, based on the | |
| 34 | ARM CortexA9MP CPU and the ARM PL310 L2 cache controller | |
| 35 | ||
| 44107d8b PDS |
36 | config ARCH_TEGRA_3x_SOC |
| 37 | bool "Enable support for Tegra30 family" | |
| f35b431d | 38 | select ARM_ERRATA_754322 |
| 8f90cce5 | 39 | select ARM_ERRATA_764369 if SMP |
| b1b3f49c RK |
40 | select PINCTRL_TEGRA30 |
| 41 | select PL310_ERRATA_769419 if CACHE_L2X0 | |
| 910978e7 | 42 | select TEGRA_TIMER |
| 44107d8b PDS |
43 | help |
| 44 | Support for NVIDIA Tegra T30 processor family, based on the | |
| 45 | ARM CortexA9MP CPU and the ARM PL310 L2 cache controller | |
| c5f80065 | 46 | |
| 5c541b88 HD |
47 | config ARCH_TEGRA_114_SOC |
| 48 | bool "Enable support for Tegra114 family" | |
| 59fd3033 | 49 | select ARM_ERRATA_798181 if SMP |
| 5c541b88 | 50 | select ARM_L1_CACHE_SHIFT_6 |
| b6bda4e0 | 51 | select HAVE_ARM_ARCH_TIMER |
| 20fd4806 | 52 | select PINCTRL_TEGRA114 |
| 910978e7 | 53 | select TEGRA_TIMER |
| 5c541b88 HD |
54 | help |
| 55 | Support for NVIDIA Tegra T114 processor family, based on the | |
| 56 | ARM CortexA15MP CPU | |
| 57 | ||
| 73944475 JL |
58 | config ARCH_TEGRA_124_SOC |
| 59 | bool "Enable support for Tegra124 family" | |
| 60 | select ARM_L1_CACHE_SHIFT_6 | |
| 61 | select HAVE_ARM_ARCH_TIMER | |
| 7e1161f8 | 62 | select PINCTRL_TEGRA124 |
| 910978e7 | 63 | select TEGRA_TIMER |
| 73944475 JL |
64 | help |
| 65 | Support for NVIDIA Tegra T124 processor family, based on the | |
| 66 | ARM CortexA15MP CPU | |
| 67 | ||
| 21278aea | 68 | endif |