projects / deliverable / linux.git / blame
| Commit | Line | Data |
|---|---|---|
| 21278aea | 1 | menuconfig ARCH_TEGRA |
| 90027225 | 2 | bool "NVIDIA Tegra" if ARCH_MULTI_V7 |
| 90027225 | 3 | select ARCH_REQUIRE_GPIOLIB |
| 1a5de3ae | 4 | select ARCH_SUPPORTS_TRUSTED_FOUNDATIONS |
| bd968d59 | 5 | select ARM_AMBA |
| 20984c44 | 6 | select ARM_GIC |
| 90027225 | 7 | select CLKSRC_MMIO |
| 4c3ffffd | 8 | select HAVE_ARM_SCU if SMP |
| a894fcc2 | 9 | select HAVE_ARM_TWD if SMP |
| 20984c44 | 10 | select PINCTRL |
| e0421468 SW |
11 | select ARCH_HAS_RESET_CONTROLLER |
| 12 | select RESET_CONTROLLER | |
| 90027225 | 13 | select SOC_BUS |
| 20984c44 SW |
14 | select USB_ULPI if USB_PHY |
| 15 | select USB_ULPI_VIEWPORT if USB_PHY | |
| 90027225 SW |
16 | help |
| 17 | This enables support for NVIDIA Tegra based systems. | |
| c5f80065 | 18 | |
| 21278aea | 19 | if ARCH_TEGRA |
| c5f80065 | 20 | |
| c5f80065 | 21 | config ARCH_TEGRA_2x_SOC |
| 44107d8b | 22 | bool "Enable support for Tegra20 family" |
| 1d328606 | 23 | select ARCH_NEEDS_CPU_IDLE_COUPLED if SMP |
| f35b431d | 24 | select ARM_ERRATA_720789 |
| 45c9e592 | 25 | select ARM_ERRATA_754327 if SMP |
| 8f90cce5 | 26 | select ARM_ERRATA_764369 if SMP |
| b1b3f49c | 27 | select PINCTRL_TEGRA20 |
| f35b431d SW |
28 | select PL310_ERRATA_727915 if CACHE_L2X0 |
| 29 | select PL310_ERRATA_769419 if CACHE_L2X0 | |
| 910978e7 | 30 | select TEGRA_TIMER |
| c5f80065 EG |
31 | help |
| 32 | Support for NVIDIA Tegra AP20 and T20 processors, based on the | |
| 33 | ARM CortexA9MP CPU and the ARM PL310 L2 cache controller | |
| 34 | ||
| 44107d8b PDS |
35 | config ARCH_TEGRA_3x_SOC |
| 36 | bool "Enable support for Tegra30 family" | |
| f35b431d | 37 | select ARM_ERRATA_754322 |
| 8f90cce5 | 38 | select ARM_ERRATA_764369 if SMP |
| b1b3f49c RK |
39 | select PINCTRL_TEGRA30 |
| 40 | select PL310_ERRATA_769419 if CACHE_L2X0 | |
| 910978e7 | 41 | select TEGRA_TIMER |
| 44107d8b PDS |
42 | help |
| 43 | Support for NVIDIA Tegra T30 processor family, based on the | |
| 44 | ARM CortexA9MP CPU and the ARM PL310 L2 cache controller | |
| c5f80065 | 45 | |
| 5c541b88 HD |
46 | config ARCH_TEGRA_114_SOC |
| 47 | bool "Enable support for Tegra114 family" | |
| 59fd3033 | 48 | select ARM_ERRATA_798181 if SMP |
| 5c541b88 | 49 | select ARM_L1_CACHE_SHIFT_6 |
| b6bda4e0 | 50 | select HAVE_ARM_ARCH_TIMER |
| 20fd4806 | 51 | select PINCTRL_TEGRA114 |
| 910978e7 | 52 | select TEGRA_TIMER |
| 5c541b88 HD |
53 | help |
| 54 | Support for NVIDIA Tegra T114 processor family, based on the | |
| 55 | ARM CortexA15MP CPU | |
| 56 | ||
| 73944475 JL |
57 | config ARCH_TEGRA_124_SOC |
| 58 | bool "Enable support for Tegra124 family" | |
| 59 | select ARM_L1_CACHE_SHIFT_6 | |
| 60 | select HAVE_ARM_ARCH_TIMER | |
| 7e1161f8 | 61 | select PINCTRL_TEGRA124 |
| 910978e7 | 62 | select TEGRA_TIMER |
| 73944475 JL |
63 | help |
| 64 | Support for NVIDIA Tegra T124 processor family, based on the | |
| 65 | ARM CortexA15MP CPU | |
| 66 | ||
| 21278aea | 67 | endif |