[deliverable/linux.git] / arch / arm / mach-tegra / Kconfig

if ARCH_TEGRA

comment "NVIDIA Tegra options"

config ARCH_TEGRA_2x_SOC
	bool "Enable support for Tegra20 family"
	select CPU_V7
	select ARM_GIC
	select ARCH_REQUIRE_GPIOLIB
	select PINCTRL
	select PINCTRL_TEGRA20
	select USB_ARCH_HAS_EHCI if USB_SUPPORT
	select USB_ULPI if USB
	select USB_ULPI_VIEWPORT if USB_SUPPORT
	select ARM_ERRATA_720789
	select ARM_ERRATA_742230
	select ARM_ERRATA_751472
	select ARM_ERRATA_754327
	select ARM_ERRATA_764369 if SMP
	select PL310_ERRATA_727915 if CACHE_L2X0
	select PL310_ERRATA_769419 if CACHE_L2X0
	select CPU_FREQ_TABLE if CPU_FREQ
	help
	  Support for NVIDIA Tegra AP20 and T20 processors, based on the
	  ARM CortexA9MP CPU and the ARM PL310 L2 cache controller

config ARCH_TEGRA_3x_SOC
	bool "Enable support for Tegra30 family"
	select CPU_V7
	select ARM_GIC
	select ARCH_REQUIRE_GPIOLIB
	select PINCTRL
	select PINCTRL_TEGRA30
	select USB_ARCH_HAS_EHCI if USB_SUPPORT
	select USB_ULPI if USB
	select USB_ULPI_VIEWPORT if USB_SUPPORT
	select ARM_ERRATA_743622
	select ARM_ERRATA_751472
	select ARM_ERRATA_754322
	select ARM_ERRATA_764369 if SMP
	select PL310_ERRATA_769419 if CACHE_L2X0
	select CPU_FREQ_TABLE if CPU_FREQ
	help
	  Support for NVIDIA Tegra T30 processor family, based on the
	  ARM CortexA9MP CPU and the ARM PL310 L2 cache controller

config TEGRA_PCI
	bool "PCI Express support"
	depends on ARCH_TEGRA_2x_SOC
	select PCI

config TEGRA_AHB
	bool "Enable AHB driver for NVIDIA Tegra SoCs"
	default y
	help
	  Adds AHB configuration functionality for NVIDIA Tegra SoCs,
	  which controls AHB bus master arbitration and some
	  perfomance parameters(priority, prefech size).

choice
        prompt "Default low-level debug console UART"
        default TEGRA_DEBUG_UART_NONE

config TEGRA_DEBUG_UART_NONE
        bool "None"

config TEGRA_DEBUG_UARTA
        bool "UART-A"

config TEGRA_DEBUG_UARTB
        bool "UART-B"

config TEGRA_DEBUG_UARTC
        bool "UART-C"

config TEGRA_DEBUG_UARTD
        bool "UART-D"

config TEGRA_DEBUG_UARTE
        bool "UART-E"

endchoice

choice
	prompt "Automatic low-level debug console UART"
	default TEGRA_DEBUG_UART_AUTO_NONE

config TEGRA_DEBUG_UART_AUTO_NONE
	bool "None"

config TEGRA_DEBUG_UART_AUTO_ODMDATA
	bool "Via ODMDATA"
	help
	  Automatically determines which UART to use for low-level debug based
	  on the ODMDATA value. This value is part of the BCT, and is written
	  to the boot memory device using nvflash, or other flashing tool.
	  When bits 19:18 are 3, then bits 17:15 indicate which UART to use;
	  0/1/2/3/4 are UART A/B/C/D/E.

config TEGRA_DEBUG_UART_AUTO_SCRATCH
	bool "Via UART scratch register"
	help
	  Automatically determines which UART to use for low-level debug based
	  on the UART scratch register value. Some bootloaders put ASCII 'D'
	  in this register when they initialize their own console UART output.
	  Using this option allows the kernel to automatically pick the same
	  UART.

endchoice

config TEGRA_EMC_SCALING_ENABLE
	bool "Enable scaling the memory frequency"

endif
Commit	Line	Data
c5f80065 EG	1	if ARCH_TEGRA
	2
	3	comment "NVIDIA Tegra options"
	4
c5f80065	5	config ARCH_TEGRA_2x_SOC
44107d8b	6	bool "Enable support for Tegra20 family"
c5f80065 EG	7	select CPU_V7
c5f80065 EG	8	select ARM_GIC
3c92db9a	9	select ARCH_REQUIRE_GPIOLIB
f1f1ffa0 SW	10	select PINCTRL
f1f1ffa0 SW	11	select PINCTRL_TEGRA20
91525d08	12	select USB_ARCH_HAS_EHCI if USB_SUPPORT
279b6585	13	select USB_ULPI if USB
91525d08	14	select USB_ULPI_VIEWPORT if USB_SUPPORT
f35b431d SW	15	select ARM_ERRATA_720789
	16	select ARM_ERRATA_742230
	17	select ARM_ERRATA_751472
	18	select ARM_ERRATA_754327
8f90cce5	19	select ARM_ERRATA_764369 if SMP
f35b431d SW	20	select PL310_ERRATA_727915 if CACHE_L2X0
f35b431d SW	21	select PL310_ERRATA_769419 if CACHE_L2X0
013df388	22	select CPU_FREQ_TABLE if CPU_FREQ
c5f80065 EG	23	help
	24	Support for NVIDIA Tegra AP20 and T20 processors, based on the
	25	ARM CortexA9MP CPU and the ARM PL310 L2 cache controller
	26
44107d8b PDS	27	config ARCH_TEGRA_3x_SOC
	28	bool "Enable support for Tegra30 family"
	29	select CPU_V7
	30	select ARM_GIC
	31	select ARCH_REQUIRE_GPIOLIB
f1f1ffa0 SW	32	select PINCTRL
f1f1ffa0 SW	33	select PINCTRL_TEGRA30
44107d8b	34	select USB_ARCH_HAS_EHCI if USB_SUPPORT
279b6585	35	select USB_ULPI if USB
44107d8b	36	select USB_ULPI_VIEWPORT if USB_SUPPORT
f35b431d SW	37	select ARM_ERRATA_743622
	38	select ARM_ERRATA_751472
	39	select ARM_ERRATA_754322
8f90cce5	40	select ARM_ERRATA_764369 if SMP
f35b431d	41	select PL310_ERRATA_769419 if CACHE_L2X0
013df388	42	select CPU_FREQ_TABLE if CPU_FREQ
44107d8b PDS	43	help
	44	Support for NVIDIA Tegra T30 processor family, based on the
	45	ARM CortexA9MP CPU and the ARM PL310 L2 cache controller
c5f80065	46
77ffc146 MR	47	config TEGRA_PCI
77ffc146 MR	48	bool "PCI Express support"
b2bbbc4d	49	depends on ARCH_TEGRA_2x_SOC
77ffc146 MR	50	select PCI
77ffc146 MR	51
87d0bab2 HD	52	config TEGRA_AHB
	53	bool "Enable AHB driver for NVIDIA Tegra SoCs"
	54	default y
	55	help
	56	Adds AHB configuration functionality for NVIDIA Tegra SoCs,
	57	which controls AHB bus master arbitration and some
	58	perfomance parameters(priority, prefech size).
	59
c5f80065	60	choice
80881dae	61	prompt "Default low-level debug console UART"
c5f80065 EG	62	default TEGRA_DEBUG_UART_NONE
	63
	64	config TEGRA_DEBUG_UART_NONE
	65	bool "None"
	66
	67	config TEGRA_DEBUG_UARTA
	68	bool "UART-A"
	69
	70	config TEGRA_DEBUG_UARTB
	71	bool "UART-B"
	72
	73	config TEGRA_DEBUG_UARTC
	74	bool "UART-C"
	75
	76	config TEGRA_DEBUG_UARTD
	77	bool "UART-D"
	78
	79	config TEGRA_DEBUG_UARTE
	80	bool "UART-E"
	81
	82	endchoice
	83
80881dae SW	84	choice
	85	prompt "Automatic low-level debug console UART"
	86	default TEGRA_DEBUG_UART_AUTO_NONE
	87
	88	config TEGRA_DEBUG_UART_AUTO_NONE
	89	bool "None"
	90
	91	config TEGRA_DEBUG_UART_AUTO_ODMDATA
	92	bool "Via ODMDATA"
	93	help
	94	Automatically determines which UART to use for low-level debug based
	95	on the ODMDATA value. This value is part of the BCT, and is written
	96	to the boot memory device using nvflash, or other flashing tool.
	97	When bits 19:18 are 3, then bits 17:15 indicate which UART to use;
	98	0/1/2/3/4 are UART A/B/C/D/E.
	99
	100	config TEGRA_DEBUG_UART_AUTO_SCRATCH
	101	bool "Via UART scratch register"
	102	help
	103	Automatically determines which UART to use for low-level debug based
	104	on the UART scratch register value. Some bootloaders put ASCII 'D'
	105	in this register when they initialize their own console UART output.
	106	Using this option allows the kernel to automatically pick the same
	107	UART.
	108
	109	endchoice
	110
efdf72ad CC	111	config TEGRA_EMC_SCALING_ENABLE
efdf72ad CC	112	bool "Enable scaling the memory frequency"
38376866 MB	113
38376866 MB	114	endif