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8e267f3d GL |
1 | /* |
2 | * nVidia Tegra device tree board support | |
3 | * | |
4 | * Copyright (C) 2010 Secret Lab Technologies, Ltd. | |
5 | * Copyright (C) 2010 Google, Inc. | |
6 | * | |
7 | * This software is licensed under the terms of the GNU General Public | |
8 | * License version 2, as published by the Free Software Foundation, and | |
9 | * may be copied, distributed, and modified under those terms. | |
10 | * | |
11 | * This program is distributed in the hope that it will be useful, | |
12 | * but WITHOUT ANY WARRANTY; without even the implied warranty of | |
13 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
14 | * GNU General Public License for more details. | |
15 | * | |
16 | */ | |
17 | ||
18 | #include <linux/kernel.h> | |
19 | #include <linux/init.h> | |
20 | #include <linux/platform_device.h> | |
21 | #include <linux/serial_8250.h> | |
22 | #include <linux/clk.h> | |
23 | #include <linux/dma-mapping.h> | |
24 | #include <linux/irqdomain.h> | |
25 | #include <linux/of.h> | |
26 | #include <linux/of_address.h> | |
27 | #include <linux/of_fdt.h> | |
28 | #include <linux/of_irq.h> | |
29 | #include <linux/of_platform.h> | |
30 | #include <linux/pda_power.h> | |
bab53ce3 | 31 | #include <linux/platform_data/tegra_usb.h> |
8e267f3d GL |
32 | #include <linux/io.h> |
33 | #include <linux/i2c.h> | |
34 | #include <linux/i2c-tegra.h> | |
bab53ce3 | 35 | #include <linux/usb/tegra_usb_phy.h> |
8e267f3d | 36 | |
afed2a26 | 37 | #include <asm/hardware/gic.h> |
8e267f3d GL |
38 | #include <asm/mach-types.h> |
39 | #include <asm/mach/arch.h> | |
40 | #include <asm/mach/time.h> | |
41 | #include <asm/setup.h> | |
42 | ||
43 | #include <mach/iomap.h> | |
44 | #include <mach/irqs.h> | |
45 | ||
46 | #include "board.h" | |
8e267f3d | 47 | #include "clock.h" |
bab53ce3 SW |
48 | |
49 | struct tegra_ehci_platform_data tegra_ehci1_pdata = { | |
50 | .operating_mode = TEGRA_USB_OTG, | |
51 | .power_down_on_bus_suspend = 1, | |
52 | .vbus_gpio = -1, | |
53 | }; | |
54 | ||
55 | struct tegra_ulpi_config tegra_ehci2_ulpi_phy_config = { | |
56 | .reset_gpio = -1, | |
57 | .clk = "cdev2", | |
58 | }; | |
59 | ||
60 | struct tegra_ehci_platform_data tegra_ehci2_pdata = { | |
61 | .phy_config = &tegra_ehci2_ulpi_phy_config, | |
62 | .operating_mode = TEGRA_USB_HOST, | |
63 | .power_down_on_bus_suspend = 1, | |
64 | .vbus_gpio = -1, | |
65 | }; | |
66 | ||
67 | struct tegra_ehci_platform_data tegra_ehci3_pdata = { | |
68 | .operating_mode = TEGRA_USB_HOST, | |
69 | .power_down_on_bus_suspend = 1, | |
70 | .vbus_gpio = -1, | |
71 | }; | |
8e267f3d | 72 | |
8e267f3d GL |
73 | struct of_dev_auxdata tegra20_auxdata_lookup[] __initdata = { |
74 | OF_DEV_AUXDATA("nvidia,tegra20-sdhci", TEGRA_SDMMC1_BASE, "sdhci-tegra.0", NULL), | |
75 | OF_DEV_AUXDATA("nvidia,tegra20-sdhci", TEGRA_SDMMC2_BASE, "sdhci-tegra.1", NULL), | |
76 | OF_DEV_AUXDATA("nvidia,tegra20-sdhci", TEGRA_SDMMC3_BASE, "sdhci-tegra.2", NULL), | |
77 | OF_DEV_AUXDATA("nvidia,tegra20-sdhci", TEGRA_SDMMC4_BASE, "sdhci-tegra.3", NULL), | |
78 | OF_DEV_AUXDATA("nvidia,tegra20-i2c", TEGRA_I2C_BASE, "tegra-i2c.0", NULL), | |
79 | OF_DEV_AUXDATA("nvidia,tegra20-i2c", TEGRA_I2C2_BASE, "tegra-i2c.1", NULL), | |
80 | OF_DEV_AUXDATA("nvidia,tegra20-i2c", TEGRA_I2C3_BASE, "tegra-i2c.2", NULL), | |
0bc2ecb6 | 81 | OF_DEV_AUXDATA("nvidia,tegra20-i2c-dvc", TEGRA_DVC_BASE, "tegra-i2c.3", NULL), |
896637ac SW |
82 | OF_DEV_AUXDATA("nvidia,tegra20-i2s", TEGRA_I2S1_BASE, "tegra20-i2s.0", NULL), |
83 | OF_DEV_AUXDATA("nvidia,tegra20-i2s", TEGRA_I2S2_BASE, "tegra20-i2s.1", NULL), | |
84 | OF_DEV_AUXDATA("nvidia,tegra20-das", TEGRA_APB_MISC_DAS_BASE, "tegra20-das", NULL), | |
4a53f4e6 | 85 | OF_DEV_AUXDATA("nvidia,tegra20-ehci", TEGRA_USB_BASE, "tegra-ehci.0", |
8c3ec841 | 86 | &tegra_ehci1_pdata), |
4a53f4e6 | 87 | OF_DEV_AUXDATA("nvidia,tegra20-ehci", TEGRA_USB2_BASE, "tegra-ehci.1", |
8c3ec841 | 88 | &tegra_ehci2_pdata), |
4a53f4e6 | 89 | OF_DEV_AUXDATA("nvidia,tegra20-ehci", TEGRA_USB3_BASE, "tegra-ehci.2", |
8c3ec841 | 90 | &tegra_ehci3_pdata), |
9ec97169 | 91 | OF_DEV_AUXDATA("nvidia,tegra20-apbdma", TEGRA_APB_DMA_BASE, "tegra-apbdma", NULL), |
140fd977 | 92 | OF_DEV_AUXDATA("nvidia,tegra20-pwm", TEGRA_PWFM_BASE, "tegra-pwm", NULL), |
8e267f3d GL |
93 | {} |
94 | }; | |
95 | ||
96 | static __initdata struct tegra_clk_init_table tegra_dt_clk_init_table[] = { | |
97 | /* name parent rate enabled */ | |
37c241ed | 98 | { "uarta", "pll_p", 216000000, true }, |
8e267f3d | 99 | { "uartd", "pll_p", 216000000, true }, |
4a53f4e6 OJ |
100 | { "usbd", "clk_m", 12000000, false }, |
101 | { "usb2", "clk_m", 12000000, false }, | |
102 | { "usb3", "clk_m", 12000000, false }, | |
586187e2 SW |
103 | { "pll_a", "pll_p_out1", 56448000, true }, |
104 | { "pll_a_out0", "pll_a", 11289600, true }, | |
105 | { "cdev1", NULL, 0, true }, | |
106 | { "i2s1", "pll_a_out0", 11289600, false}, | |
107 | { "i2s2", "pll_a_out0", 11289600, false}, | |
8e267f3d GL |
108 | { NULL, NULL, 0, 0}, |
109 | }; | |
110 | ||
8e267f3d GL |
111 | static void __init tegra_dt_init(void) |
112 | { | |
8e267f3d GL |
113 | tegra_clk_init_from_table(tegra_dt_clk_init_table); |
114 | ||
a58116f3 SW |
115 | /* |
116 | * Finished with the static registrations now; fill in the missing | |
117 | * devices | |
118 | */ | |
2553dcc6 | 119 | of_platform_populate(NULL, of_default_bus_match_table, |
a58116f3 | 120 | tegra20_auxdata_lookup, NULL); |
8e267f3d GL |
121 | } |
122 | ||
c554dee3 SW |
123 | static void __init trimslice_init(void) |
124 | { | |
be6a9194 | 125 | #ifdef CONFIG_TEGRA_PCI |
c554dee3 SW |
126 | int ret; |
127 | ||
128 | ret = tegra_pcie_init(true, true); | |
129 | if (ret) | |
130 | pr_err("tegra_pci_init() failed: %d\n", ret); | |
c554dee3 | 131 | #endif |
be6a9194 | 132 | } |
c554dee3 | 133 | |
a12c0efc SW |
134 | static void __init harmony_init(void) |
135 | { | |
3cc404de | 136 | #ifdef CONFIG_TEGRA_PCI |
a12c0efc SW |
137 | int ret; |
138 | ||
a12c0efc SW |
139 | ret = harmony_pcie_init(); |
140 | if (ret) | |
141 | pr_err("harmony_pcie_init() failed: %d\n", ret); | |
a12c0efc | 142 | #endif |
bb25af81 | 143 | } |
a12c0efc | 144 | |
b64a02c6 SW |
145 | static void __init paz00_init(void) |
146 | { | |
147 | tegra_paz00_wifikill_init(); | |
148 | } | |
b64a02c6 | 149 | |
c554dee3 SW |
150 | static struct { |
151 | char *machine; | |
152 | void (*init)(void); | |
153 | } board_init_funcs[] = { | |
c554dee3 | 154 | { "compulab,trimslice", trimslice_init }, |
a12c0efc | 155 | { "nvidia,harmony", harmony_init }, |
b64a02c6 | 156 | { "compal,paz00", paz00_init }, |
c554dee3 SW |
157 | }; |
158 | ||
159 | static void __init tegra_dt_init_late(void) | |
160 | { | |
161 | int i; | |
162 | ||
163 | tegra_init_late(); | |
164 | ||
165 | for (i = 0; i < ARRAY_SIZE(board_init_funcs); i++) { | |
166 | if (of_machine_is_compatible(board_init_funcs[i].machine)) { | |
167 | board_init_funcs[i].init(); | |
168 | break; | |
169 | } | |
170 | } | |
171 | } | |
172 | ||
c37c07dd | 173 | static const char *tegra20_dt_board_compat[] = { |
c5444f39 | 174 | "nvidia,tegra20", |
8e267f3d GL |
175 | NULL |
176 | }; | |
177 | ||
c37c07dd | 178 | DT_MACHINE_START(TEGRA_DT, "nVidia Tegra20 (Flattened Device Tree)") |
8e267f3d | 179 | .map_io = tegra_map_common_io, |
c37c07dd | 180 | .init_early = tegra20_init_early, |
0d4f7479 | 181 | .init_irq = tegra_dt_init_irq, |
afed2a26 | 182 | .handle_irq = gic_handle_irq, |
8e267f3d GL |
183 | .timer = &tegra_timer, |
184 | .init_machine = tegra_dt_init, | |
c554dee3 | 185 | .init_late = tegra_dt_init_late, |
abea3f2c | 186 | .restart = tegra_assert_system_reset, |
c37c07dd | 187 | .dt_compat = tegra20_dt_board_compat, |
8e267f3d | 188 | MACHINE_END |