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8e267f3d GL |
1 | /* |
2 | * nVidia Tegra device tree board support | |
3 | * | |
4 | * Copyright (C) 2010 Secret Lab Technologies, Ltd. | |
5 | * Copyright (C) 2010 Google, Inc. | |
6 | * | |
7 | * This software is licensed under the terms of the GNU General Public | |
8 | * License version 2, as published by the Free Software Foundation, and | |
9 | * may be copied, distributed, and modified under those terms. | |
10 | * | |
11 | * This program is distributed in the hope that it will be useful, | |
12 | * but WITHOUT ANY WARRANTY; without even the implied warranty of | |
13 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
14 | * GNU General Public License for more details. | |
15 | * | |
16 | */ | |
17 | ||
18 | #include <linux/kernel.h> | |
19 | #include <linux/init.h> | |
20 | #include <linux/platform_device.h> | |
21 | #include <linux/serial_8250.h> | |
22 | #include <linux/clk.h> | |
23 | #include <linux/dma-mapping.h> | |
24 | #include <linux/irqdomain.h> | |
25 | #include <linux/of.h> | |
26 | #include <linux/of_address.h> | |
27 | #include <linux/of_fdt.h> | |
28 | #include <linux/of_irq.h> | |
29 | #include <linux/of_platform.h> | |
30 | #include <linux/pda_power.h> | |
31 | #include <linux/io.h> | |
32 | #include <linux/i2c.h> | |
33 | #include <linux/i2c-tegra.h> | |
34 | ||
afed2a26 | 35 | #include <asm/hardware/gic.h> |
8e267f3d GL |
36 | #include <asm/mach-types.h> |
37 | #include <asm/mach/arch.h> | |
38 | #include <asm/mach/time.h> | |
39 | #include <asm/setup.h> | |
40 | ||
41 | #include <mach/iomap.h> | |
42 | #include <mach/irqs.h> | |
43 | ||
44 | #include "board.h" | |
45 | #include "board-harmony.h" | |
46 | #include "clock.h" | |
47 | #include "devices.h" | |
48 | ||
8e267f3d GL |
49 | struct of_dev_auxdata tegra20_auxdata_lookup[] __initdata = { |
50 | OF_DEV_AUXDATA("nvidia,tegra20-sdhci", TEGRA_SDMMC1_BASE, "sdhci-tegra.0", NULL), | |
51 | OF_DEV_AUXDATA("nvidia,tegra20-sdhci", TEGRA_SDMMC2_BASE, "sdhci-tegra.1", NULL), | |
52 | OF_DEV_AUXDATA("nvidia,tegra20-sdhci", TEGRA_SDMMC3_BASE, "sdhci-tegra.2", NULL), | |
53 | OF_DEV_AUXDATA("nvidia,tegra20-sdhci", TEGRA_SDMMC4_BASE, "sdhci-tegra.3", NULL), | |
54 | OF_DEV_AUXDATA("nvidia,tegra20-i2c", TEGRA_I2C_BASE, "tegra-i2c.0", NULL), | |
55 | OF_DEV_AUXDATA("nvidia,tegra20-i2c", TEGRA_I2C2_BASE, "tegra-i2c.1", NULL), | |
56 | OF_DEV_AUXDATA("nvidia,tegra20-i2c", TEGRA_I2C3_BASE, "tegra-i2c.2", NULL), | |
0bc2ecb6 | 57 | OF_DEV_AUXDATA("nvidia,tegra20-i2c-dvc", TEGRA_DVC_BASE, "tegra-i2c.3", NULL), |
896637ac SW |
58 | OF_DEV_AUXDATA("nvidia,tegra20-i2s", TEGRA_I2S1_BASE, "tegra20-i2s.0", NULL), |
59 | OF_DEV_AUXDATA("nvidia,tegra20-i2s", TEGRA_I2S2_BASE, "tegra20-i2s.1", NULL), | |
60 | OF_DEV_AUXDATA("nvidia,tegra20-das", TEGRA_APB_MISC_DAS_BASE, "tegra20-das", NULL), | |
4a53f4e6 | 61 | OF_DEV_AUXDATA("nvidia,tegra20-ehci", TEGRA_USB_BASE, "tegra-ehci.0", |
8c3ec841 | 62 | &tegra_ehci1_pdata), |
4a53f4e6 | 63 | OF_DEV_AUXDATA("nvidia,tegra20-ehci", TEGRA_USB2_BASE, "tegra-ehci.1", |
8c3ec841 | 64 | &tegra_ehci2_pdata), |
4a53f4e6 | 65 | OF_DEV_AUXDATA("nvidia,tegra20-ehci", TEGRA_USB3_BASE, "tegra-ehci.2", |
8c3ec841 | 66 | &tegra_ehci3_pdata), |
8e267f3d GL |
67 | {} |
68 | }; | |
69 | ||
70 | static __initdata struct tegra_clk_init_table tegra_dt_clk_init_table[] = { | |
71 | /* name parent rate enabled */ | |
72 | { "uartd", "pll_p", 216000000, true }, | |
4a53f4e6 OJ |
73 | { "usbd", "clk_m", 12000000, false }, |
74 | { "usb2", "clk_m", 12000000, false }, | |
75 | { "usb3", "clk_m", 12000000, false }, | |
586187e2 SW |
76 | { "pll_a", "pll_p_out1", 56448000, true }, |
77 | { "pll_a_out0", "pll_a", 11289600, true }, | |
78 | { "cdev1", NULL, 0, true }, | |
79 | { "i2s1", "pll_a_out0", 11289600, false}, | |
80 | { "i2s2", "pll_a_out0", 11289600, false}, | |
8e267f3d GL |
81 | { NULL, NULL, 0, 0}, |
82 | }; | |
83 | ||
84 | static struct of_device_id tegra_dt_match_table[] __initdata = { | |
85 | { .compatible = "simple-bus", }, | |
86 | {} | |
87 | }; | |
88 | ||
8e267f3d GL |
89 | static void __init tegra_dt_init(void) |
90 | { | |
8e267f3d GL |
91 | tegra_clk_init_from_table(tegra_dt_clk_init_table); |
92 | ||
a58116f3 SW |
93 | /* |
94 | * Finished with the static registrations now; fill in the missing | |
95 | * devices | |
96 | */ | |
97 | of_platform_populate(NULL, tegra_dt_match_table, | |
98 | tegra20_auxdata_lookup, NULL); | |
8e267f3d GL |
99 | } |
100 | ||
c554dee3 SW |
101 | #ifdef CONFIG_MACH_TRIMSLICE |
102 | static void __init trimslice_init(void) | |
103 | { | |
104 | int ret; | |
105 | ||
106 | ret = tegra_pcie_init(true, true); | |
107 | if (ret) | |
108 | pr_err("tegra_pci_init() failed: %d\n", ret); | |
109 | } | |
110 | #endif | |
111 | ||
112 | static struct { | |
113 | char *machine; | |
114 | void (*init)(void); | |
115 | } board_init_funcs[] = { | |
116 | #ifdef CONFIG_MACH_TRIMSLICE | |
117 | { "compulab,trimslice", trimslice_init }, | |
118 | #endif | |
119 | }; | |
120 | ||
121 | static void __init tegra_dt_init_late(void) | |
122 | { | |
123 | int i; | |
124 | ||
125 | tegra_init_late(); | |
126 | ||
127 | for (i = 0; i < ARRAY_SIZE(board_init_funcs); i++) { | |
128 | if (of_machine_is_compatible(board_init_funcs[i].machine)) { | |
129 | board_init_funcs[i].init(); | |
130 | break; | |
131 | } | |
132 | } | |
133 | } | |
134 | ||
c37c07dd | 135 | static const char *tegra20_dt_board_compat[] = { |
c5444f39 | 136 | "nvidia,tegra20", |
8e267f3d GL |
137 | NULL |
138 | }; | |
139 | ||
c37c07dd | 140 | DT_MACHINE_START(TEGRA_DT, "nVidia Tegra20 (Flattened Device Tree)") |
8e267f3d | 141 | .map_io = tegra_map_common_io, |
c37c07dd | 142 | .init_early = tegra20_init_early, |
0d4f7479 | 143 | .init_irq = tegra_dt_init_irq, |
afed2a26 | 144 | .handle_irq = gic_handle_irq, |
8e267f3d GL |
145 | .timer = &tegra_timer, |
146 | .init_machine = tegra_dt_init, | |
c554dee3 | 147 | .init_late = tegra_dt_init_late, |
abea3f2c | 148 | .restart = tegra_assert_system_reset, |
c37c07dd | 149 | .dt_compat = tegra20_dt_board_compat, |
8e267f3d | 150 | MACHINE_END |