[deliverable/linux.git] / arch / arm / mach-tegra / clock.h

/*
 * arch/arm/mach-tegra/include/mach/clock.h
 *
 * Copyright (C) 2010 Google, Inc.
 * Copyright (c) 2012 NVIDIA CORPORATION.  All rights reserved.
 *
 * Author:
 *	Colin Cross <ccross@google.com>
 *
 * This software is licensed under the terms of the GNU General Public
 * License version 2, as published by the Free Software Foundation, and
 * may be copied, distributed, and modified under those terms.
 *
 * This program is distributed in the hope that it will be useful,
 * but WITHOUT ANY WARRANTY; without even the implied warranty of
 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
 * GNU General Public License for more details.
 *
 */

#ifndef __MACH_TEGRA_CLOCK_H
#define __MACH_TEGRA_CLOCK_H

#include <linux/clk-provider.h>
#include <linux/clkdev.h>
#include <linux/list.h>

#include <mach/clk.h>

#define DIV_BUS			(1 << 0)
#define DIV_U71			(1 << 1)
#define DIV_U71_FIXED		(1 << 2)
#define DIV_2			(1 << 3)
#define DIV_U16			(1 << 4)
#define PLL_FIXED		(1 << 5)
#define PLL_HAS_CPCON		(1 << 6)
#define MUX			(1 << 7)
#define PLLD			(1 << 8)
#define PERIPH_NO_RESET		(1 << 9)
#define PERIPH_NO_ENB		(1 << 10)
#define PERIPH_EMC_ENB		(1 << 11)
#define PERIPH_MANUAL_RESET	(1 << 12)
#define PLL_ALT_MISC_REG	(1 << 13)
#define PLLU			(1 << 14)
#define PLLX                    (1 << 15)
#define MUX_PWM                 (1 << 16)
#define MUX8                    (1 << 17)
#define DIV_U71_UART            (1 << 18)
#define MUX_CLK_OUT             (1 << 19)
#define PLLM                    (1 << 20)
#define DIV_U71_INT             (1 << 21)
#define DIV_U71_IDLE            (1 << 22)
#define ENABLE_ON_INIT		(1 << 28)
#define PERIPH_ON_APB           (1 << 29)

struct clk_tegra;
#define to_clk_tegra(_hw) container_of(_hw, struct clk_tegra, hw)

struct clk_mux_sel {
	struct clk	*input;
	u32		value;
};

struct clk_pll_freq_table {
	unsigned long	input_rate;
	unsigned long	output_rate;
	u16		n;
	u16		m;
	u8		p;
	u8		cpcon;
};

enum clk_state {
	UNINITIALIZED = 0,
	ON,
	OFF,
};

struct clk_tegra {
	/* node for master clocks list */
	struct list_head	node;	/* node for list of all clocks */
	struct clk_lookup	lookup;
	struct clk_hw		hw;

	bool			set;
	unsigned long		fixed_rate;
	unsigned long		max_rate;
	unsigned long		min_rate;
	u32			flags;
	const char		*name;

	enum clk_state		state;
	u32			div;
	u32			mul;

	u32				reg;
	u32				reg_shift;

	struct list_head		shared_bus_list;

	union {
		struct {
			unsigned int			clk_num;
		} periph;
		struct {
			unsigned long			input_min;
			unsigned long			input_max;
			unsigned long			cf_min;
			unsigned long			cf_max;
			unsigned long			vco_min;
			unsigned long			vco_max;
			const struct clk_pll_freq_table	*freq_table;
			int				lock_delay;
			unsigned long			fixed_rate;
		} pll;
		struct {
			u32				sel;
			u32				reg_mask;
		} mux;
		struct {
			struct clk			*main;
			struct clk			*backup;
		} cpu;
		struct {
			struct list_head		node;
			bool				enabled;
			unsigned long			rate;
		} shared_bus_user;
	} u;

	void (*reset)(struct clk_hw *, bool);
	int (*clk_cfg_ex)(struct clk_hw *, enum tegra_clk_ex_param, u32);
};

struct clk_duplicate {
	const char *name;
	struct clk_lookup lookup;
};

struct tegra_clk_init_table {
	const char *name;
	const char *parent;
	unsigned long rate;
	bool enabled;
};

void tegra_clk_add(struct clk *c);
void tegra2_init_clocks(void);
void tegra30_init_clocks(void);
struct clk *tegra_get_clock_by_name(const char *name);
void tegra_clk_init_from_table(struct tegra_clk_init_table *table);

#endif
Commit	Line	Data
d8611961 CC	1	/*
	2	* arch/arm/mach-tegra/include/mach/clock.h
	3	*
	4	* Copyright (C) 2010 Google, Inc.
96a1bd1e	5	* Copyright (c) 2012 NVIDIA CORPORATION. All rights reserved.
d8611961 CC	6	*
	7	* Author:
	8	* Colin Cross <ccross@google.com>
	9	*
	10	* This software is licensed under the terms of the GNU General Public
	11	* License version 2, as published by the Free Software Foundation, and
	12	* may be copied, distributed, and modified under those terms.
	13	*
	14	* This program is distributed in the hope that it will be useful,
	15	* but WITHOUT ANY WARRANTY; without even the implied warranty of
	16	* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
	17	* GNU General Public License for more details.
	18	*
	19	*/
	20
	21	#ifndef __MACH_TEGRA_CLOCK_H
	22	#define __MACH_TEGRA_CLOCK_H
	23
96a1bd1e	24	#include <linux/clk-provider.h>
6d803ba7	25	#include <linux/clkdev.h>
4729fd7a	26	#include <linux/list.h>
d8611961	27
4fccf75b PDS	28	#include <mach/clk.h>
4fccf75b PDS	29
d8611961 CC	30	#define DIV_BUS (1 << 0)
	31	#define DIV_U71 (1 << 1)
	32	#define DIV_U71_FIXED (1 << 2)
	33	#define DIV_2 (1 << 3)
71fc84cc CC	34	#define DIV_U16 (1 << 4)
	35	#define PLL_FIXED (1 << 5)
	36	#define PLL_HAS_CPCON (1 << 6)
	37	#define MUX (1 << 7)
	38	#define PLLD (1 << 8)
	39	#define PERIPH_NO_RESET (1 << 9)
	40	#define PERIPH_NO_ENB (1 << 10)
	41	#define PERIPH_EMC_ENB (1 << 11)
	42	#define PERIPH_MANUAL_RESET (1 << 12)
	43	#define PLL_ALT_MISC_REG (1 << 13)
	44	#define PLLU (1 << 14)
4fccf75b PDS	45	#define PLLX (1 << 15)
	46	#define MUX_PWM (1 << 16)
	47	#define MUX8 (1 << 17)
	48	#define DIV_U71_UART (1 << 18)
	49	#define MUX_CLK_OUT (1 << 19)
	50	#define PLLM (1 << 20)
	51	#define DIV_U71_INT (1 << 21)
	52	#define DIV_U71_IDLE (1 << 22)
d8611961	53	#define ENABLE_ON_INIT (1 << 28)
4fccf75b	54	#define PERIPH_ON_APB (1 << 29)
d8611961	55
96a1bd1e PG	56	struct clk_tegra;
96a1bd1e PG	57	#define to_clk_tegra(_hw) container_of(_hw, struct clk_tegra, hw)
96a1bd1e	58
d8611961 CC	59	struct clk_mux_sel {
	60	struct clk *input;
	61	u32 value;
	62	};
	63
f1519611	64	struct clk_pll_freq_table {
d8611961 CC	65	unsigned long input_rate;
	66	unsigned long output_rate;
	67	u16 n;
	68	u16 m;
	69	u8 p;
	70	u8 cpcon;
	71	};
	72
96a1bd1e PG	73	enum clk_state {
	74	UNINITIALIZED = 0,
	75	ON,
	76	OFF,
	77	};
	78
96a1bd1e PG	79	struct clk_tegra {
	80	/* node for master clocks list */
	81	struct list_head node; /* node for list of all clocks */
	82	struct clk_lookup lookup;
	83	struct clk_hw hw;
	84
	85	bool set;
	86	unsigned long fixed_rate;
	87	unsigned long max_rate;
	88	unsigned long min_rate;
	89	u32 flags;
	90	const char *name;
	91
	92	enum clk_state state;
	93	u32 div;
	94	u32 mul;
	95
	96	u32 reg;
	97	u32 reg_shift;
	98
	99	struct list_head shared_bus_list;
	100
	101	union {
	102	struct {
	103	unsigned int clk_num;
	104	} periph;
	105	struct {
	106	unsigned long input_min;
	107	unsigned long input_max;
	108	unsigned long cf_min;
	109	unsigned long cf_max;
	110	unsigned long vco_min;
	111	unsigned long vco_max;
	112	const struct clk_pll_freq_table *freq_table;
	113	int lock_delay;
	114	unsigned long fixed_rate;
	115	} pll;
	116	struct {
	117	u32 sel;
	118	u32 reg_mask;
	119	} mux;
	120	struct {
	121	struct clk *main;
	122	struct clk *backup;
	123	} cpu;
	124	struct {
	125	struct list_head node;
	126	bool enabled;
	127	unsigned long rate;
	128	} shared_bus_user;
	129	} u;
	130
	131	void (reset)(struct clk_hw , bool);
	132	int (clk_cfg_ex)(struct clk_hw , enum tegra_clk_ex_param, u32);
	133	};
96a1bd1e	134
d8611961 CC	135	struct clk_duplicate {
	136	const char *name;
	137	struct clk_lookup lookup;
	138	};
	139
	140	struct tegra_clk_init_table {
	141	const char *name;
	142	const char *parent;
	143	unsigned long rate;
	144	bool enabled;
	145	};
	146
92fe58f0	147	void tegra_clk_add(struct clk *c);
d8611961	148	void tegra2_init_clocks(void);
7ff43eea	149	void tegra30_init_clocks(void);
d8611961	150	struct clk tegra_get_clock_by_name(const char name);
d8611961 CC	151	void tegra_clk_init_from_table(struct tegra_clk_init_table *table);
	152
	153	#endif