Commit | Line | Data |
---|---|---|
c5f80065 | 1 | /* |
c37c07dd | 2 | * arch/arm/mach-tegra/common.c |
c5f80065 EG |
3 | * |
4 | * Copyright (C) 2010 Google, Inc. | |
5 | * | |
6 | * Author: | |
7 | * Colin Cross <ccross@android.com> | |
8 | * | |
9 | * This software is licensed under the terms of the GNU General Public | |
10 | * License version 2, as published by the Free Software Foundation, and | |
11 | * may be copied, distributed, and modified under those terms. | |
12 | * | |
13 | * This program is distributed in the hope that it will be useful, | |
14 | * but WITHOUT ANY WARRANTY; without even the implied warranty of | |
15 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
16 | * GNU General Public License for more details. | |
17 | * | |
18 | */ | |
19 | ||
20 | #include <linux/init.h> | |
21 | #include <linux/io.h> | |
4de3a8fa CC |
22 | #include <linux/clk.h> |
23 | #include <linux/delay.h> | |
c37c07dd | 24 | #include <linux/of_irq.h> |
c5f80065 EG |
25 | |
26 | #include <asm/hardware/cache-l2x0.h> | |
c37c07dd | 27 | #include <asm/hardware/gic.h> |
c5f80065 | 28 | |
65fe31da | 29 | #include <mach/powergate.h> |
c5f80065 EG |
30 | |
31 | #include "board.h" | |
d8611961 | 32 | #include "clock.h" |
a1725732 | 33 | #include "common.h" |
73625e3e | 34 | #include "fuse.h" |
2be39c07 | 35 | #include "iomap.h" |
d3b8bdd5 | 36 | #include "pmc.h" |
b861c275 | 37 | #include "apbio.h" |
59b0f682 | 38 | #include "sleep.h" |
29a0e7be | 39 | #include "pm.h" |
d8611961 | 40 | |
6d7d7b3e SW |
41 | /* |
42 | * Storage for debug-macro.S's state. | |
43 | * | |
44 | * This must be in .data not .bss so that it gets initialized each time the | |
45 | * kernel is loaded. The data is declared here rather than debug-macro.S so | |
46 | * that multiple inclusions of debug-macro.S point at the same data. | |
47 | */ | |
1a6d3da8 | 48 | u32 tegra_uart_config[4] = { |
6d7d7b3e SW |
49 | /* Debug UART initialization required */ |
50 | 1, | |
51 | /* Debug UART physical address */ | |
adc18315 | 52 | 0, |
6d7d7b3e | 53 | /* Debug UART virtual address */ |
adc18315 | 54 | 0, |
1a6d3da8 SW |
55 | /* Scratch space for debug macro */ |
56 | 0, | |
6d7d7b3e | 57 | }; |
d8611961 | 58 | |
6cc04a44 | 59 | #ifdef CONFIG_OF |
c37c07dd PDS |
60 | static const struct of_device_id tegra_dt_irq_match[] __initconst = { |
61 | { .compatible = "arm,cortex-a9-gic", .data = gic_of_init }, | |
62 | { } | |
63 | }; | |
64 | ||
65 | void __init tegra_dt_init_irq(void) | |
66 | { | |
67 | tegra_init_irq(); | |
68 | of_irq_init(tegra_dt_irq_match); | |
69 | } | |
6cc04a44 | 70 | #endif |
c37c07dd | 71 | |
699fe145 CC |
72 | void tegra_assert_system_reset(char mode, const char *cmd) |
73 | { | |
9bfc3f0d | 74 | void __iomem *reset = IO_ADDRESS(TEGRA_PMC_BASE + 0); |
699fe145 CC |
75 | u32 reg; |
76 | ||
375b19cd | 77 | reg = readl_relaxed(reset); |
9bfc3f0d | 78 | reg |= 0x10; |
375b19cd | 79 | writel_relaxed(reg, reset); |
699fe145 CC |
80 | } |
81 | ||
c37c07dd PDS |
82 | #ifdef CONFIG_ARCH_TEGRA_2x_SOC |
83 | static __initdata struct tegra_clk_init_table tegra20_clk_init_table[] = { | |
d8611961 CC |
84 | /* name parent rate enabled */ |
85 | { "clk_m", NULL, 0, true }, | |
86 | { "pll_p", "clk_m", 216000000, true }, | |
87 | { "pll_p_out1", "pll_p", 28800000, true }, | |
88 | { "pll_p_out2", "pll_p", 48000000, true }, | |
89 | { "pll_p_out3", "pll_p", 72000000, true }, | |
9abafa02 | 90 | { "pll_p_out4", "pll_p", 24000000, true }, |
60f975b9 SW |
91 | { "pll_c", "clk_m", 600000000, true }, |
92 | { "pll_c_out1", "pll_c", 120000000, true }, | |
93 | { "sclk", "pll_c_out1", 120000000, true }, | |
94 | { "hclk", "sclk", 120000000, true }, | |
7ff4db09 | 95 | { "pclk", "hclk", 60000000, true }, |
cd51d0ed CC |
96 | { "csite", NULL, 0, true }, |
97 | { "emc", NULL, 0, true }, | |
98 | { "cpu", NULL, 0, true }, | |
d8611961 CC |
99 | { NULL, NULL, 0, 0}, |
100 | }; | |
c37c07dd | 101 | #endif |
c5f80065 | 102 | |
64376269 PDS |
103 | #ifdef CONFIG_ARCH_TEGRA_3x_SOC |
104 | static __initdata struct tegra_clk_init_table tegra30_clk_init_table[] = { | |
105 | /* name parent rate enabled */ | |
106 | { "clk_m", NULL, 0, true }, | |
6eb583da | 107 | { "pll_p", "pll_ref", 408000000, true }, |
64376269 | 108 | { "pll_p_out1", "pll_p", 9600000, true }, |
d534b5d4 JL |
109 | { "pll_p_out4", "pll_p", 102000000, true }, |
110 | { "sclk", "pll_p_out4", 102000000, true }, | |
111 | { "hclk", "sclk", 102000000, true }, | |
112 | { "pclk", "hclk", 51000000, true }, | |
fe508d77 | 113 | { "csite", NULL, 0, true }, |
64376269 PDS |
114 | { NULL, NULL, 0, 0}, |
115 | }; | |
116 | #endif | |
117 | ||
118 | ||
d065ab71 | 119 | static void __init tegra_init_cache(void) |
c5f80065 EG |
120 | { |
121 | #ifdef CONFIG_CACHE_L2X0 | |
29a0e7be | 122 | int ret; |
c5f80065 | 123 | void __iomem *p = IO_ADDRESS(TEGRA_ARM_PERIF_BASE) + 0x3000; |
01548673 | 124 | u32 aux_ctrl, cache_type; |
c5f80065 | 125 | |
01548673 PDS |
126 | cache_type = readl(p + L2X0_CACHE_TYPE); |
127 | aux_ctrl = (cache_type & 0x700) << (17-8); | |
fd072a86 | 128 | aux_ctrl |= 0x7C400001; |
01548673 | 129 | |
29a0e7be JL |
130 | ret = l2x0_of_init(aux_ctrl, 0x8200c3fe); |
131 | if (!ret) | |
132 | l2x0_saved_regs_addr = virt_to_phys(&l2x0_saved_regs); | |
c5f80065 | 133 | #endif |
4de3a8fa | 134 | |
c5f80065 EG |
135 | } |
136 | ||
c37c07dd PDS |
137 | #ifdef CONFIG_ARCH_TEGRA_2x_SOC |
138 | void __init tegra20_init_early(void) | |
c5f80065 | 139 | { |
b861c275 | 140 | tegra_apb_io_init(); |
73625e3e | 141 | tegra_init_fuse(); |
c37c07dd PDS |
142 | tegra2_init_clocks(); |
143 | tegra_clk_init_from_table(tegra20_clk_init_table); | |
d065ab71 | 144 | tegra_init_cache(); |
d3b8bdd5 | 145 | tegra_pmc_init(); |
65fe31da | 146 | tegra_powergate_init(); |
453689e4 | 147 | tegra20_hotplug_init(); |
c5f80065 | 148 | } |
c37c07dd | 149 | #endif |
44107d8b PDS |
150 | #ifdef CONFIG_ARCH_TEGRA_3x_SOC |
151 | void __init tegra30_init_early(void) | |
152 | { | |
b861c275 | 153 | tegra_apb_io_init(); |
cec60064 | 154 | tegra_init_fuse(); |
7ff43eea | 155 | tegra30_init_clocks(); |
64376269 | 156 | tegra_clk_init_from_table(tegra30_clk_init_table); |
d065ab71 | 157 | tegra_init_cache(); |
d3b8bdd5 | 158 | tegra_pmc_init(); |
65fe31da | 159 | tegra_powergate_init(); |
59b0f682 | 160 | tegra30_hotplug_init(); |
44107d8b PDS |
161 | } |
162 | #endif | |
390e0cfd SG |
163 | |
164 | void __init tegra_init_late(void) | |
165 | { | |
390e0cfd SG |
166 | tegra_powergate_debugfs_init(); |
167 | } |