Commit | Line | Data |
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c5f80065 | 1 | /* |
c37c07dd | 2 | * arch/arm/mach-tegra/common.c |
c5f80065 EG |
3 | * |
4 | * Copyright (C) 2010 Google, Inc. | |
5 | * | |
6 | * Author: | |
7 | * Colin Cross <ccross@android.com> | |
8 | * | |
9 | * This software is licensed under the terms of the GNU General Public | |
10 | * License version 2, as published by the Free Software Foundation, and | |
11 | * may be copied, distributed, and modified under those terms. | |
12 | * | |
13 | * This program is distributed in the hope that it will be useful, | |
14 | * but WITHOUT ANY WARRANTY; without even the implied warranty of | |
15 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
16 | * GNU General Public License for more details. | |
17 | * | |
18 | */ | |
19 | ||
20 | #include <linux/init.h> | |
21 | #include <linux/io.h> | |
4de3a8fa CC |
22 | #include <linux/clk.h> |
23 | #include <linux/delay.h> | |
c37c07dd | 24 | #include <linux/of_irq.h> |
c5f80065 EG |
25 | |
26 | #include <asm/hardware/cache-l2x0.h> | |
c37c07dd | 27 | #include <asm/hardware/gic.h> |
c5f80065 EG |
28 | |
29 | #include <mach/iomap.h> | |
699fe145 | 30 | #include <mach/system.h> |
c5f80065 EG |
31 | |
32 | #include "board.h" | |
d8611961 | 33 | #include "clock.h" |
73625e3e | 34 | #include "fuse.h" |
d8611961 | 35 | |
699fe145 CC |
36 | void (*arch_reset)(char mode, const char *cmd) = tegra_assert_system_reset; |
37 | ||
c37c07dd PDS |
38 | static const struct of_device_id tegra_dt_irq_match[] __initconst = { |
39 | { .compatible = "arm,cortex-a9-gic", .data = gic_of_init }, | |
40 | { } | |
41 | }; | |
42 | ||
43 | void __init tegra_dt_init_irq(void) | |
44 | { | |
45 | tegra_init_irq(); | |
46 | of_irq_init(tegra_dt_irq_match); | |
47 | } | |
48 | ||
699fe145 CC |
49 | void tegra_assert_system_reset(char mode, const char *cmd) |
50 | { | |
9bfc3f0d | 51 | void __iomem *reset = IO_ADDRESS(TEGRA_PMC_BASE + 0); |
699fe145 CC |
52 | u32 reg; |
53 | ||
375b19cd | 54 | reg = readl_relaxed(reset); |
9bfc3f0d | 55 | reg |= 0x10; |
375b19cd | 56 | writel_relaxed(reg, reset); |
699fe145 CC |
57 | } |
58 | ||
c37c07dd PDS |
59 | #ifdef CONFIG_ARCH_TEGRA_2x_SOC |
60 | static __initdata struct tegra_clk_init_table tegra20_clk_init_table[] = { | |
d8611961 CC |
61 | /* name parent rate enabled */ |
62 | { "clk_m", NULL, 0, true }, | |
63 | { "pll_p", "clk_m", 216000000, true }, | |
64 | { "pll_p_out1", "pll_p", 28800000, true }, | |
65 | { "pll_p_out2", "pll_p", 48000000, true }, | |
66 | { "pll_p_out3", "pll_p", 72000000, true }, | |
67 | { "pll_p_out4", "pll_p", 108000000, true }, | |
8486bddc CC |
68 | { "sclk", "pll_p_out4", 108000000, true }, |
69 | { "hclk", "sclk", 108000000, true }, | |
d8611961 | 70 | { "pclk", "hclk", 54000000, true }, |
cd51d0ed CC |
71 | { "csite", NULL, 0, true }, |
72 | { "emc", NULL, 0, true }, | |
73 | { "cpu", NULL, 0, true }, | |
d8611961 CC |
74 | { NULL, NULL, 0, 0}, |
75 | }; | |
c37c07dd | 76 | #endif |
c5f80065 | 77 | |
74ae6c3c | 78 | static void __init tegra_init_cache(void) |
c5f80065 EG |
79 | { |
80 | #ifdef CONFIG_CACHE_L2X0 | |
81 | void __iomem *p = IO_ADDRESS(TEGRA_ARM_PERIF_BASE) + 0x3000; | |
82 | ||
535371c3 CC |
83 | writel_relaxed(0x331, p + L2X0_TAG_LATENCY_CTRL); |
84 | writel_relaxed(0x441, p + L2X0_DATA_LATENCY_CTRL); | |
c5f80065 EG |
85 | |
86 | l2x0_init(p, 0x6C080001, 0x8200c3fe); | |
87 | #endif | |
4de3a8fa | 88 | |
c5f80065 EG |
89 | } |
90 | ||
c37c07dd PDS |
91 | #ifdef CONFIG_ARCH_TEGRA_2x_SOC |
92 | void __init tegra20_init_early(void) | |
c5f80065 | 93 | { |
73625e3e | 94 | tegra_init_fuse(); |
c37c07dd PDS |
95 | tegra2_init_clocks(); |
96 | tegra_clk_init_from_table(tegra20_clk_init_table); | |
c5f80065 EG |
97 | tegra_init_cache(); |
98 | } | |
c37c07dd | 99 | #endif |