Commit | Line | Data |
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c5f80065 | 1 | /* |
c37c07dd | 2 | * arch/arm/mach-tegra/common.c |
c5f80065 EG |
3 | * |
4 | * Copyright (C) 2010 Google, Inc. | |
5 | * | |
6 | * Author: | |
7 | * Colin Cross <ccross@android.com> | |
8 | * | |
9 | * This software is licensed under the terms of the GNU General Public | |
10 | * License version 2, as published by the Free Software Foundation, and | |
11 | * may be copied, distributed, and modified under those terms. | |
12 | * | |
13 | * This program is distributed in the hope that it will be useful, | |
14 | * but WITHOUT ANY WARRANTY; without even the implied warranty of | |
15 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
16 | * GNU General Public License for more details. | |
17 | * | |
18 | */ | |
19 | ||
20 | #include <linux/init.h> | |
21 | #include <linux/io.h> | |
4de3a8fa CC |
22 | #include <linux/clk.h> |
23 | #include <linux/delay.h> | |
c37c07dd | 24 | #include <linux/of_irq.h> |
c5f80065 EG |
25 | |
26 | #include <asm/hardware/cache-l2x0.h> | |
c37c07dd | 27 | #include <asm/hardware/gic.h> |
c5f80065 EG |
28 | |
29 | #include <mach/iomap.h> | |
65fe31da | 30 | #include <mach/powergate.h> |
c5f80065 EG |
31 | |
32 | #include "board.h" | |
d8611961 | 33 | #include "clock.h" |
73625e3e | 34 | #include "fuse.h" |
d3b8bdd5 | 35 | #include "pmc.h" |
d8611961 | 36 | |
6d7d7b3e SW |
37 | /* |
38 | * Storage for debug-macro.S's state. | |
39 | * | |
40 | * This must be in .data not .bss so that it gets initialized each time the | |
41 | * kernel is loaded. The data is declared here rather than debug-macro.S so | |
42 | * that multiple inclusions of debug-macro.S point at the same data. | |
43 | */ | |
44 | #define TEGRA_DEBUG_UART_OFFSET (TEGRA_DEBUG_UART_BASE & 0xFFFF) | |
45 | u32 tegra_uart_config[3] = { | |
46 | /* Debug UART initialization required */ | |
47 | 1, | |
48 | /* Debug UART physical address */ | |
49 | (u32)(IO_APB_PHYS + TEGRA_DEBUG_UART_OFFSET), | |
50 | /* Debug UART virtual address */ | |
51 | (u32)(IO_APB_VIRT + TEGRA_DEBUG_UART_OFFSET), | |
52 | }; | |
d8611961 | 53 | |
6cc04a44 | 54 | #ifdef CONFIG_OF |
c37c07dd PDS |
55 | static const struct of_device_id tegra_dt_irq_match[] __initconst = { |
56 | { .compatible = "arm,cortex-a9-gic", .data = gic_of_init }, | |
57 | { } | |
58 | }; | |
59 | ||
60 | void __init tegra_dt_init_irq(void) | |
61 | { | |
62 | tegra_init_irq(); | |
63 | of_irq_init(tegra_dt_irq_match); | |
64 | } | |
6cc04a44 | 65 | #endif |
c37c07dd | 66 | |
699fe145 CC |
67 | void tegra_assert_system_reset(char mode, const char *cmd) |
68 | { | |
9bfc3f0d | 69 | void __iomem *reset = IO_ADDRESS(TEGRA_PMC_BASE + 0); |
699fe145 CC |
70 | u32 reg; |
71 | ||
375b19cd | 72 | reg = readl_relaxed(reset); |
9bfc3f0d | 73 | reg |= 0x10; |
375b19cd | 74 | writel_relaxed(reg, reset); |
699fe145 CC |
75 | } |
76 | ||
c37c07dd PDS |
77 | #ifdef CONFIG_ARCH_TEGRA_2x_SOC |
78 | static __initdata struct tegra_clk_init_table tegra20_clk_init_table[] = { | |
d8611961 CC |
79 | /* name parent rate enabled */ |
80 | { "clk_m", NULL, 0, true }, | |
81 | { "pll_p", "clk_m", 216000000, true }, | |
82 | { "pll_p_out1", "pll_p", 28800000, true }, | |
83 | { "pll_p_out2", "pll_p", 48000000, true }, | |
84 | { "pll_p_out3", "pll_p", 72000000, true }, | |
85 | { "pll_p_out4", "pll_p", 108000000, true }, | |
8486bddc CC |
86 | { "sclk", "pll_p_out4", 108000000, true }, |
87 | { "hclk", "sclk", 108000000, true }, | |
d8611961 | 88 | { "pclk", "hclk", 54000000, true }, |
cd51d0ed CC |
89 | { "csite", NULL, 0, true }, |
90 | { "emc", NULL, 0, true }, | |
91 | { "cpu", NULL, 0, true }, | |
d8611961 CC |
92 | { NULL, NULL, 0, 0}, |
93 | }; | |
c37c07dd | 94 | #endif |
c5f80065 | 95 | |
01548673 | 96 | static void __init tegra_init_cache(u32 tag_latency, u32 data_latency) |
c5f80065 EG |
97 | { |
98 | #ifdef CONFIG_CACHE_L2X0 | |
99 | void __iomem *p = IO_ADDRESS(TEGRA_ARM_PERIF_BASE) + 0x3000; | |
01548673 | 100 | u32 aux_ctrl, cache_type; |
c5f80065 | 101 | |
01548673 PDS |
102 | writel_relaxed(tag_latency, p + L2X0_TAG_LATENCY_CTRL); |
103 | writel_relaxed(data_latency, p + L2X0_DATA_LATENCY_CTRL); | |
c5f80065 | 104 | |
01548673 PDS |
105 | cache_type = readl(p + L2X0_CACHE_TYPE); |
106 | aux_ctrl = (cache_type & 0x700) << (17-8); | |
107 | aux_ctrl |= 0x6C000001; | |
108 | ||
109 | l2x0_init(p, aux_ctrl, 0x8200c3fe); | |
c5f80065 | 110 | #endif |
4de3a8fa | 111 | |
c5f80065 EG |
112 | } |
113 | ||
c37c07dd PDS |
114 | #ifdef CONFIG_ARCH_TEGRA_2x_SOC |
115 | void __init tegra20_init_early(void) | |
c5f80065 | 116 | { |
73625e3e | 117 | tegra_init_fuse(); |
c37c07dd PDS |
118 | tegra2_init_clocks(); |
119 | tegra_clk_init_from_table(tegra20_clk_init_table); | |
01548673 | 120 | tegra_init_cache(0x331, 0x441); |
d3b8bdd5 | 121 | tegra_pmc_init(); |
65fe31da | 122 | tegra_powergate_init(); |
c5f80065 | 123 | } |
c37c07dd | 124 | #endif |
44107d8b PDS |
125 | #ifdef CONFIG_ARCH_TEGRA_3x_SOC |
126 | void __init tegra30_init_early(void) | |
127 | { | |
cec60064 | 128 | tegra_init_fuse(); |
7ff43eea | 129 | tegra30_init_clocks(); |
44107d8b | 130 | tegra_init_cache(0x441, 0x551); |
d3b8bdd5 | 131 | tegra_pmc_init(); |
65fe31da | 132 | tegra_powergate_init(); |
44107d8b PDS |
133 | } |
134 | #endif |