Commit | Line | Data |
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c5f80065 | 1 | /* |
c37c07dd | 2 | * arch/arm/mach-tegra/common.c |
c5f80065 EG |
3 | * |
4 | * Copyright (C) 2010 Google, Inc. | |
5 | * | |
6 | * Author: | |
7 | * Colin Cross <ccross@android.com> | |
8 | * | |
9 | * This software is licensed under the terms of the GNU General Public | |
10 | * License version 2, as published by the Free Software Foundation, and | |
11 | * may be copied, distributed, and modified under those terms. | |
12 | * | |
13 | * This program is distributed in the hope that it will be useful, | |
14 | * but WITHOUT ANY WARRANTY; without even the implied warranty of | |
15 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
16 | * GNU General Public License for more details. | |
17 | * | |
18 | */ | |
19 | ||
20 | #include <linux/init.h> | |
21 | #include <linux/io.h> | |
4de3a8fa CC |
22 | #include <linux/clk.h> |
23 | #include <linux/delay.h> | |
c37c07dd | 24 | #include <linux/of_irq.h> |
c5f80065 EG |
25 | |
26 | #include <asm/hardware/cache-l2x0.h> | |
c37c07dd | 27 | #include <asm/hardware/gic.h> |
c5f80065 | 28 | |
65fe31da | 29 | #include <mach/powergate.h> |
c5f80065 EG |
30 | |
31 | #include "board.h" | |
d8611961 | 32 | #include "clock.h" |
a1725732 | 33 | #include "common.h" |
73625e3e | 34 | #include "fuse.h" |
2be39c07 | 35 | #include "iomap.h" |
d3b8bdd5 | 36 | #include "pmc.h" |
b861c275 | 37 | #include "apbio.h" |
59b0f682 | 38 | #include "sleep.h" |
d8611961 | 39 | |
6d7d7b3e SW |
40 | /* |
41 | * Storage for debug-macro.S's state. | |
42 | * | |
43 | * This must be in .data not .bss so that it gets initialized each time the | |
44 | * kernel is loaded. The data is declared here rather than debug-macro.S so | |
45 | * that multiple inclusions of debug-macro.S point at the same data. | |
46 | */ | |
47 | #define TEGRA_DEBUG_UART_OFFSET (TEGRA_DEBUG_UART_BASE & 0xFFFF) | |
48 | u32 tegra_uart_config[3] = { | |
49 | /* Debug UART initialization required */ | |
50 | 1, | |
51 | /* Debug UART physical address */ | |
52 | (u32)(IO_APB_PHYS + TEGRA_DEBUG_UART_OFFSET), | |
53 | /* Debug UART virtual address */ | |
54 | (u32)(IO_APB_VIRT + TEGRA_DEBUG_UART_OFFSET), | |
55 | }; | |
d8611961 | 56 | |
6cc04a44 | 57 | #ifdef CONFIG_OF |
c37c07dd PDS |
58 | static const struct of_device_id tegra_dt_irq_match[] __initconst = { |
59 | { .compatible = "arm,cortex-a9-gic", .data = gic_of_init }, | |
60 | { } | |
61 | }; | |
62 | ||
63 | void __init tegra_dt_init_irq(void) | |
64 | { | |
65 | tegra_init_irq(); | |
66 | of_irq_init(tegra_dt_irq_match); | |
67 | } | |
6cc04a44 | 68 | #endif |
c37c07dd | 69 | |
699fe145 CC |
70 | void tegra_assert_system_reset(char mode, const char *cmd) |
71 | { | |
9bfc3f0d | 72 | void __iomem *reset = IO_ADDRESS(TEGRA_PMC_BASE + 0); |
699fe145 CC |
73 | u32 reg; |
74 | ||
375b19cd | 75 | reg = readl_relaxed(reset); |
9bfc3f0d | 76 | reg |= 0x10; |
375b19cd | 77 | writel_relaxed(reg, reset); |
699fe145 CC |
78 | } |
79 | ||
c37c07dd PDS |
80 | #ifdef CONFIG_ARCH_TEGRA_2x_SOC |
81 | static __initdata struct tegra_clk_init_table tegra20_clk_init_table[] = { | |
d8611961 CC |
82 | /* name parent rate enabled */ |
83 | { "clk_m", NULL, 0, true }, | |
84 | { "pll_p", "clk_m", 216000000, true }, | |
85 | { "pll_p_out1", "pll_p", 28800000, true }, | |
86 | { "pll_p_out2", "pll_p", 48000000, true }, | |
87 | { "pll_p_out3", "pll_p", 72000000, true }, | |
9abafa02 | 88 | { "pll_p_out4", "pll_p", 24000000, true }, |
60f975b9 SW |
89 | { "pll_c", "clk_m", 600000000, true }, |
90 | { "pll_c_out1", "pll_c", 120000000, true }, | |
91 | { "sclk", "pll_c_out1", 120000000, true }, | |
92 | { "hclk", "sclk", 120000000, true }, | |
7ff4db09 | 93 | { "pclk", "hclk", 60000000, true }, |
cd51d0ed CC |
94 | { "csite", NULL, 0, true }, |
95 | { "emc", NULL, 0, true }, | |
96 | { "cpu", NULL, 0, true }, | |
d8611961 CC |
97 | { NULL, NULL, 0, 0}, |
98 | }; | |
c37c07dd | 99 | #endif |
c5f80065 | 100 | |
64376269 PDS |
101 | #ifdef CONFIG_ARCH_TEGRA_3x_SOC |
102 | static __initdata struct tegra_clk_init_table tegra30_clk_init_table[] = { | |
103 | /* name parent rate enabled */ | |
104 | { "clk_m", NULL, 0, true }, | |
105 | { "pll_p", "clk_m", 408000000, true }, | |
106 | { "pll_p_out1", "pll_p", 9600000, true }, | |
d534b5d4 JL |
107 | { "pll_p_out4", "pll_p", 102000000, true }, |
108 | { "sclk", "pll_p_out4", 102000000, true }, | |
109 | { "hclk", "sclk", 102000000, true }, | |
110 | { "pclk", "hclk", 51000000, true }, | |
64376269 PDS |
111 | { NULL, NULL, 0, 0}, |
112 | }; | |
113 | #endif | |
114 | ||
115 | ||
d065ab71 | 116 | static void __init tegra_init_cache(void) |
c5f80065 EG |
117 | { |
118 | #ifdef CONFIG_CACHE_L2X0 | |
119 | void __iomem *p = IO_ADDRESS(TEGRA_ARM_PERIF_BASE) + 0x3000; | |
01548673 | 120 | u32 aux_ctrl, cache_type; |
c5f80065 | 121 | |
01548673 PDS |
122 | cache_type = readl(p + L2X0_CACHE_TYPE); |
123 | aux_ctrl = (cache_type & 0x700) << (17-8); | |
fd072a86 | 124 | aux_ctrl |= 0x7C400001; |
01548673 | 125 | |
d065ab71 | 126 | l2x0_of_init(aux_ctrl, 0x8200c3fe); |
c5f80065 | 127 | #endif |
4de3a8fa | 128 | |
c5f80065 EG |
129 | } |
130 | ||
c37c07dd PDS |
131 | #ifdef CONFIG_ARCH_TEGRA_2x_SOC |
132 | void __init tegra20_init_early(void) | |
c5f80065 | 133 | { |
b861c275 | 134 | tegra_apb_io_init(); |
73625e3e | 135 | tegra_init_fuse(); |
c37c07dd PDS |
136 | tegra2_init_clocks(); |
137 | tegra_clk_init_from_table(tegra20_clk_init_table); | |
d065ab71 | 138 | tegra_init_cache(); |
d3b8bdd5 | 139 | tegra_pmc_init(); |
65fe31da | 140 | tegra_powergate_init(); |
453689e4 | 141 | tegra20_hotplug_init(); |
c5f80065 | 142 | } |
c37c07dd | 143 | #endif |
44107d8b PDS |
144 | #ifdef CONFIG_ARCH_TEGRA_3x_SOC |
145 | void __init tegra30_init_early(void) | |
146 | { | |
b861c275 | 147 | tegra_apb_io_init(); |
cec60064 | 148 | tegra_init_fuse(); |
7ff43eea | 149 | tegra30_init_clocks(); |
64376269 | 150 | tegra_clk_init_from_table(tegra30_clk_init_table); |
d065ab71 | 151 | tegra_init_cache(); |
d3b8bdd5 | 152 | tegra_pmc_init(); |
65fe31da | 153 | tegra_powergate_init(); |
59b0f682 | 154 | tegra30_hotplug_init(); |
44107d8b PDS |
155 | } |
156 | #endif | |
390e0cfd SG |
157 | |
158 | void __init tegra_init_late(void) | |
159 | { | |
390e0cfd SG |
160 | tegra_powergate_debugfs_init(); |
161 | } |