[deliverable/linux.git] / arch / arm / mach-tegra / cpuidle-tegra20.c

/*
 * CPU idle driver for Tegra CPUs
 *
 * Copyright (c) 2010-2012, NVIDIA Corporation.
 * Copyright (c) 2011 Google, Inc.
 * Author: Colin Cross <ccross@android.com>
 *         Gary King <gking@nvidia.com>
 *
 * Rework for 3.3 by Peter De Schrijver <pdeschrijver@nvidia.com>
 *
 * This program is free software; you can redistribute it and/or modify
 * it under the terms of the GNU General Public License as published by
 * the Free Software Foundation; either version 2 of the License, or
 * (at your option) any later version.
 *
 * This program is distributed in the hope that it will be useful, but WITHOUT
 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
 * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
 * more details.
 */

#include <linux/kernel.h>
#include <linux/module.h>
#include <linux/cpuidle.h>
#include <linux/cpu_pm.h>
#include <linux/clockchips.h>
#include <linux/clk/tegra.h>

#include <asm/cpuidle.h>
#include <asm/proc-fns.h>
#include <asm/suspend.h>
#include <asm/smp_plat.h>

#include "pm.h"
#include "sleep.h"
#include "iomap.h"
#include "irq.h"
#include "flowctrl.h"

#ifdef CONFIG_PM_SLEEP
static bool abort_flag;
static atomic_t abort_barrier;
static int tegra20_idle_lp2_coupled(struct cpuidle_device *dev,
				    struct cpuidle_driver *drv,
				    int index);
#endif

static struct cpuidle_state tegra_idle_states[] = {
	[0] = ARM_CPUIDLE_WFI_STATE_PWR(600),
#ifdef CONFIG_PM_SLEEP
	[1] = {
		.enter			= tegra20_idle_lp2_coupled,
		.exit_latency		= 5000,
		.target_residency	= 10000,
		.power_usage		= 0,
		.flags			= CPUIDLE_FLAG_TIME_VALID |
					  CPUIDLE_FLAG_COUPLED,
		.name			= "powered-down",
		.desc			= "CPU power gated",
	},
#endif
};

static struct cpuidle_driver tegra_idle_driver = {
	.name = "tegra_idle",
	.owner = THIS_MODULE,
	.en_core_tk_irqen = 1,
};

static DEFINE_PER_CPU(struct cpuidle_device, tegra_idle_device);

#ifdef CONFIG_PM_SLEEP
#ifdef CONFIG_SMP
static void __iomem *pmc = IO_ADDRESS(TEGRA_PMC_BASE);

static int tegra20_reset_sleeping_cpu_1(void)
{
	int ret = 0;

	tegra_pen_lock();

	if (readl(pmc + PMC_SCRATCH41) == CPU_RESETTABLE)
		tegra20_cpu_shutdown(1);
	else
		ret = -EINVAL;

	tegra_pen_unlock();

	return ret;
}

static void tegra20_wake_cpu1_from_reset(void)
{
	tegra_pen_lock();

	tegra20_cpu_clear_resettable();

	/* enable cpu clock on cpu */
	tegra_enable_cpu_clock(1);

	/* take the CPU out of reset */
	tegra_cpu_out_of_reset(1);

	/* unhalt the cpu */
	flowctrl_write_cpu_halt(1, 0);

	tegra_pen_unlock();
}

static int tegra20_reset_cpu_1(void)
{
	if (!cpu_online(1) || !tegra20_reset_sleeping_cpu_1())
		return 0;

	tegra20_wake_cpu1_from_reset();
	return -EBUSY;
}
#else
static inline void tegra20_wake_cpu1_from_reset(void)
{
}

static inline int tegra20_reset_cpu_1(void)
{
	return 0;
}
#endif

static bool tegra20_cpu_cluster_power_down(struct cpuidle_device *dev,
					   struct cpuidle_driver *drv,
					   int index)
{
	struct cpuidle_state *state = &drv->states[index];
	u32 cpu_on_time = state->exit_latency;
	u32 cpu_off_time = state->target_residency - state->exit_latency;

	while (tegra20_cpu_is_resettable_soon())
		cpu_relax();

	if (tegra20_reset_cpu_1() || !tegra_cpu_rail_off_ready())
		return false;

	clockevents_notify(CLOCK_EVT_NOTIFY_BROADCAST_ENTER, &dev->cpu);

	tegra_idle_lp2_last(cpu_on_time, cpu_off_time);

	clockevents_notify(CLOCK_EVT_NOTIFY_BROADCAST_EXIT, &dev->cpu);

	if (cpu_online(1))
		tegra20_wake_cpu1_from_reset();

	return true;
}

#ifdef CONFIG_SMP
static bool tegra20_idle_enter_lp2_cpu_1(struct cpuidle_device *dev,
					 struct cpuidle_driver *drv,
					 int index)
{
	clockevents_notify(CLOCK_EVT_NOTIFY_BROADCAST_ENTER, &dev->cpu);

	cpu_suspend(0, tegra20_sleep_cpu_secondary_finish);

	tegra20_cpu_clear_resettable();

	clockevents_notify(CLOCK_EVT_NOTIFY_BROADCAST_EXIT, &dev->cpu);

	return true;
}
#else
static inline bool tegra20_idle_enter_lp2_cpu_1(struct cpuidle_device *dev,
						struct cpuidle_driver *drv,
						int index)
{
	return true;
}
#endif

static int tegra20_idle_lp2_coupled(struct cpuidle_device *dev,
				    struct cpuidle_driver *drv,
				    int index)
{
	u32 cpu = is_smp() ? cpu_logical_map(dev->cpu) : dev->cpu;
	bool entered_lp2 = false;

	if (tegra_pending_sgi())
		ACCESS_ONCE(abort_flag) = true;

	cpuidle_coupled_parallel_barrier(dev, &abort_barrier);

	if (abort_flag) {
		cpuidle_coupled_parallel_barrier(dev, &abort_barrier);
		abort_flag = false;	/* clean flag for next coming */
		return -EINTR;
	}

	local_fiq_disable();

	tegra_set_cpu_in_lp2(cpu);
	cpu_pm_enter();

	if (cpu == 0)
		entered_lp2 = tegra20_cpu_cluster_power_down(dev, drv, index);
	else
		entered_lp2 = tegra20_idle_enter_lp2_cpu_1(dev, drv, index);

	cpu_pm_exit();
	tegra_clear_cpu_in_lp2(cpu);

	local_fiq_enable();

	smp_rmb();

	return entered_lp2 ? index : 0;
}
#endif

int __init tegra20_cpuidle_init(void)
{
	int ret;
	unsigned int cpu;
	struct cpuidle_device *dev;
	struct cpuidle_driver *drv = &tegra_idle_driver;

#ifdef CONFIG_PM_SLEEP
	tegra_tear_down_cpu = tegra20_tear_down_cpu;
#endif

	drv->state_count = ARRAY_SIZE(tegra_idle_states);
	memcpy(drv->states, tegra_idle_states,
			drv->state_count * sizeof(drv->states[0]));

	ret = cpuidle_register_driver(&tegra_idle_driver);
	if (ret) {
		pr_err("CPUidle driver registration failed\n");
		return ret;
	}

	for_each_possible_cpu(cpu) {
		dev = &per_cpu(tegra_idle_device, cpu);
		dev->cpu = cpu;
#ifdef CONFIG_ARCH_NEEDS_CPU_IDLE_COUPLED
		dev->coupled_cpus = *cpu_possible_mask;
#endif

		dev->state_count = drv->state_count;
		ret = cpuidle_register_device(dev);
		if (ret) {
			pr_err("CPU%u: CPUidle device registration failed\n",
				cpu);
			return ret;
		}
	}
	return 0;
}
Commit	Line	Data
0b25e25b JL	1	/*
	2	* CPU idle driver for Tegra CPUs
	3	*
	4	* Copyright (c) 2010-2012, NVIDIA Corporation.
	5	* Copyright (c) 2011 Google, Inc.
	6	* Author: Colin Cross <ccross@android.com>
	7	* Gary King <gking@nvidia.com>
	8	*
	9	* Rework for 3.3 by Peter De Schrijver <pdeschrijver@nvidia.com>
	10	*
	11	* This program is free software; you can redistribute it and/or modify
	12	* it under the terms of the GNU General Public License as published by
	13	* the Free Software Foundation; either version 2 of the License, or
	14	* (at your option) any later version.
	15	*
	16	* This program is distributed in the hope that it will be useful, but WITHOUT
	17	* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
	18	* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
	19	* more details.
	20	*/
	21
	22	#include <linux/kernel.h>
	23	#include <linux/module.h>
	24	#include <linux/cpuidle.h>
5c1350bd JL	25	#include <linux/cpu_pm.h>
5c1350bd JL	26	#include <linux/clockchips.h>
1d328606	27	#include <linux/clk/tegra.h>
0b25e25b JL	28
0b25e25b JL	29	#include <asm/cpuidle.h>
5c1350bd JL	30	#include <asm/proc-fns.h>
	31	#include <asm/suspend.h>
	32	#include <asm/smp_plat.h>
	33
	34	#include "pm.h"
	35	#include "sleep.h"
1d328606 JL	36	#include "iomap.h"
	37	#include "irq.h"
	38	#include "flowctrl.h"
5c1350bd JL	39
5c1350bd JL	40	#ifdef CONFIG_PM_SLEEP
1d328606 JL	41	static bool abort_flag;
	42	static atomic_t abort_barrier;
	43	static int tegra20_idle_lp2_coupled(struct cpuidle_device *dev,
	44	struct cpuidle_driver *drv,
	45	int index);
5c1350bd JL	46	#endif
	47
	48	static struct cpuidle_state tegra_idle_states[] = {
	49	[0] = ARM_CPUIDLE_WFI_STATE_PWR(600),
	50	#ifdef CONFIG_PM_SLEEP
	51	[1] = {
1d328606	52	.enter = tegra20_idle_lp2_coupled,
5c1350bd JL	53	.exit_latency = 5000,
	54	.target_residency = 10000,
	55	.power_usage = 0,
1d328606 JL	56	.flags = CPUIDLE_FLAG_TIME_VALID \|
1d328606 JL	57	CPUIDLE_FLAG_COUPLED,
5c1350bd JL	58	.name = "powered-down",
	59	.desc = "CPU power gated",
	60	},
	61	#endif
	62	};
0b25e25b JL	63
	64	static struct cpuidle_driver tegra_idle_driver = {
	65	.name = "tegra_idle",
	66	.owner = THIS_MODULE,
	67	.en_core_tk_irqen = 1,
0b25e25b JL	68	};
	69
	70	static DEFINE_PER_CPU(struct cpuidle_device, tegra_idle_device);
	71
5c1350bd	72	#ifdef CONFIG_PM_SLEEP
1d328606 JL	73	#ifdef CONFIG_SMP
	74	static void __iomem *pmc = IO_ADDRESS(TEGRA_PMC_BASE);
	75
	76	static int tegra20_reset_sleeping_cpu_1(void)
	77	{
	78	int ret = 0;
	79
	80	tegra_pen_lock();
	81
	82	if (readl(pmc + PMC_SCRATCH41) == CPU_RESETTABLE)
	83	tegra20_cpu_shutdown(1);
	84	else
	85	ret = -EINVAL;
	86
	87	tegra_pen_unlock();
	88
	89	return ret;
	90	}
	91
	92	static void tegra20_wake_cpu1_from_reset(void)
	93	{
	94	tegra_pen_lock();
	95
	96	tegra20_cpu_clear_resettable();
	97
	98	/* enable cpu clock on cpu */
	99	tegra_enable_cpu_clock(1);
	100
	101	/* take the CPU out of reset */
	102	tegra_cpu_out_of_reset(1);
	103
	104	/* unhalt the cpu */
	105	flowctrl_write_cpu_halt(1, 0);
	106
	107	tegra_pen_unlock();
	108	}
	109
	110	static int tegra20_reset_cpu_1(void)
	111	{
	112	if (!cpu_online(1) \|\| !tegra20_reset_sleeping_cpu_1())
	113	return 0;
	114
	115	tegra20_wake_cpu1_from_reset();
	116	return -EBUSY;
	117	}
	118	#else
	119	static inline void tegra20_wake_cpu1_from_reset(void)
	120	{
	121	}
	122
	123	static inline int tegra20_reset_cpu_1(void)
	124	{
	125	return 0;
	126	}
	127	#endif
	128
	129	static bool tegra20_cpu_cluster_power_down(struct cpuidle_device *dev,
	130	struct cpuidle_driver *drv,
	131	int index)
	132	{
	133	struct cpuidle_state *state = &drv->states[index];
	134	u32 cpu_on_time = state->exit_latency;
	135	u32 cpu_off_time = state->target_residency - state->exit_latency;
	136
137	while (tegra20_cpu_is_resettable_soon())
138	cpu_relax();
139
140	if (tegra20_reset_cpu_1() \|\| !tegra_cpu_rail_off_ready())
141	return false;
142
143	clockevents_notify(CLOCK_EVT_NOTIFY_BROADCAST_ENTER, &dev->cpu);
144
145	tegra_idle_lp2_last(cpu_on_time, cpu_off_time);
146
147	clockevents_notify(CLOCK_EVT_NOTIFY_BROADCAST_EXIT, &dev->cpu);
148
149	if (cpu_online(1))
150	tegra20_wake_cpu1_from_reset();
151
152	return true;
153	}
154
5c1350bd JL	155	#ifdef CONFIG_SMP
	156	static bool tegra20_idle_enter_lp2_cpu_1(struct cpuidle_device *dev,
	157	struct cpuidle_driver *drv,
	158	int index)
	159	{
	160	clockevents_notify(CLOCK_EVT_NOTIFY_BROADCAST_ENTER, &dev->cpu);
	161
	162	cpu_suspend(0, tegra20_sleep_cpu_secondary_finish);
	163
	164	tegra20_cpu_clear_resettable();
	165
	166	clockevents_notify(CLOCK_EVT_NOTIFY_BROADCAST_EXIT, &dev->cpu);
	167
	168	return true;
	169	}
	170	#else
	171	static inline bool tegra20_idle_enter_lp2_cpu_1(struct cpuidle_device *dev,
	172	struct cpuidle_driver *drv,
	173	int index)
	174	{
	175	return true;
	176	}
	177	#endif
	178
1d328606 JL	179	static int tegra20_idle_lp2_coupled(struct cpuidle_device *dev,
	180	struct cpuidle_driver *drv,
	181	int index)
5c1350bd JL	182	{
	183	u32 cpu = is_smp() ? cpu_logical_map(dev->cpu) : dev->cpu;
	184	bool entered_lp2 = false;
	185
1d328606 JL	186	if (tegra_pending_sgi())
	187	ACCESS_ONCE(abort_flag) = true;
	188
	189	cpuidle_coupled_parallel_barrier(dev, &abort_barrier);
	190
	191	if (abort_flag) {
	192	cpuidle_coupled_parallel_barrier(dev, &abort_barrier);
	193	abort_flag = false; /* clean flag for next coming */
	194	return -EINTR;
	195	}
	196
5c1350bd JL	197	local_fiq_disable();
	198
	199	tegra_set_cpu_in_lp2(cpu);
	200	cpu_pm_enter();
	201
	202	if (cpu == 0)
1d328606	203	entered_lp2 = tegra20_cpu_cluster_power_down(dev, drv, index);
5c1350bd JL	204	else
	205	entered_lp2 = tegra20_idle_enter_lp2_cpu_1(dev, drv, index);
	206
	207	cpu_pm_exit();
	208	tegra_clear_cpu_in_lp2(cpu);
	209
	210	local_fiq_enable();
	211
	212	smp_rmb();
	213
	214	return entered_lp2 ? index : 0;
	215	}
	216	#endif
	217
0b25e25b JL	218	int __init tegra20_cpuidle_init(void)
	219	{
	220	int ret;
	221	unsigned int cpu;
	222	struct cpuidle_device *dev;
	223	struct cpuidle_driver *drv = &tegra_idle_driver;
	224
1d328606 JL	225	#ifdef CONFIG_PM_SLEEP
	226	tegra_tear_down_cpu = tegra20_tear_down_cpu;
	227	#endif
	228
5c1350bd JL	229	drv->state_count = ARRAY_SIZE(tegra_idle_states);
	230	memcpy(drv->states, tegra_idle_states,
	231	drv->state_count * sizeof(drv->states[0]));
	232
0b25e25b JL	233	ret = cpuidle_register_driver(&tegra_idle_driver);
	234	if (ret) {
	235	pr_err("CPUidle driver registration failed\n");
	236	return ret;
	237	}
	238
	239	for_each_possible_cpu(cpu) {
	240	dev = &per_cpu(tegra_idle_device, cpu);
	241	dev->cpu = cpu;
1d328606 JL	242	#ifdef CONFIG_ARCH_NEEDS_CPU_IDLE_COUPLED
	243	dev->coupled_cpus = *cpu_possible_mask;
	244	#endif
0b25e25b JL	245
	246	dev->state_count = drv->state_count;
	247	ret = cpuidle_register_device(dev);
	248	if (ret) {
	249	pr_err("CPU%u: CPUidle device registration failed\n",
	250	cpu);
	251	return ret;
	252	}
	253	}
	254	return 0;
	255	}