[deliverable/linux.git] / arch / arm / mach-tegra / cpuidle-tegra30.c

/*
 * CPU idle driver for Tegra CPUs
 *
 * Copyright (c) 2010-2012, NVIDIA Corporation.
 * Copyright (c) 2011 Google, Inc.
 * Author: Colin Cross <ccross@android.com>
 *         Gary King <gking@nvidia.com>
 *
 * Rework for 3.3 by Peter De Schrijver <pdeschrijver@nvidia.com>
 *
 * This program is free software; you can redistribute it and/or modify
 * it under the terms of the GNU General Public License as published by
 * the Free Software Foundation; either version 2 of the License, or
 * (at your option) any later version.
 *
 * This program is distributed in the hope that it will be useful, but WITHOUT
 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
 * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
 * more details.
 */

#include <linux/kernel.h>
#include <linux/module.h>
#include <linux/cpuidle.h>
#include <linux/cpu_pm.h>
#include <linux/clockchips.h>
#include <linux/clk/tegra.h>

#include <asm/cpuidle.h>
#include <asm/proc-fns.h>
#include <asm/suspend.h>
#include <asm/smp_plat.h>

#include "pm.h"
#include "sleep.h"

#ifdef CONFIG_PM_SLEEP
static int tegra30_idle_lp2(struct cpuidle_device *dev,
			    struct cpuidle_driver *drv,
			    int index);
#endif

static struct cpuidle_driver tegra_idle_driver = {
	.name = "tegra_idle",
	.owner = THIS_MODULE,
#ifdef CONFIG_PM_SLEEP
	.state_count = 2,
#else
	.state_count = 1,
#endif
	.states = {
		[0] = ARM_CPUIDLE_WFI_STATE_PWR(600),
#ifdef CONFIG_PM_SLEEP
		[1] = {
			.enter			= tegra30_idle_lp2,
			.exit_latency		= 2000,
			.target_residency	= 2200,
			.power_usage		= 0,
			.flags			= CPUIDLE_FLAG_TIME_VALID,
			.name			= "powered-down",
			.desc			= "CPU power gated",
		},
#endif
	},
};

#ifdef CONFIG_PM_SLEEP
static bool tegra30_cpu_cluster_power_down(struct cpuidle_device *dev,
					   struct cpuidle_driver *drv,
					   int index)
{
	/* All CPUs entering LP2 is not working.
	 * Don't let CPU0 enter LP2 when any secondary CPU is online.
	 */
	if (num_online_cpus() > 1 || !tegra_cpu_rail_off_ready()) {
		cpu_do_idle();
		return false;
	}

	clockevents_notify(CLOCK_EVT_NOTIFY_BROADCAST_ENTER, &dev->cpu);

	tegra_idle_lp2_last();

	clockevents_notify(CLOCK_EVT_NOTIFY_BROADCAST_EXIT, &dev->cpu);

	return true;
}

#ifdef CONFIG_SMP
static bool tegra30_cpu_core_power_down(struct cpuidle_device *dev,
					struct cpuidle_driver *drv,
					int index)
{
	clockevents_notify(CLOCK_EVT_NOTIFY_BROADCAST_ENTER, &dev->cpu);

	smp_wmb();

	cpu_suspend(0, tegra30_sleep_cpu_secondary_finish);

	clockevents_notify(CLOCK_EVT_NOTIFY_BROADCAST_EXIT, &dev->cpu);

	return true;
}
#else
static inline bool tegra30_cpu_core_power_down(struct cpuidle_device *dev,
					       struct cpuidle_driver *drv,
					       int index)
{
	return true;
}
#endif

static int tegra30_idle_lp2(struct cpuidle_device *dev,
			    struct cpuidle_driver *drv,
			    int index)
{
	bool entered_lp2 = false;
	bool last_cpu;

	local_fiq_disable();

	last_cpu = tegra_set_cpu_in_lp2();
	cpu_pm_enter();

	if (dev->cpu == 0) {
		if (last_cpu)
			entered_lp2 = tegra30_cpu_cluster_power_down(dev, drv,
								     index);
		else
			cpu_do_idle();
	} else {
		entered_lp2 = tegra30_cpu_core_power_down(dev, drv, index);
	}

	cpu_pm_exit();
	tegra_clear_cpu_in_lp2();

	local_fiq_enable();

	smp_rmb();

	return (entered_lp2) ? index : 0;
}
#endif

int __init tegra30_cpuidle_init(void)
{
	return cpuidle_register(&tegra_idle_driver, NULL);
}
Commit	Line	Data
0b25e25b JL	1	/*
	2	* CPU idle driver for Tegra CPUs
	3	*
	4	* Copyright (c) 2010-2012, NVIDIA Corporation.
	5	* Copyright (c) 2011 Google, Inc.
	6	* Author: Colin Cross <ccross@android.com>
	7	* Gary King <gking@nvidia.com>
	8	*
	9	* Rework for 3.3 by Peter De Schrijver <pdeschrijver@nvidia.com>
	10	*
	11	* This program is free software; you can redistribute it and/or modify
	12	* it under the terms of the GNU General Public License as published by
	13	* the Free Software Foundation; either version 2 of the License, or
	14	* (at your option) any later version.
	15	*
	16	* This program is distributed in the hope that it will be useful, but WITHOUT
	17	* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
	18	* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
	19	* more details.
	20	*/
	21
	22	#include <linux/kernel.h>
	23	#include <linux/module.h>
	24	#include <linux/cpuidle.h>
d457ef35 JL	25	#include <linux/cpu_pm.h>
d457ef35 JL	26	#include <linux/clockchips.h>
89572c77	27	#include <linux/clk/tegra.h>
0b25e25b JL	28
0b25e25b JL	29	#include <asm/cpuidle.h>
d457ef35 JL	30	#include <asm/proc-fns.h>
	31	#include <asm/suspend.h>
	32	#include <asm/smp_plat.h>
	33
	34	#include "pm.h"
	35	#include "sleep.h"
	36
	37	#ifdef CONFIG_PM_SLEEP
	38	static int tegra30_idle_lp2(struct cpuidle_device *dev,
	39	struct cpuidle_driver *drv,
	40	int index);
	41	#endif
0b25e25b JL	42
	43	static struct cpuidle_driver tegra_idle_driver = {
	44	.name = "tegra_idle",
	45	.owner = THIS_MODULE,
d457ef35 JL	46	#ifdef CONFIG_PM_SLEEP
	47	.state_count = 2,
	48	#else
0b25e25b	49	.state_count = 1,
d457ef35	50	#endif
0b25e25b JL	51	.states = {
0b25e25b JL	52	[0] = ARM_CPUIDLE_WFI_STATE_PWR(600),
d457ef35 JL	53	#ifdef CONFIG_PM_SLEEP
	54	[1] = {
	55	.enter = tegra30_idle_lp2,
	56	.exit_latency = 2000,
	57	.target_residency = 2200,
	58	.power_usage = 0,
	59	.flags = CPUIDLE_FLAG_TIME_VALID,
	60	.name = "powered-down",
	61	.desc = "CPU power gated",
	62	},
	63	#endif
0b25e25b JL	64	},
	65	};
	66
d457ef35	67	#ifdef CONFIG_PM_SLEEP
d552920a JL	68	static bool tegra30_cpu_cluster_power_down(struct cpuidle_device *dev,
	69	struct cpuidle_driver *drv,
	70	int index)
	71	{
d552920a JL	72	/* All CPUs entering LP2 is not working.
	73	* Don't let CPU0 enter LP2 when any secondary CPU is online.
	74	*/
	75	if (num_online_cpus() > 1 \|\| !tegra_cpu_rail_off_ready()) {
	76	cpu_do_idle();
	77	return false;
	78	}
	79
	80	clockevents_notify(CLOCK_EVT_NOTIFY_BROADCAST_ENTER, &dev->cpu);
	81
4d82d058	82	tegra_idle_lp2_last();
d552920a JL	83
	84	clockevents_notify(CLOCK_EVT_NOTIFY_BROADCAST_EXIT, &dev->cpu);
	85
	86	return true;
	87	}
	88
d457ef35 JL	89	#ifdef CONFIG_SMP
	90	static bool tegra30_cpu_core_power_down(struct cpuidle_device *dev,
	91	struct cpuidle_driver *drv,
	92	int index)
	93	{
	94	clockevents_notify(CLOCK_EVT_NOTIFY_BROADCAST_ENTER, &dev->cpu);
	95
	96	smp_wmb();
	97
d457ef35 JL	98	cpu_suspend(0, tegra30_sleep_cpu_secondary_finish);
d457ef35 JL	99
d457ef35 JL	100	clockevents_notify(CLOCK_EVT_NOTIFY_BROADCAST_EXIT, &dev->cpu);
	101
	102	return true;
	103	}
	104	#else
	105	static inline bool tegra30_cpu_core_power_down(struct cpuidle_device *dev,
	106	struct cpuidle_driver *drv,
	107	int index)
	108	{
	109	return true;
	110	}
	111	#endif
	112
8c627fa6 JL	113	static int tegra30_idle_lp2(struct cpuidle_device *dev,
	114	struct cpuidle_driver *drv,
	115	int index)
d457ef35	116	{
d457ef35	117	bool entered_lp2 = false;
d552920a	118	bool last_cpu;
d457ef35 JL	119
	120	local_fiq_disable();
	121
8f6a0b65	122	last_cpu = tegra_set_cpu_in_lp2();
d457ef35 JL	123	cpu_pm_enter();
d457ef35 JL	124
8f6a0b65	125	if (dev->cpu == 0) {
d552920a JL	126	if (last_cpu)
	127	entered_lp2 = tegra30_cpu_cluster_power_down(dev, drv,
	128	index);
	129	else
	130	cpu_do_idle();
	131	} else {
d457ef35	132	entered_lp2 = tegra30_cpu_core_power_down(dev, drv, index);
d552920a	133	}
d457ef35 JL	134
d457ef35 JL	135	cpu_pm_exit();
8f6a0b65	136	tegra_clear_cpu_in_lp2();
d457ef35 JL	137
	138	local_fiq_enable();
	139
	140	smp_rmb();
	141
	142	return (entered_lp2) ? index : 0;
	143	}
	144	#endif
	145
0b25e25b JL	146	int __init tegra30_cpuidle_init(void)
0b25e25b JL	147	{
f040c26f	148	return cpuidle_register(&tegra_idle_driver, NULL);
0b25e25b	149	}