[deliverable/linux.git] / arch / arm / mach-tegra / flowctrl.c

/*
 * arch/arm/mach-tegra/flowctrl.c
 *
 * functions and macros to control the flowcontroller
 *
 * Copyright (c) 2010-2012, NVIDIA Corporation. All rights reserved.
 *
 * This program is free software; you can redistribute it and/or modify it
 * under the terms and conditions of the GNU General Public License,
 * version 2, as published by the Free Software Foundation.
 *
 * This program is distributed in the hope that it will be useful, but WITHOUT
 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
 * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
 * more details.
 *
 * You should have received a copy of the GNU General Public License
 * along with this program.  If not, see <http://www.gnu.org/licenses/>.
 */

#include <linux/init.h>
#include <linux/kernel.h>
#include <linux/io.h>
#include <linux/cpumask.h>

#include "flowctrl.h"
#include "iomap.h"

u8 flowctrl_offset_halt_cpu[] = {
	FLOW_CTRL_HALT_CPU0_EVENTS,
	FLOW_CTRL_HALT_CPU1_EVENTS,
	FLOW_CTRL_HALT_CPU1_EVENTS + 8,
	FLOW_CTRL_HALT_CPU1_EVENTS + 16,
};

u8 flowctrl_offset_cpu_csr[] = {
	FLOW_CTRL_CPU0_CSR,
	FLOW_CTRL_CPU1_CSR,
	FLOW_CTRL_CPU1_CSR + 8,
	FLOW_CTRL_CPU1_CSR + 16,
};

static void flowctrl_update(u8 offset, u32 value)
{
	void __iomem *addr = IO_ADDRESS(TEGRA_FLOW_CTRL_BASE) + offset;

	writel(value, addr);

	/* ensure the update has reached the flow controller */
	wmb();
	readl_relaxed(addr);
}

u32 flowctrl_read_cpu_csr(unsigned int cpuid)
{
	u8 offset = flowctrl_offset_cpu_csr[cpuid];
	void __iomem *addr = IO_ADDRESS(TEGRA_FLOW_CTRL_BASE) + offset;

	return readl(addr);
}

void flowctrl_write_cpu_csr(unsigned int cpuid, u32 value)
{
	return flowctrl_update(flowctrl_offset_cpu_csr[cpuid], value);
}

void flowctrl_write_cpu_halt(unsigned int cpuid, u32 value)
{
	return flowctrl_update(flowctrl_offset_halt_cpu[cpuid], value);
}

void flowctrl_cpu_suspend_enter(unsigned int cpuid)
{
	unsigned int reg;
	int i;

	reg = flowctrl_read_cpu_csr(cpuid);
	reg &= ~TEGRA30_FLOW_CTRL_CSR_WFE_BITMAP;	/* clear wfe bitmap */
	reg &= ~TEGRA30_FLOW_CTRL_CSR_WFI_BITMAP;	/* clear wfi bitmap */
	reg |= FLOW_CTRL_CSR_INTR_FLAG;			/* clear intr flag */
	reg |= FLOW_CTRL_CSR_EVENT_FLAG;		/* clear event flag */
	reg |= TEGRA30_FLOW_CTRL_CSR_WFI_CPU0 << cpuid;	/* pwr gating on wfi */
	reg |= FLOW_CTRL_CSR_ENABLE;			/* pwr gating */
	flowctrl_write_cpu_csr(cpuid, reg);

	for (i = 0; i < num_possible_cpus(); i++) {
		if (i == cpuid)
			continue;
		reg = flowctrl_read_cpu_csr(i);
		reg |= FLOW_CTRL_CSR_EVENT_FLAG;
		reg |= FLOW_CTRL_CSR_INTR_FLAG;
		flowctrl_write_cpu_csr(i, reg);
	}
}

void flowctrl_cpu_suspend_exit(unsigned int cpuid)
{
	unsigned int reg;

	/* Disable powergating via flow controller for CPU0 */
	reg = flowctrl_read_cpu_csr(cpuid);
	reg &= ~TEGRA30_FLOW_CTRL_CSR_WFE_BITMAP;	/* clear wfe bitmap */
	reg &= ~TEGRA30_FLOW_CTRL_CSR_WFI_BITMAP;	/* clear wfi bitmap */
	reg &= ~FLOW_CTRL_CSR_ENABLE;			/* clear enable */
	reg |= FLOW_CTRL_CSR_INTR_FLAG;			/* clear intr */
	reg |= FLOW_CTRL_CSR_EVENT_FLAG;		/* clear event */
	flowctrl_write_cpu_csr(cpuid, reg);
}
Commit	Line	Data
26fe681f PDS	1	/*
	2	* arch/arm/mach-tegra/flowctrl.c
	3	*
	4	* functions and macros to control the flowcontroller
	5	*
	6	* Copyright (c) 2010-2012, NVIDIA Corporation. All rights reserved.
	7	*
	8	* This program is free software; you can redistribute it and/or modify it
	9	* under the terms and conditions of the GNU General Public License,
	10	* version 2, as published by the Free Software Foundation.
	11	*
	12	* This program is distributed in the hope that it will be useful, but WITHOUT
	13	* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
	14	* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
	15	* more details.
	16	*
	17	* You should have received a copy of the GNU General Public License
	18	* along with this program. If not, see <http://www.gnu.org/licenses/>.
	19	*/
	20
	21	#include <linux/init.h>
	22	#include <linux/kernel.h>
	23	#include <linux/io.h>
01459c69	24	#include <linux/cpumask.h>
26fe681f	25
26fe681f	26	#include "flowctrl.h"
2be39c07	27	#include "iomap.h"
26fe681f PDS	28
	29	u8 flowctrl_offset_halt_cpu[] = {
	30	FLOW_CTRL_HALT_CPU0_EVENTS,
	31	FLOW_CTRL_HALT_CPU1_EVENTS,
	32	FLOW_CTRL_HALT_CPU1_EVENTS + 8,
	33	FLOW_CTRL_HALT_CPU1_EVENTS + 16,
	34	};
	35
	36	u8 flowctrl_offset_cpu_csr[] = {
	37	FLOW_CTRL_CPU0_CSR,
	38	FLOW_CTRL_CPU1_CSR,
	39	FLOW_CTRL_CPU1_CSR + 8,
	40	FLOW_CTRL_CPU1_CSR + 16,
	41	};
	42
	43	static void flowctrl_update(u8 offset, u32 value)
	44	{
	45	void __iomem *addr = IO_ADDRESS(TEGRA_FLOW_CTRL_BASE) + offset;
	46
	47	writel(value, addr);
	48
	49	/* ensure the update has reached the flow controller */
	50	wmb();
	51	readl_relaxed(addr);
	52	}
	53
01459c69 JL	54	u32 flowctrl_read_cpu_csr(unsigned int cpuid)
	55	{
	56	u8 offset = flowctrl_offset_cpu_csr[cpuid];
	57	void __iomem *addr = IO_ADDRESS(TEGRA_FLOW_CTRL_BASE) + offset;
	58
	59	return readl(addr);
	60	}
	61
26fe681f PDS	62	void flowctrl_write_cpu_csr(unsigned int cpuid, u32 value)
26fe681f PDS	63	{
97e7abc5	64	return flowctrl_update(flowctrl_offset_cpu_csr[cpuid], value);
26fe681f PDS	65	}
	66
	67	void flowctrl_write_cpu_halt(unsigned int cpuid, u32 value)
	68	{
97e7abc5	69	return flowctrl_update(flowctrl_offset_halt_cpu[cpuid], value);
26fe681f	70	}
01459c69 JL	71
	72	void flowctrl_cpu_suspend_enter(unsigned int cpuid)
	73	{
	74	unsigned int reg;
	75	int i;
	76
	77	reg = flowctrl_read_cpu_csr(cpuid);
	78	reg &= ~TEGRA30_FLOW_CTRL_CSR_WFE_BITMAP; /* clear wfe bitmap */
	79	reg &= ~TEGRA30_FLOW_CTRL_CSR_WFI_BITMAP; /* clear wfi bitmap */
	80	reg \|= FLOW_CTRL_CSR_INTR_FLAG; /* clear intr flag */
	81	reg \|= FLOW_CTRL_CSR_EVENT_FLAG; /* clear event flag */
	82	reg \|= TEGRA30_FLOW_CTRL_CSR_WFI_CPU0 << cpuid; /* pwr gating on wfi */
	83	reg \|= FLOW_CTRL_CSR_ENABLE; /* pwr gating */
	84	flowctrl_write_cpu_csr(cpuid, reg);
	85
	86	for (i = 0; i < num_possible_cpus(); i++) {
	87	if (i == cpuid)
	88	continue;
	89	reg = flowctrl_read_cpu_csr(i);
	90	reg \|= FLOW_CTRL_CSR_EVENT_FLAG;
	91	reg \|= FLOW_CTRL_CSR_INTR_FLAG;
	92	flowctrl_write_cpu_csr(i, reg);
	93	}
	94	}
	95
	96	void flowctrl_cpu_suspend_exit(unsigned int cpuid)
	97	{
	98	unsigned int reg;
	99
	100	/* Disable powergating via flow controller for CPU0 */
	101	reg = flowctrl_read_cpu_csr(cpuid);
	102	reg &= ~TEGRA30_FLOW_CTRL_CSR_WFE_BITMAP; /* clear wfe bitmap */
	103	reg &= ~TEGRA30_FLOW_CTRL_CSR_WFI_BITMAP; /* clear wfi bitmap */
	104	reg &= ~FLOW_CTRL_CSR_ENABLE; /* clear enable */
	105	reg \|= FLOW_CTRL_CSR_INTR_FLAG; /* clear intr */
	106	reg \|= FLOW_CTRL_CSR_EVENT_FLAG; /* clear event */
	107	flowctrl_write_cpu_csr(cpuid, reg);
	108	}