[deliverable/linux.git] / arch / arm / mach-tegra / flowctrl.c

/*
 * arch/arm/mach-tegra/flowctrl.c
 *
 * functions and macros to control the flowcontroller
 *
 * Copyright (c) 2010-2012, NVIDIA Corporation. All rights reserved.
 *
 * This program is free software; you can redistribute it and/or modify it
 * under the terms and conditions of the GNU General Public License,
 * version 2, as published by the Free Software Foundation.
 *
 * This program is distributed in the hope that it will be useful, but WITHOUT
 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
 * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
 * more details.
 *
 * You should have received a copy of the GNU General Public License
 * along with this program.  If not, see <http://www.gnu.org/licenses/>.
 */

#include <linux/init.h>
#include <linux/kernel.h>
#include <linux/io.h>
#include <linux/cpumask.h>

#include "flowctrl.h"
#include "iomap.h"
#include "fuse.h"

static u8 flowctrl_offset_halt_cpu[] = {
	FLOW_CTRL_HALT_CPU0_EVENTS,
	FLOW_CTRL_HALT_CPU1_EVENTS,
	FLOW_CTRL_HALT_CPU1_EVENTS + 8,
	FLOW_CTRL_HALT_CPU1_EVENTS + 16,
};

static u8 flowctrl_offset_cpu_csr[] = {
	FLOW_CTRL_CPU0_CSR,
	FLOW_CTRL_CPU1_CSR,
	FLOW_CTRL_CPU1_CSR + 8,
	FLOW_CTRL_CPU1_CSR + 16,
};

static void flowctrl_update(u8 offset, u32 value)
{
	void __iomem *addr = IO_ADDRESS(TEGRA_FLOW_CTRL_BASE) + offset;

	writel(value, addr);

	/* ensure the update has reached the flow controller */
	wmb();
	readl_relaxed(addr);
}

u32 flowctrl_read_cpu_csr(unsigned int cpuid)
{
	u8 offset = flowctrl_offset_cpu_csr[cpuid];
	void __iomem *addr = IO_ADDRESS(TEGRA_FLOW_CTRL_BASE) + offset;

	return readl(addr);
}

void flowctrl_write_cpu_csr(unsigned int cpuid, u32 value)
{
	return flowctrl_update(flowctrl_offset_cpu_csr[cpuid], value);
}

void flowctrl_write_cpu_halt(unsigned int cpuid, u32 value)
{
	return flowctrl_update(flowctrl_offset_halt_cpu[cpuid], value);
}

void flowctrl_cpu_suspend_enter(unsigned int cpuid)
{
	unsigned int reg;
	int i;

	reg = flowctrl_read_cpu_csr(cpuid);
	switch (tegra_chip_id) {
	case TEGRA20:
		/* clear wfe bitmap */
		reg &= ~TEGRA20_FLOW_CTRL_CSR_WFE_BITMAP;
		/* clear wfi bitmap */
		reg &= ~TEGRA20_FLOW_CTRL_CSR_WFI_BITMAP;
		/* pwr gating on wfe */
		reg |= TEGRA20_FLOW_CTRL_CSR_WFE_CPU0 << cpuid;
		break;
	case TEGRA30:
	case TEGRA114:
	case TEGRA124:
		/* clear wfe bitmap */
		reg &= ~TEGRA30_FLOW_CTRL_CSR_WFE_BITMAP;
		/* clear wfi bitmap */
		reg &= ~TEGRA30_FLOW_CTRL_CSR_WFI_BITMAP;
		/* pwr gating on wfi */
		reg |= TEGRA30_FLOW_CTRL_CSR_WFI_CPU0 << cpuid;
		break;
	}
	reg |= FLOW_CTRL_CSR_INTR_FLAG;			/* clear intr flag */
	reg |= FLOW_CTRL_CSR_EVENT_FLAG;		/* clear event flag */
	reg |= FLOW_CTRL_CSR_ENABLE;			/* pwr gating */
	flowctrl_write_cpu_csr(cpuid, reg);

	for (i = 0; i < num_possible_cpus(); i++) {
		if (i == cpuid)
			continue;
		reg = flowctrl_read_cpu_csr(i);
		reg |= FLOW_CTRL_CSR_EVENT_FLAG;
		reg |= FLOW_CTRL_CSR_INTR_FLAG;
		flowctrl_write_cpu_csr(i, reg);
	}
}

void flowctrl_cpu_suspend_exit(unsigned int cpuid)
{
	unsigned int reg;

	/* Disable powergating via flow controller for CPU0 */
	reg = flowctrl_read_cpu_csr(cpuid);
	switch (tegra_chip_id) {
	case TEGRA20:
		/* clear wfe bitmap */
		reg &= ~TEGRA20_FLOW_CTRL_CSR_WFE_BITMAP;
		/* clear wfi bitmap */
		reg &= ~TEGRA20_FLOW_CTRL_CSR_WFI_BITMAP;
		break;
	case TEGRA30:
	case TEGRA114:
	case TEGRA124:
		/* clear wfe bitmap */
		reg &= ~TEGRA30_FLOW_CTRL_CSR_WFE_BITMAP;
		/* clear wfi bitmap */
		reg &= ~TEGRA30_FLOW_CTRL_CSR_WFI_BITMAP;
		break;
	}
	reg &= ~FLOW_CTRL_CSR_ENABLE;			/* clear enable */
	reg |= FLOW_CTRL_CSR_INTR_FLAG;			/* clear intr */
	reg |= FLOW_CTRL_CSR_EVENT_FLAG;		/* clear event */
	flowctrl_write_cpu_csr(cpuid, reg);
}
Commit	Line	Data
26fe681f PDS	1	/*
	2	* arch/arm/mach-tegra/flowctrl.c
	3	*
	4	* functions and macros to control the flowcontroller
	5	*
	6	* Copyright (c) 2010-2012, NVIDIA Corporation. All rights reserved.
	7	*
	8	* This program is free software; you can redistribute it and/or modify it
	9	* under the terms and conditions of the GNU General Public License,
	10	* version 2, as published by the Free Software Foundation.
	11	*
	12	* This program is distributed in the hope that it will be useful, but WITHOUT
	13	* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
	14	* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
	15	* more details.
	16	*
	17	* You should have received a copy of the GNU General Public License
	18	* along with this program. If not, see <http://www.gnu.org/licenses/>.
	19	*/
	20
	21	#include <linux/init.h>
	22	#include <linux/kernel.h>
	23	#include <linux/io.h>
01459c69	24	#include <linux/cpumask.h>
26fe681f	25
26fe681f	26	#include "flowctrl.h"
2be39c07	27	#include "iomap.h"
afec581c	28	#include "fuse.h"
26fe681f	29
deeb8d19	30	static u8 flowctrl_offset_halt_cpu[] = {
26fe681f PDS	31	FLOW_CTRL_HALT_CPU0_EVENTS,
	32	FLOW_CTRL_HALT_CPU1_EVENTS,
	33	FLOW_CTRL_HALT_CPU1_EVENTS + 8,
	34	FLOW_CTRL_HALT_CPU1_EVENTS + 16,
	35	};
	36
deeb8d19	37	static u8 flowctrl_offset_cpu_csr[] = {
26fe681f PDS	38	FLOW_CTRL_CPU0_CSR,
	39	FLOW_CTRL_CPU1_CSR,
	40	FLOW_CTRL_CPU1_CSR + 8,
	41	FLOW_CTRL_CPU1_CSR + 16,
	42	};
	43
	44	static void flowctrl_update(u8 offset, u32 value)
	45	{
	46	void __iomem *addr = IO_ADDRESS(TEGRA_FLOW_CTRL_BASE) + offset;
	47
	48	writel(value, addr);
	49
	50	/* ensure the update has reached the flow controller */
	51	wmb();
	52	readl_relaxed(addr);
	53	}
	54
01459c69 JL	55	u32 flowctrl_read_cpu_csr(unsigned int cpuid)
	56	{
	57	u8 offset = flowctrl_offset_cpu_csr[cpuid];
	58	void __iomem *addr = IO_ADDRESS(TEGRA_FLOW_CTRL_BASE) + offset;
	59
	60	return readl(addr);
	61	}
	62
26fe681f PDS	63	void flowctrl_write_cpu_csr(unsigned int cpuid, u32 value)
26fe681f PDS	64	{
97e7abc5	65	return flowctrl_update(flowctrl_offset_cpu_csr[cpuid], value);
26fe681f PDS	66	}
	67
	68	void flowctrl_write_cpu_halt(unsigned int cpuid, u32 value)
	69	{
97e7abc5	70	return flowctrl_update(flowctrl_offset_halt_cpu[cpuid], value);
26fe681f	71	}
01459c69 JL	72
	73	void flowctrl_cpu_suspend_enter(unsigned int cpuid)
	74	{
	75	unsigned int reg;
	76	int i;
	77
	78	reg = flowctrl_read_cpu_csr(cpuid);
afec581c JL	79	switch (tegra_chip_id) {
	80	case TEGRA20:
	81	/* clear wfe bitmap */
	82	reg &= ~TEGRA20_FLOW_CTRL_CSR_WFE_BITMAP;
	83	/* clear wfi bitmap */
	84	reg &= ~TEGRA20_FLOW_CTRL_CSR_WFI_BITMAP;
	85	/* pwr gating on wfe */
	86	reg \|= TEGRA20_FLOW_CTRL_CSR_WFE_CPU0 << cpuid;
	87	break;
	88	case TEGRA30:
dd6fe9a9	89	case TEGRA114:
f0c4ac13	90	case TEGRA124:
afec581c JL	91	/* clear wfe bitmap */
	92	reg &= ~TEGRA30_FLOW_CTRL_CSR_WFE_BITMAP;
	93	/* clear wfi bitmap */
	94	reg &= ~TEGRA30_FLOW_CTRL_CSR_WFI_BITMAP;
	95	/* pwr gating on wfi */
	96	reg \|= TEGRA30_FLOW_CTRL_CSR_WFI_CPU0 << cpuid;
	97	break;
	98	}
01459c69 JL	99	reg \|= FLOW_CTRL_CSR_INTR_FLAG; /* clear intr flag */
01459c69 JL	100	reg \|= FLOW_CTRL_CSR_EVENT_FLAG; /* clear event flag */
01459c69 JL	101	reg \|= FLOW_CTRL_CSR_ENABLE; /* pwr gating */
	102	flowctrl_write_cpu_csr(cpuid, reg);
	103
	104	for (i = 0; i < num_possible_cpus(); i++) {
	105	if (i == cpuid)
	106	continue;
	107	reg = flowctrl_read_cpu_csr(i);
	108	reg \|= FLOW_CTRL_CSR_EVENT_FLAG;
	109	reg \|= FLOW_CTRL_CSR_INTR_FLAG;
	110	flowctrl_write_cpu_csr(i, reg);
	111	}
	112	}
	113
	114	void flowctrl_cpu_suspend_exit(unsigned int cpuid)
	115	{
	116	unsigned int reg;
	117
	118	/* Disable powergating via flow controller for CPU0 */
	119	reg = flowctrl_read_cpu_csr(cpuid);
afec581c JL	120	switch (tegra_chip_id) {
	121	case TEGRA20:
	122	/* clear wfe bitmap */
	123	reg &= ~TEGRA20_FLOW_CTRL_CSR_WFE_BITMAP;
	124	/* clear wfi bitmap */
	125	reg &= ~TEGRA20_FLOW_CTRL_CSR_WFI_BITMAP;
	126	break;
	127	case TEGRA30:
dd6fe9a9	128	case TEGRA114:
f0c4ac13	129	case TEGRA124:
afec581c JL	130	/* clear wfe bitmap */
	131	reg &= ~TEGRA30_FLOW_CTRL_CSR_WFE_BITMAP;
	132	/* clear wfi bitmap */
	133	reg &= ~TEGRA30_FLOW_CTRL_CSR_WFI_BITMAP;
	134	break;
	135	}
01459c69 JL	136	reg &= ~FLOW_CTRL_CSR_ENABLE; /* clear enable */
	137	reg \|= FLOW_CTRL_CSR_INTR_FLAG; /* clear intr */
	138	reg \|= FLOW_CTRL_CSR_EVENT_FLAG; /* clear event */
	139	flowctrl_write_cpu_csr(cpuid, reg);
	140	}