[deliverable/linux.git] / arch / arm / mach-tegra / fuse.c

/*
 * arch/arm/mach-tegra/fuse.c
 *
 * Copyright (C) 2010 Google, Inc.
 *
 * Author:
 *	Colin Cross <ccross@android.com>
 *
 * This software is licensed under the terms of the GNU General Public
 * License version 2, as published by the Free Software Foundation, and
 * may be copied, distributed, and modified under those terms.
 *
 * This program is distributed in the hope that it will be useful,
 * but WITHOUT ANY WARRANTY; without even the implied warranty of
 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
 * GNU General Public License for more details.
 *
 */

#include <linux/kernel.h>
#include <linux/io.h>
#include <linux/export.h>

#include <mach/iomap.h>

#include "fuse.h"
#include "apbio.h"

#define FUSE_UID_LOW		0x108
#define FUSE_UID_HIGH		0x10c
#define FUSE_SKU_INFO		0x110
#define FUSE_SPARE_BIT		0x200

int tegra_sku_id;
int tegra_cpu_process_id;
int tegra_core_process_id;
int tegra_chip_id;
enum tegra_revision tegra_revision;

/* The BCT to use at boot is specified by board straps that can be read
 * through a APB misc register and decoded. 2 bits, i.e. 4 possible BCTs.
 */
int tegra_bct_strapping;

#define STRAP_OPT 0x008
#define GMI_AD0 (1 << 4)
#define GMI_AD1 (1 << 5)
#define RAM_ID_MASK (GMI_AD0 | GMI_AD1)
#define RAM_CODE_SHIFT 4

static const char *tegra_revision_name[TEGRA_REVISION_MAX] = {
	[TEGRA_REVISION_UNKNOWN] = "unknown",
	[TEGRA_REVISION_A01]     = "A01",
	[TEGRA_REVISION_A02]     = "A02",
	[TEGRA_REVISION_A03]     = "A03",
	[TEGRA_REVISION_A03p]    = "A03 prime",
	[TEGRA_REVISION_A04]     = "A04",
};

static inline u32 tegra_fuse_readl(unsigned long offset)
{
	return tegra_apb_readl(TEGRA_FUSE_BASE + offset);
}

static inline bool get_spare_fuse(int bit)
{
	return tegra_fuse_readl(FUSE_SPARE_BIT + bit * 4);
}

static enum tegra_revision tegra_get_revision(u32 id)
{
	u32 minor_rev = (id >> 16) & 0xf;

	switch (minor_rev) {
	case 1:
		return TEGRA_REVISION_A01;
	case 2:
		return TEGRA_REVISION_A02;
	case 3:
		if (tegra_chip_id == TEGRA20 &&
			(get_spare_fuse(18) || get_spare_fuse(19)))
			return TEGRA_REVISION_A03p;
		else
			return TEGRA_REVISION_A03;
	case 4:
		return TEGRA_REVISION_A04;
	default:
		return TEGRA_REVISION_UNKNOWN;
	}
}

void tegra_init_fuse(void)
{
	u32 id;

	u32 reg = readl(IO_ADDRESS(TEGRA_CLK_RESET_BASE + 0x48));
	reg |= 1 << 28;
	writel(reg, IO_ADDRESS(TEGRA_CLK_RESET_BASE + 0x48));

	reg = tegra_fuse_readl(FUSE_SKU_INFO);
	tegra_sku_id = reg & 0xFF;

	reg = tegra_fuse_readl(FUSE_SPARE_BIT);
	tegra_cpu_process_id = (reg >> 6) & 3;

	reg = tegra_fuse_readl(FUSE_SPARE_BIT);
	tegra_core_process_id = (reg >> 12) & 3;

	reg = tegra_apb_readl(TEGRA_APB_MISC_BASE + STRAP_OPT);
	tegra_bct_strapping = (reg & RAM_ID_MASK) >> RAM_CODE_SHIFT;

	id = readl_relaxed(IO_ADDRESS(TEGRA_APB_MISC_BASE) + 0x804);
	tegra_chip_id = (id >> 8) & 0xff;

	tegra_revision = tegra_get_revision(id);

	pr_info("Tegra Revision: %s SKU: %d CPU Process: %d Core Process: %d\n",
		tegra_revision_name[tegra_revision],
		tegra_sku_id, tegra_cpu_process_id,
		tegra_core_process_id);
}

unsigned long long tegra_chip_uid(void)
{
	unsigned long long lo, hi;

	lo = tegra_fuse_readl(FUSE_UID_LOW);
	hi = tegra_fuse_readl(FUSE_UID_HIGH);
	return (hi << 32ull) | lo;
}
EXPORT_SYMBOL(tegra_chip_uid);
Commit	Line	Data
73625e3e CC	1	/*
	2	* arch/arm/mach-tegra/fuse.c
	3	*
	4	* Copyright (C) 2010 Google, Inc.
	5	*
	6	* Author:
	7	* Colin Cross <ccross@android.com>
	8	*
	9	* This software is licensed under the terms of the GNU General Public
	10	* License version 2, as published by the Free Software Foundation, and
	11	* may be copied, distributed, and modified under those terms.
	12	*
	13	* This program is distributed in the hope that it will be useful,
	14	* but WITHOUT ANY WARRANTY; without even the implied warranty of
	15	* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
	16	* GNU General Public License for more details.
	17	*
	18	*/
	19
	20	#include <linux/kernel.h>
	21	#include <linux/io.h>
34800598	22	#include <linux/export.h>
73625e3e CC	23
	24	#include <mach/iomap.h>
	25
	26	#include "fuse.h"
d262f49d	27	#include "apbio.h"
73625e3e CC	28
	29	#define FUSE_UID_LOW 0x108
	30	#define FUSE_UID_HIGH 0x10c
	31	#define FUSE_SKU_INFO 0x110
	32	#define FUSE_SPARE_BIT 0x200
	33
9a1086da OJ	34	int tegra_sku_id;
	35	int tegra_cpu_process_id;
	36	int tegra_core_process_id;
4c4ad669	37	int tegra_chip_id;
9a1086da OJ	38	enum tegra_revision tegra_revision;
9a1086da OJ	39
dee47183 OJ	40	/* The BCT to use at boot is specified by board straps that can be read
	41	* through a APB misc register and decoded. 2 bits, i.e. 4 possible BCTs.
	42	*/
	43	int tegra_bct_strapping;
	44
	45	#define STRAP_OPT 0x008
	46	#define GMI_AD0 (1 << 4)
	47	#define GMI_AD1 (1 << 5)
	48	#define RAM_ID_MASK (GMI_AD0 \| GMI_AD1)
	49	#define RAM_CODE_SHIFT 4
	50
9a1086da OJ	51	static const char *tegra_revision_name[TEGRA_REVISION_MAX] = {
	52	[TEGRA_REVISION_UNKNOWN] = "unknown",
	53	[TEGRA_REVISION_A01] = "A01",
	54	[TEGRA_REVISION_A02] = "A02",
	55	[TEGRA_REVISION_A03] = "A03",
	56	[TEGRA_REVISION_A03p] = "A03 prime",
	57	[TEGRA_REVISION_A04] = "A04",
	58	};
	59
d262f49d	60	static inline u32 tegra_fuse_readl(unsigned long offset)
73625e3e	61	{
d262f49d	62	return tegra_apb_readl(TEGRA_FUSE_BASE + offset);
73625e3e CC	63	}
73625e3e CC	64
9a1086da	65	static inline bool get_spare_fuse(int bit)
73625e3e	66	{
9a1086da	67	return tegra_fuse_readl(FUSE_SPARE_BIT + bit * 4);
73625e3e CC	68	}
73625e3e CC	69
35b1498a	70	static enum tegra_revision tegra_get_revision(u32 id)
73625e3e	71	{
9a1086da	72	u32 minor_rev = (id >> 16) & 0xf;
9a1086da OJ	73
	74	switch (minor_rev) {
	75	case 1:
	76	return TEGRA_REVISION_A01;
	77	case 2:
	78	return TEGRA_REVISION_A02;
	79	case 3:
35b1498a PDS	80	if (tegra_chip_id == TEGRA20 &&
35b1498a PDS	81	(get_spare_fuse(18) \|\| get_spare_fuse(19)))
9a1086da OJ	82	return TEGRA_REVISION_A03p;
	83	else
	84	return TEGRA_REVISION_A03;
	85	case 4:
	86	return TEGRA_REVISION_A04;
	87	default:
	88	return TEGRA_REVISION_UNKNOWN;
	89	}
73625e3e CC	90	}
	91
	92	void tegra_init_fuse(void)
	93	{
35b1498a PDS	94	u32 id;
35b1498a PDS	95
f8e798a9	96	u32 reg = readl(IO_ADDRESS(TEGRA_CLK_RESET_BASE + 0x48));
73625e3e	97	reg \|= 1 << 28;
f8e798a9	98	writel(reg, IO_ADDRESS(TEGRA_CLK_RESET_BASE + 0x48));
73625e3e	99
9a1086da OJ	100	reg = tegra_fuse_readl(FUSE_SKU_INFO);
	101	tegra_sku_id = reg & 0xFF;
	102
	103	reg = tegra_fuse_readl(FUSE_SPARE_BIT);
	104	tegra_cpu_process_id = (reg >> 6) & 3;
	105
	106	reg = tegra_fuse_readl(FUSE_SPARE_BIT);
	107	tegra_core_process_id = (reg >> 12) & 3;
	108
dee47183 OJ	109	reg = tegra_apb_readl(TEGRA_APB_MISC_BASE + STRAP_OPT);
	110	tegra_bct_strapping = (reg & RAM_ID_MASK) >> RAM_CODE_SHIFT;
	111
35b1498a PDS	112	id = readl_relaxed(IO_ADDRESS(TEGRA_APB_MISC_BASE) + 0x804);
	113	tegra_chip_id = (id >> 8) & 0xff;
	114
	115	tegra_revision = tegra_get_revision(id);
9a1086da OJ	116
9a1086da OJ	117	pr_info("Tegra Revision: %s SKU: %d CPU Process: %d Core Process: %d\n",
35b1498a	118	tegra_revision_name[tegra_revision],
9a1086da OJ	119	tegra_sku_id, tegra_cpu_process_id,
9a1086da OJ	120	tegra_core_process_id);
73625e3e CC	121	}
	122
	123	unsigned long long tegra_chip_uid(void)
	124	{
	125	unsigned long long lo, hi;
	126
d262f49d OJ	127	lo = tegra_fuse_readl(FUSE_UID_LOW);
d262f49d OJ	128	hi = tegra_fuse_readl(FUSE_UID_HIGH);
73625e3e CC	129	return (hi << 32ull) \| lo;
73625e3e CC	130	}
e87e06cd	131	EXPORT_SYMBOL(tegra_chip_uid);