[deliverable/linux.git] / arch / arm / mach-tegra / fuse.c

/*
 * arch/arm/mach-tegra/fuse.c
 *
 * Copyright (C) 2010 Google, Inc.
 * Copyright (c) 2013, NVIDIA CORPORATION.  All rights reserved.
 *
 * Author:
 *	Colin Cross <ccross@android.com>
 *
 * This software is licensed under the terms of the GNU General Public
 * License version 2, as published by the Free Software Foundation, and
 * may be copied, distributed, and modified under those terms.
 *
 * This program is distributed in the hope that it will be useful,
 * but WITHOUT ANY WARRANTY; without even the implied warranty of
 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
 * GNU General Public License for more details.
 *
 */

#include <linux/kernel.h>
#include <linux/io.h>
#include <linux/export.h>
#include <linux/random.h>
#include <linux/clk.h>
#include <linux/tegra-soc.h>

#include "fuse.h"
#include "iomap.h"
#include "apbio.h"

/* Tegra20 only */
#define FUSE_UID_LOW		0x108
#define FUSE_UID_HIGH		0x10c

/* Tegra30 and later */
#define FUSE_VENDOR_CODE	0x200
#define FUSE_FAB_CODE		0x204
#define FUSE_LOT_CODE_0		0x208
#define FUSE_LOT_CODE_1		0x20c
#define FUSE_WAFER_ID		0x210
#define FUSE_X_COORDINATE	0x214
#define FUSE_Y_COORDINATE	0x218

#define FUSE_SKU_INFO		0x110

#define TEGRA20_FUSE_SPARE_BIT		0x200
#define TEGRA30_FUSE_SPARE_BIT		0x244

int tegra_sku_id;
int tegra_cpu_process_id;
int tegra_core_process_id;
int tegra_chip_id;
int tegra_cpu_speedo_id;		/* only exist in Tegra30 and later */
int tegra_soc_speedo_id;
enum tegra_revision tegra_revision;

static struct clk *fuse_clk;
static int tegra_fuse_spare_bit;
static void (*tegra_init_speedo_data)(void);

/* The BCT to use at boot is specified by board straps that can be read
 * through a APB misc register and decoded. 2 bits, i.e. 4 possible BCTs.
 */
int tegra_bct_strapping;

#define STRAP_OPT 0x008
#define GMI_AD0 (1 << 4)
#define GMI_AD1 (1 << 5)
#define RAM_ID_MASK (GMI_AD0 | GMI_AD1)
#define RAM_CODE_SHIFT 4

static const char *tegra_revision_name[TEGRA_REVISION_MAX] = {
	[TEGRA_REVISION_UNKNOWN] = "unknown",
	[TEGRA_REVISION_A01]     = "A01",
	[TEGRA_REVISION_A02]     = "A02",
	[TEGRA_REVISION_A03]     = "A03",
	[TEGRA_REVISION_A03p]    = "A03 prime",
	[TEGRA_REVISION_A04]     = "A04",
};

static void tegra_fuse_enable_clk(void)
{
	if (IS_ERR(fuse_clk))
		fuse_clk = clk_get_sys(NULL, "fuse");
	if (IS_ERR(fuse_clk))
		return;
	clk_prepare_enable(fuse_clk);
}

static void tegra_fuse_disable_clk(void)
{
	if (IS_ERR(fuse_clk))
		return;
	clk_disable_unprepare(fuse_clk);
}

u32 tegra_fuse_readl(unsigned long offset)
{
	return tegra_apb_readl(TEGRA_FUSE_BASE + offset);
}

bool tegra_spare_fuse(int bit)
{
	bool ret;

	tegra_fuse_enable_clk();

	ret = tegra_fuse_readl(tegra_fuse_spare_bit + bit * 4);

	tegra_fuse_disable_clk();

	return ret;
}

static enum tegra_revision tegra_get_revision(u32 id)
{
	u32 minor_rev = (id >> 16) & 0xf;

	switch (minor_rev) {
	case 1:
		return TEGRA_REVISION_A01;
	case 2:
		return TEGRA_REVISION_A02;
	case 3:
		if (tegra_chip_id == TEGRA20 &&
			(tegra_spare_fuse(18) || tegra_spare_fuse(19)))
			return TEGRA_REVISION_A03p;
		else
			return TEGRA_REVISION_A03;
	case 4:
		return TEGRA_REVISION_A04;
	default:
		return TEGRA_REVISION_UNKNOWN;
	}
}

static void tegra_get_process_id(void)
{
	u32 reg;

	tegra_fuse_enable_clk();

	reg = tegra_fuse_readl(tegra_fuse_spare_bit);
	tegra_cpu_process_id = (reg >> 6) & 3;
	reg = tegra_fuse_readl(tegra_fuse_spare_bit);
	tegra_core_process_id = (reg >> 12) & 3;

	tegra_fuse_disable_clk();
}

u32 tegra_read_chipid(void)
{
	return readl_relaxed(IO_ADDRESS(TEGRA_APB_MISC_BASE) + 0x804);
}

static void __init tegra20_fuse_init_randomness(void)
{
	u32 randomness[2];

	randomness[0] = tegra_fuse_readl(FUSE_UID_LOW);
	randomness[1] = tegra_fuse_readl(FUSE_UID_HIGH);

	add_device_randomness(randomness, sizeof(randomness));
}

/* Applies to Tegra30 or later */
static void __init tegra30_fuse_init_randomness(void)
{
	u32 randomness[7];

	randomness[0] = tegra_fuse_readl(FUSE_VENDOR_CODE);
	randomness[1] = tegra_fuse_readl(FUSE_FAB_CODE);
	randomness[2] = tegra_fuse_readl(FUSE_LOT_CODE_0);
	randomness[3] = tegra_fuse_readl(FUSE_LOT_CODE_1);
	randomness[4] = tegra_fuse_readl(FUSE_WAFER_ID);
	randomness[5] = tegra_fuse_readl(FUSE_X_COORDINATE);
	randomness[6] = tegra_fuse_readl(FUSE_Y_COORDINATE);

	add_device_randomness(randomness, sizeof(randomness));
}

void __init tegra_init_fuse(void)
{
	u32 id;
	u32 randomness[5];

	u32 reg = readl(IO_ADDRESS(TEGRA_CLK_RESET_BASE + 0x48));
	reg |= 1 << 28;
	writel(reg, IO_ADDRESS(TEGRA_CLK_RESET_BASE + 0x48));

	/*
	 * Enable FUSE clock. This needs to be hardcoded because the clock
	 * subsystem is not active during early boot.
	 */
	reg = readl(IO_ADDRESS(TEGRA_CLK_RESET_BASE + 0x14));
	reg |= 1 << 7;
	writel(reg, IO_ADDRESS(TEGRA_CLK_RESET_BASE + 0x14));
	fuse_clk = ERR_PTR(-EINVAL);

	reg = tegra_fuse_readl(FUSE_SKU_INFO);
	randomness[0] = reg;
	tegra_sku_id = reg & 0xFF;

	reg = tegra_apb_readl(TEGRA_APB_MISC_BASE + STRAP_OPT);
	randomness[1] = reg;
	tegra_bct_strapping = (reg & RAM_ID_MASK) >> RAM_CODE_SHIFT;

	id = tegra_read_chipid();
	randomness[2] = id;
	tegra_chip_id = (id >> 8) & 0xff;

	switch (tegra_chip_id) {
	case TEGRA20:
		tegra_fuse_spare_bit = TEGRA20_FUSE_SPARE_BIT;
		tegra_init_speedo_data = &tegra20_init_speedo_data;
		break;
	case TEGRA30:
		tegra_fuse_spare_bit = TEGRA30_FUSE_SPARE_BIT;
		tegra_init_speedo_data = &tegra30_init_speedo_data;
		break;
	case TEGRA114:
		tegra_init_speedo_data = &tegra114_init_speedo_data;
		break;
	default:
		pr_warn("Tegra: unknown chip id %d\n", tegra_chip_id);
		tegra_fuse_spare_bit = TEGRA20_FUSE_SPARE_BIT;
		tegra_init_speedo_data = &tegra_get_process_id;
	}

	tegra_revision = tegra_get_revision(id);
	tegra_init_speedo_data();
	randomness[3] = (tegra_cpu_process_id << 16) | tegra_core_process_id;
	randomness[4] = (tegra_cpu_speedo_id << 16) | tegra_soc_speedo_id;

	add_device_randomness(randomness, sizeof(randomness));
	switch (tegra_chip_id) {
	case TEGRA20:
		tegra20_fuse_init_randomness();
		break;
	case TEGRA30:
	case TEGRA114:
	default:
		tegra30_fuse_init_randomness();
		break;
	}

	pr_info("Tegra Revision: %s SKU: %d CPU Process: %d Core Process: %d\n",
		tegra_revision_name[tegra_revision],
		tegra_sku_id, tegra_cpu_process_id,
		tegra_core_process_id);
}
Commit	Line	Data
73625e3e CC	1	/*
	2	* arch/arm/mach-tegra/fuse.c
	3	*
	4	* Copyright (C) 2010 Google, Inc.
7495b2eb	5	* Copyright (c) 2013, NVIDIA CORPORATION. All rights reserved.
73625e3e CC	6	*
	7	* Author:
	8	* Colin Cross <ccross@android.com>
	9	*
	10	* This software is licensed under the terms of the GNU General Public
	11	* License version 2, as published by the Free Software Foundation, and
	12	* may be copied, distributed, and modified under those terms.
	13	*
	14	* This program is distributed in the hope that it will be useful,
	15	* but WITHOUT ANY WARRANTY; without even the implied warranty of
	16	* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
	17	* GNU General Public License for more details.
	18	*
	19	*/
	20
	21	#include <linux/kernel.h>
	22	#include <linux/io.h>
34800598	23	#include <linux/export.h>
3bd1ae57	24	#include <linux/random.h>
cdcb5a07	25	#include <linux/clk.h>
c7736edf	26	#include <linux/tegra-soc.h>
73625e3e	27
73625e3e	28	#include "fuse.h"
2be39c07	29	#include "iomap.h"
d262f49d	30	#include "apbio.h"
73625e3e	31
3bd1ae57	32	/* Tegra20 only */
73625e3e CC	33	#define FUSE_UID_LOW 0x108
73625e3e CC	34	#define FUSE_UID_HIGH 0x10c
3bd1ae57 SW	35
	36	/* Tegra30 and later */
	37	#define FUSE_VENDOR_CODE 0x200
	38	#define FUSE_FAB_CODE 0x204
	39	#define FUSE_LOT_CODE_0 0x208
	40	#define FUSE_LOT_CODE_1 0x20c
	41	#define FUSE_WAFER_ID 0x210
	42	#define FUSE_X_COORDINATE 0x214
	43	#define FUSE_Y_COORDINATE 0x218
	44
73625e3e	45	#define FUSE_SKU_INFO 0x110
1f851a26 DH	46
1f851a26 DH	47	#define TEGRA20_FUSE_SPARE_BIT 0x200
f8ddda71	48	#define TEGRA30_FUSE_SPARE_BIT 0x244
73625e3e	49
9a1086da OJ	50	int tegra_sku_id;
	51	int tegra_cpu_process_id;
	52	int tegra_core_process_id;
4c4ad669	53	int tegra_chip_id;
f8ddda71	54	int tegra_cpu_speedo_id; /* only exist in Tegra30 and later */
25cd5a39	55	int tegra_soc_speedo_id;
9a1086da OJ	56	enum tegra_revision tegra_revision;
9a1086da OJ	57
cdcb5a07	58	static struct clk *fuse_clk;
1f851a26	59	static int tegra_fuse_spare_bit;
25cd5a39	60	static void (*tegra_init_speedo_data)(void);
1f851a26	61
dee47183 OJ	62	/* The BCT to use at boot is specified by board straps that can be read
	63	* through a APB misc register and decoded. 2 bits, i.e. 4 possible BCTs.
	64	*/
	65	int tegra_bct_strapping;
	66
	67	#define STRAP_OPT 0x008
	68	#define GMI_AD0 (1 << 4)
	69	#define GMI_AD1 (1 << 5)
	70	#define RAM_ID_MASK (GMI_AD0 \| GMI_AD1)
	71	#define RAM_CODE_SHIFT 4
	72
9a1086da OJ	73	static const char *tegra_revision_name[TEGRA_REVISION_MAX] = {
	74	[TEGRA_REVISION_UNKNOWN] = "unknown",
	75	[TEGRA_REVISION_A01] = "A01",
	76	[TEGRA_REVISION_A02] = "A02",
	77	[TEGRA_REVISION_A03] = "A03",
	78	[TEGRA_REVISION_A03p] = "A03 prime",
	79	[TEGRA_REVISION_A04] = "A04",
	80	};
	81
cdcb5a07 AC	82	static void tegra_fuse_enable_clk(void)
	83	{
	84	if (IS_ERR(fuse_clk))
	85	fuse_clk = clk_get_sys(NULL, "fuse");
	86	if (IS_ERR(fuse_clk))
	87	return;
	88	clk_prepare_enable(fuse_clk);
	89	}
	90
	91	static void tegra_fuse_disable_clk(void)
	92	{
	93	if (IS_ERR(fuse_clk))
	94	return;
	95	clk_disable_unprepare(fuse_clk);
	96	}
	97
1f851a26	98	u32 tegra_fuse_readl(unsigned long offset)
73625e3e	99	{
d262f49d	100	return tegra_apb_readl(TEGRA_FUSE_BASE + offset);
73625e3e CC	101	}
73625e3e CC	102
1f851a26	103	bool tegra_spare_fuse(int bit)
73625e3e	104	{
cdcb5a07 AC	105	bool ret;
	106
	107	tegra_fuse_enable_clk();
	108
	109	ret = tegra_fuse_readl(tegra_fuse_spare_bit + bit * 4);
	110
	111	tegra_fuse_disable_clk();
	112
	113	return ret;
73625e3e CC	114	}
73625e3e CC	115
35b1498a	116	static enum tegra_revision tegra_get_revision(u32 id)
73625e3e	117	{
9a1086da	118	u32 minor_rev = (id >> 16) & 0xf;
9a1086da OJ	119
	120	switch (minor_rev) {
	121	case 1:
	122	return TEGRA_REVISION_A01;
	123	case 2:
	124	return TEGRA_REVISION_A02;
	125	case 3:
35b1498a	126	if (tegra_chip_id == TEGRA20 &&
1f851a26	127	(tegra_spare_fuse(18) \|\| tegra_spare_fuse(19)))
9a1086da OJ	128	return TEGRA_REVISION_A03p;
	129	else
	130	return TEGRA_REVISION_A03;
	131	case 4:
	132	return TEGRA_REVISION_A04;
	133	default:
	134	return TEGRA_REVISION_UNKNOWN;
	135	}
73625e3e CC	136	}
73625e3e CC	137
25cd5a39 DH	138	static void tegra_get_process_id(void)
	139	{
	140	u32 reg;
	141
cdcb5a07 AC	142	tegra_fuse_enable_clk();
cdcb5a07 AC	143
25cd5a39 DH	144	reg = tegra_fuse_readl(tegra_fuse_spare_bit);
	145	tegra_cpu_process_id = (reg >> 6) & 3;
	146	reg = tegra_fuse_readl(tegra_fuse_spare_bit);
	147	tegra_core_process_id = (reg >> 12) & 3;
cdcb5a07 AC	148
cdcb5a07 AC	149	tegra_fuse_disable_clk();
25cd5a39 DH	150	}
25cd5a39 DH	151
c7736edf PG	152	u32 tegra_read_chipid(void)
	153	{
	154	return readl_relaxed(IO_ADDRESS(TEGRA_APB_MISC_BASE) + 0x804);
	155	}
	156
3bd1ae57 SW	157	static void __init tegra20_fuse_init_randomness(void)
	158	{
	159	u32 randomness[2];
	160
	161	randomness[0] = tegra_fuse_readl(FUSE_UID_LOW);
	162	randomness[1] = tegra_fuse_readl(FUSE_UID_HIGH);
	163
	164	add_device_randomness(randomness, sizeof(randomness));
	165	}
	166
	167	/* Applies to Tegra30 or later */
	168	static void __init tegra30_fuse_init_randomness(void)
	169	{
	170	u32 randomness[7];
	171
	172	randomness[0] = tegra_fuse_readl(FUSE_VENDOR_CODE);
	173	randomness[1] = tegra_fuse_readl(FUSE_FAB_CODE);
	174	randomness[2] = tegra_fuse_readl(FUSE_LOT_CODE_0);
	175	randomness[3] = tegra_fuse_readl(FUSE_LOT_CODE_1);
	176	randomness[4] = tegra_fuse_readl(FUSE_WAFER_ID);
	177	randomness[5] = tegra_fuse_readl(FUSE_X_COORDINATE);
	178	randomness[6] = tegra_fuse_readl(FUSE_Y_COORDINATE);
	179
	180	add_device_randomness(randomness, sizeof(randomness));
	181	}
	182
5875df17	183	void __init tegra_init_fuse(void)
73625e3e	184	{
35b1498a	185	u32 id;
3bd1ae57	186	u32 randomness[5];
35b1498a	187
f8e798a9	188	u32 reg = readl(IO_ADDRESS(TEGRA_CLK_RESET_BASE + 0x48));
73625e3e	189	reg \|= 1 << 28;
f8e798a9	190	writel(reg, IO_ADDRESS(TEGRA_CLK_RESET_BASE + 0x48));
73625e3e	191
cdcb5a07 AC	192	/*
	193	* Enable FUSE clock. This needs to be hardcoded because the clock
	194	* subsystem is not active during early boot.
	195	*/
	196	reg = readl(IO_ADDRESS(TEGRA_CLK_RESET_BASE + 0x14));
	197	reg \|= 1 << 7;
	198	writel(reg, IO_ADDRESS(TEGRA_CLK_RESET_BASE + 0x14));
	199	fuse_clk = ERR_PTR(-EINVAL);
	200
9a1086da	201	reg = tegra_fuse_readl(FUSE_SKU_INFO);
3bd1ae57	202	randomness[0] = reg;
9a1086da OJ	203	tegra_sku_id = reg & 0xFF;
9a1086da OJ	204
dee47183	205	reg = tegra_apb_readl(TEGRA_APB_MISC_BASE + STRAP_OPT);
3bd1ae57	206	randomness[1] = reg;
dee47183 OJ	207	tegra_bct_strapping = (reg & RAM_ID_MASK) >> RAM_CODE_SHIFT;
dee47183 OJ	208
c7736edf	209	id = tegra_read_chipid();
3bd1ae57	210	randomness[2] = id;
35b1498a PDS	211	tegra_chip_id = (id >> 8) & 0xff;
35b1498a PDS	212
25cd5a39 DH	213	switch (tegra_chip_id) {
25cd5a39 DH	214	case TEGRA20:
f8ddda71	215	tegra_fuse_spare_bit = TEGRA20_FUSE_SPARE_BIT;
25cd5a39 DH	216	tegra_init_speedo_data = &tegra20_init_speedo_data;
25cd5a39 DH	217	break;
f8ddda71 DH	218	case TEGRA30:
	219	tegra_fuse_spare_bit = TEGRA30_FUSE_SPARE_BIT;
	220	tegra_init_speedo_data = &tegra30_init_speedo_data;
	221	break;
7495b2eb DH	222	case TEGRA114:
	223	tegra_init_speedo_data = &tegra114_init_speedo_data;
	224	break;
25cd5a39	225	default:
f8ddda71 DH	226	pr_warn("Tegra: unknown chip id %d\n", tegra_chip_id);
f8ddda71 DH	227	tegra_fuse_spare_bit = TEGRA20_FUSE_SPARE_BIT;
25cd5a39 DH	228	tegra_init_speedo_data = &tegra_get_process_id;
	229	}
	230
35b1498a	231	tegra_revision = tegra_get_revision(id);
25cd5a39	232	tegra_init_speedo_data();
3bd1ae57 SW	233	randomness[3] = (tegra_cpu_process_id << 16) \| tegra_core_process_id;
	234	randomness[4] = (tegra_cpu_speedo_id << 16) \| tegra_soc_speedo_id;
	235
	236	add_device_randomness(randomness, sizeof(randomness));
	237	switch (tegra_chip_id) {
	238	case TEGRA20:
	239	tegra20_fuse_init_randomness();
b988ba1b	240	break;
3bd1ae57 SW	241	case TEGRA30:
	242	case TEGRA114:
	243	default:
	244	tegra30_fuse_init_randomness();
b988ba1b	245	break;
3bd1ae57	246	}
9a1086da OJ	247
9a1086da OJ	248	pr_info("Tegra Revision: %s SKU: %d CPU Process: %d Core Process: %d\n",
35b1498a	249	tegra_revision_name[tegra_revision],
9a1086da OJ	250	tegra_sku_id, tegra_cpu_process_id,
9a1086da OJ	251	tegra_core_process_id);
73625e3e	252	}