[deliverable/linux.git] / arch / arm / mach-tegra / fuse.c

/*
 * arch/arm/mach-tegra/fuse.c
 *
 * Copyright (C) 2010 Google, Inc.
 *
 * Author:
 *	Colin Cross <ccross@android.com>
 *
 * This software is licensed under the terms of the GNU General Public
 * License version 2, as published by the Free Software Foundation, and
 * may be copied, distributed, and modified under those terms.
 *
 * This program is distributed in the hope that it will be useful,
 * but WITHOUT ANY WARRANTY; without even the implied warranty of
 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
 * GNU General Public License for more details.
 *
 */

#include <linux/kernel.h>
#include <linux/io.h>
#include <linux/export.h>

#include "fuse.h"
#include "iomap.h"
#include "apbio.h"

#define FUSE_UID_LOW		0x108
#define FUSE_UID_HIGH		0x10c
#define FUSE_SKU_INFO		0x110

#define TEGRA20_FUSE_SPARE_BIT		0x200

int tegra_sku_id;
int tegra_cpu_process_id;
int tegra_core_process_id;
int tegra_chip_id;
int tegra_soc_speedo_id;
enum tegra_revision tegra_revision;

static int tegra_fuse_spare_bit;
static void (*tegra_init_speedo_data)(void);

/* The BCT to use at boot is specified by board straps that can be read
 * through a APB misc register and decoded. 2 bits, i.e. 4 possible BCTs.
 */
int tegra_bct_strapping;

#define STRAP_OPT 0x008
#define GMI_AD0 (1 << 4)
#define GMI_AD1 (1 << 5)
#define RAM_ID_MASK (GMI_AD0 | GMI_AD1)
#define RAM_CODE_SHIFT 4

static const char *tegra_revision_name[TEGRA_REVISION_MAX] = {
	[TEGRA_REVISION_UNKNOWN] = "unknown",
	[TEGRA_REVISION_A01]     = "A01",
	[TEGRA_REVISION_A02]     = "A02",
	[TEGRA_REVISION_A03]     = "A03",
	[TEGRA_REVISION_A03p]    = "A03 prime",
	[TEGRA_REVISION_A04]     = "A04",
};

u32 tegra_fuse_readl(unsigned long offset)
{
	return tegra_apb_readl(TEGRA_FUSE_BASE + offset);
}

bool tegra_spare_fuse(int bit)
{
	return tegra_fuse_readl(tegra_fuse_spare_bit + bit * 4);
}

static enum tegra_revision tegra_get_revision(u32 id)
{
	u32 minor_rev = (id >> 16) & 0xf;

	switch (minor_rev) {
	case 1:
		return TEGRA_REVISION_A01;
	case 2:
		return TEGRA_REVISION_A02;
	case 3:
		if (tegra_chip_id == TEGRA20 &&
			(tegra_spare_fuse(18) || tegra_spare_fuse(19)))
			return TEGRA_REVISION_A03p;
		else
			return TEGRA_REVISION_A03;
	case 4:
		return TEGRA_REVISION_A04;
	default:
		return TEGRA_REVISION_UNKNOWN;
	}
}

static void tegra_get_process_id(void)
{
	u32 reg;

	reg = tegra_fuse_readl(tegra_fuse_spare_bit);
	tegra_cpu_process_id = (reg >> 6) & 3;
	reg = tegra_fuse_readl(tegra_fuse_spare_bit);
	tegra_core_process_id = (reg >> 12) & 3;
}

void tegra_init_fuse(void)
{
	u32 id;

	u32 reg = readl(IO_ADDRESS(TEGRA_CLK_RESET_BASE + 0x48));
	reg |= 1 << 28;
	writel(reg, IO_ADDRESS(TEGRA_CLK_RESET_BASE + 0x48));

	reg = tegra_fuse_readl(FUSE_SKU_INFO);
	tegra_sku_id = reg & 0xFF;

	reg = tegra_apb_readl(TEGRA_APB_MISC_BASE + STRAP_OPT);
	tegra_bct_strapping = (reg & RAM_ID_MASK) >> RAM_CODE_SHIFT;

	id = readl_relaxed(IO_ADDRESS(TEGRA_APB_MISC_BASE) + 0x804);
	tegra_chip_id = (id >> 8) & 0xff;

	tegra_fuse_spare_bit = TEGRA20_FUSE_SPARE_BIT;

	switch (tegra_chip_id) {
	case TEGRA20:
		tegra_init_speedo_data = &tegra20_init_speedo_data;
		break;
	default:
		tegra_init_speedo_data = &tegra_get_process_id;
	}

	tegra_revision = tegra_get_revision(id);
	tegra_init_speedo_data();

	pr_info("Tegra Revision: %s SKU: %d CPU Process: %d Core Process: %d\n",
		tegra_revision_name[tegra_revision],
		tegra_sku_id, tegra_cpu_process_id,
		tegra_core_process_id);
}

unsigned long long tegra_chip_uid(void)
{
	unsigned long long lo, hi;

	lo = tegra_fuse_readl(FUSE_UID_LOW);
	hi = tegra_fuse_readl(FUSE_UID_HIGH);
	return (hi << 32ull) | lo;
}
EXPORT_SYMBOL(tegra_chip_uid);
Commit	Line	Data
73625e3e CC	1	/*
	2	* arch/arm/mach-tegra/fuse.c
	3	*
	4	* Copyright (C) 2010 Google, Inc.
	5	*
	6	* Author:
	7	* Colin Cross <ccross@android.com>
	8	*
	9	* This software is licensed under the terms of the GNU General Public
	10	* License version 2, as published by the Free Software Foundation, and
	11	* may be copied, distributed, and modified under those terms.
	12	*
	13	* This program is distributed in the hope that it will be useful,
	14	* but WITHOUT ANY WARRANTY; without even the implied warranty of
	15	* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
	16	* GNU General Public License for more details.
	17	*
	18	*/
	19
	20	#include <linux/kernel.h>
	21	#include <linux/io.h>
34800598	22	#include <linux/export.h>
73625e3e	23
73625e3e	24	#include "fuse.h"
2be39c07	25	#include "iomap.h"
d262f49d	26	#include "apbio.h"
73625e3e CC	27
	28	#define FUSE_UID_LOW 0x108
	29	#define FUSE_UID_HIGH 0x10c
	30	#define FUSE_SKU_INFO 0x110
1f851a26 DH	31
1f851a26 DH	32	#define TEGRA20_FUSE_SPARE_BIT 0x200
73625e3e	33
9a1086da OJ	34	int tegra_sku_id;
	35	int tegra_cpu_process_id;
	36	int tegra_core_process_id;
4c4ad669	37	int tegra_chip_id;
25cd5a39	38	int tegra_soc_speedo_id;
9a1086da OJ	39	enum tegra_revision tegra_revision;
9a1086da OJ	40
1f851a26	41	static int tegra_fuse_spare_bit;
25cd5a39	42	static void (*tegra_init_speedo_data)(void);
1f851a26	43
dee47183 OJ	44	/* The BCT to use at boot is specified by board straps that can be read
	45	* through a APB misc register and decoded. 2 bits, i.e. 4 possible BCTs.
	46	*/
	47	int tegra_bct_strapping;
	48
	49	#define STRAP_OPT 0x008
	50	#define GMI_AD0 (1 << 4)
	51	#define GMI_AD1 (1 << 5)
	52	#define RAM_ID_MASK (GMI_AD0 \| GMI_AD1)
	53	#define RAM_CODE_SHIFT 4
	54
9a1086da OJ	55	static const char *tegra_revision_name[TEGRA_REVISION_MAX] = {
	56	[TEGRA_REVISION_UNKNOWN] = "unknown",
	57	[TEGRA_REVISION_A01] = "A01",
	58	[TEGRA_REVISION_A02] = "A02",
	59	[TEGRA_REVISION_A03] = "A03",
	60	[TEGRA_REVISION_A03p] = "A03 prime",
	61	[TEGRA_REVISION_A04] = "A04",
	62	};
	63
1f851a26	64	u32 tegra_fuse_readl(unsigned long offset)
73625e3e	65	{
d262f49d	66	return tegra_apb_readl(TEGRA_FUSE_BASE + offset);
73625e3e CC	67	}
73625e3e CC	68
1f851a26	69	bool tegra_spare_fuse(int bit)
73625e3e	70	{
1f851a26	71	return tegra_fuse_readl(tegra_fuse_spare_bit + bit * 4);
73625e3e CC	72	}
73625e3e CC	73
35b1498a	74	static enum tegra_revision tegra_get_revision(u32 id)
73625e3e	75	{
9a1086da	76	u32 minor_rev = (id >> 16) & 0xf;
9a1086da OJ	77
	78	switch (minor_rev) {
	79	case 1:
	80	return TEGRA_REVISION_A01;
	81	case 2:
	82	return TEGRA_REVISION_A02;
	83	case 3:
35b1498a	84	if (tegra_chip_id == TEGRA20 &&
1f851a26	85	(tegra_spare_fuse(18) \|\| tegra_spare_fuse(19)))
9a1086da OJ	86	return TEGRA_REVISION_A03p;
	87	else
	88	return TEGRA_REVISION_A03;
	89	case 4:
	90	return TEGRA_REVISION_A04;
	91	default:
	92	return TEGRA_REVISION_UNKNOWN;
	93	}
73625e3e CC	94	}
73625e3e CC	95
25cd5a39 DH	96	static void tegra_get_process_id(void)
	97	{
	98	u32 reg;
	99
	100	reg = tegra_fuse_readl(tegra_fuse_spare_bit);
	101	tegra_cpu_process_id = (reg >> 6) & 3;
	102	reg = tegra_fuse_readl(tegra_fuse_spare_bit);
	103	tegra_core_process_id = (reg >> 12) & 3;
	104	}
	105
73625e3e CC	106	void tegra_init_fuse(void)
73625e3e CC	107	{
35b1498a PDS	108	u32 id;
35b1498a PDS	109
f8e798a9	110	u32 reg = readl(IO_ADDRESS(TEGRA_CLK_RESET_BASE + 0x48));
73625e3e	111	reg \|= 1 << 28;
f8e798a9	112	writel(reg, IO_ADDRESS(TEGRA_CLK_RESET_BASE + 0x48));
73625e3e	113
9a1086da OJ	114	reg = tegra_fuse_readl(FUSE_SKU_INFO);
	115	tegra_sku_id = reg & 0xFF;
	116
dee47183 OJ	117	reg = tegra_apb_readl(TEGRA_APB_MISC_BASE + STRAP_OPT);
	118	tegra_bct_strapping = (reg & RAM_ID_MASK) >> RAM_CODE_SHIFT;
	119
35b1498a PDS	120	id = readl_relaxed(IO_ADDRESS(TEGRA_APB_MISC_BASE) + 0x804);
	121	tegra_chip_id = (id >> 8) & 0xff;
	122
25cd5a39 DH	123	tegra_fuse_spare_bit = TEGRA20_FUSE_SPARE_BIT;
	124
	125	switch (tegra_chip_id) {
	126	case TEGRA20:
	127	tegra_init_speedo_data = &tegra20_init_speedo_data;
	128	break;
	129	default:
	130	tegra_init_speedo_data = &tegra_get_process_id;
	131	}
	132
35b1498a	133	tegra_revision = tegra_get_revision(id);
25cd5a39	134	tegra_init_speedo_data();
9a1086da OJ	135
9a1086da OJ	136	pr_info("Tegra Revision: %s SKU: %d CPU Process: %d Core Process: %d\n",
35b1498a	137	tegra_revision_name[tegra_revision],
9a1086da OJ	138	tegra_sku_id, tegra_cpu_process_id,
9a1086da OJ	139	tegra_core_process_id);
73625e3e CC	140	}
	141
	142	unsigned long long tegra_chip_uid(void)
	143	{
	144	unsigned long long lo, hi;
	145
d262f49d OJ	146	lo = tegra_fuse_readl(FUSE_UID_LOW);
d262f49d OJ	147	hi = tegra_fuse_readl(FUSE_UID_HIGH);
73625e3e CC	148	return (hi << 32ull) \| lo;
73625e3e CC	149	}
e87e06cd	150	EXPORT_SYMBOL(tegra_chip_uid);