[deliverable/linux.git] / arch / arm / mach-tegra / fuse.c

/*
 * arch/arm/mach-tegra/fuse.c
 *
 * Copyright (C) 2010 Google, Inc.
 *
 * Author:
 *	Colin Cross <ccross@android.com>
 *
 * This software is licensed under the terms of the GNU General Public
 * License version 2, as published by the Free Software Foundation, and
 * may be copied, distributed, and modified under those terms.
 *
 * This program is distributed in the hope that it will be useful,
 * but WITHOUT ANY WARRANTY; without even the implied warranty of
 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
 * GNU General Public License for more details.
 *
 */

#include <linux/kernel.h>
#include <linux/io.h>
#include <linux/export.h>
#include <linux/tegra-soc.h>

#include "fuse.h"
#include "iomap.h"
#include "apbio.h"

#define FUSE_UID_LOW		0x108
#define FUSE_UID_HIGH		0x10c
#define FUSE_SKU_INFO		0x110

#define TEGRA20_FUSE_SPARE_BIT		0x200
#define TEGRA30_FUSE_SPARE_BIT		0x244

int tegra_sku_id;
int tegra_cpu_process_id;
int tegra_core_process_id;
int tegra_chip_id;
int tegra_cpu_speedo_id;		/* only exist in Tegra30 and later */
int tegra_soc_speedo_id;
enum tegra_revision tegra_revision;

static int tegra_fuse_spare_bit;
static void (*tegra_init_speedo_data)(void);

/* The BCT to use at boot is specified by board straps that can be read
 * through a APB misc register and decoded. 2 bits, i.e. 4 possible BCTs.
 */
int tegra_bct_strapping;

#define STRAP_OPT 0x008
#define GMI_AD0 (1 << 4)
#define GMI_AD1 (1 << 5)
#define RAM_ID_MASK (GMI_AD0 | GMI_AD1)
#define RAM_CODE_SHIFT 4

static const char *tegra_revision_name[TEGRA_REVISION_MAX] = {
	[TEGRA_REVISION_UNKNOWN] = "unknown",
	[TEGRA_REVISION_A01]     = "A01",
	[TEGRA_REVISION_A02]     = "A02",
	[TEGRA_REVISION_A03]     = "A03",
	[TEGRA_REVISION_A03p]    = "A03 prime",
	[TEGRA_REVISION_A04]     = "A04",
};

u32 tegra_fuse_readl(unsigned long offset)
{
	return tegra_apb_readl(TEGRA_FUSE_BASE + offset);
}

bool tegra_spare_fuse(int bit)
{
	return tegra_fuse_readl(tegra_fuse_spare_bit + bit * 4);
}

static enum tegra_revision tegra_get_revision(u32 id)
{
	u32 minor_rev = (id >> 16) & 0xf;

	switch (minor_rev) {
	case 1:
		return TEGRA_REVISION_A01;
	case 2:
		return TEGRA_REVISION_A02;
	case 3:
		if (tegra_chip_id == TEGRA20 &&
			(tegra_spare_fuse(18) || tegra_spare_fuse(19)))
			return TEGRA_REVISION_A03p;
		else
			return TEGRA_REVISION_A03;
	case 4:
		return TEGRA_REVISION_A04;
	default:
		return TEGRA_REVISION_UNKNOWN;
	}
}

static void tegra_get_process_id(void)
{
	u32 reg;

	reg = tegra_fuse_readl(tegra_fuse_spare_bit);
	tegra_cpu_process_id = (reg >> 6) & 3;
	reg = tegra_fuse_readl(tegra_fuse_spare_bit);
	tegra_core_process_id = (reg >> 12) & 3;
}

u32 tegra_read_chipid(void)
{
	return readl_relaxed(IO_ADDRESS(TEGRA_APB_MISC_BASE) + 0x804);
}

void tegra_init_fuse(void)
{
	u32 id;

	u32 reg = readl(IO_ADDRESS(TEGRA_CLK_RESET_BASE + 0x48));
	reg |= 1 << 28;
	writel(reg, IO_ADDRESS(TEGRA_CLK_RESET_BASE + 0x48));

	reg = tegra_fuse_readl(FUSE_SKU_INFO);
	tegra_sku_id = reg & 0xFF;

	reg = tegra_apb_readl(TEGRA_APB_MISC_BASE + STRAP_OPT);
	tegra_bct_strapping = (reg & RAM_ID_MASK) >> RAM_CODE_SHIFT;

	id = tegra_read_chipid();
	tegra_chip_id = (id >> 8) & 0xff;

	switch (tegra_chip_id) {
	case TEGRA20:
		tegra_fuse_spare_bit = TEGRA20_FUSE_SPARE_BIT;
		tegra_init_speedo_data = &tegra20_init_speedo_data;
		break;
	case TEGRA30:
		tegra_fuse_spare_bit = TEGRA30_FUSE_SPARE_BIT;
		tegra_init_speedo_data = &tegra30_init_speedo_data;
		break;
	default:
		pr_warn("Tegra: unknown chip id %d\n", tegra_chip_id);
		tegra_fuse_spare_bit = TEGRA20_FUSE_SPARE_BIT;
		tegra_init_speedo_data = &tegra_get_process_id;
	}

	tegra_revision = tegra_get_revision(id);
	tegra_init_speedo_data();

	pr_info("Tegra Revision: %s SKU: %d CPU Process: %d Core Process: %d\n",
		tegra_revision_name[tegra_revision],
		tegra_sku_id, tegra_cpu_process_id,
		tegra_core_process_id);
}

unsigned long long tegra_chip_uid(void)
{
	unsigned long long lo, hi;

	lo = tegra_fuse_readl(FUSE_UID_LOW);
	hi = tegra_fuse_readl(FUSE_UID_HIGH);
	return (hi << 32ull) | lo;
}
EXPORT_SYMBOL(tegra_chip_uid);
Commit	Line	Data
73625e3e CC	1	/*
	2	* arch/arm/mach-tegra/fuse.c
	3	*
	4	* Copyright (C) 2010 Google, Inc.
	5	*
	6	* Author:
	7	* Colin Cross <ccross@android.com>
	8	*
	9	* This software is licensed under the terms of the GNU General Public
	10	* License version 2, as published by the Free Software Foundation, and
	11	* may be copied, distributed, and modified under those terms.
	12	*
	13	* This program is distributed in the hope that it will be useful,
	14	* but WITHOUT ANY WARRANTY; without even the implied warranty of
	15	* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
	16	* GNU General Public License for more details.
	17	*
	18	*/
	19
	20	#include <linux/kernel.h>
	21	#include <linux/io.h>
34800598	22	#include <linux/export.h>
c7736edf	23	#include <linux/tegra-soc.h>
73625e3e	24
73625e3e	25	#include "fuse.h"
2be39c07	26	#include "iomap.h"
d262f49d	27	#include "apbio.h"
73625e3e CC	28
	29	#define FUSE_UID_LOW 0x108
	30	#define FUSE_UID_HIGH 0x10c
	31	#define FUSE_SKU_INFO 0x110
1f851a26 DH	32
1f851a26 DH	33	#define TEGRA20_FUSE_SPARE_BIT 0x200
f8ddda71	34	#define TEGRA30_FUSE_SPARE_BIT 0x244
73625e3e	35
9a1086da OJ	36	int tegra_sku_id;
	37	int tegra_cpu_process_id;
	38	int tegra_core_process_id;
4c4ad669	39	int tegra_chip_id;
f8ddda71	40	int tegra_cpu_speedo_id; /* only exist in Tegra30 and later */
25cd5a39	41	int tegra_soc_speedo_id;
9a1086da OJ	42	enum tegra_revision tegra_revision;
9a1086da OJ	43
1f851a26	44	static int tegra_fuse_spare_bit;
25cd5a39	45	static void (*tegra_init_speedo_data)(void);
1f851a26	46
dee47183 OJ	47	/* The BCT to use at boot is specified by board straps that can be read
	48	* through a APB misc register and decoded. 2 bits, i.e. 4 possible BCTs.
	49	*/
	50	int tegra_bct_strapping;
	51
	52	#define STRAP_OPT 0x008
	53	#define GMI_AD0 (1 << 4)
	54	#define GMI_AD1 (1 << 5)
	55	#define RAM_ID_MASK (GMI_AD0 \| GMI_AD1)
	56	#define RAM_CODE_SHIFT 4
	57
9a1086da OJ	58	static const char *tegra_revision_name[TEGRA_REVISION_MAX] = {
	59	[TEGRA_REVISION_UNKNOWN] = "unknown",
	60	[TEGRA_REVISION_A01] = "A01",
	61	[TEGRA_REVISION_A02] = "A02",
	62	[TEGRA_REVISION_A03] = "A03",
	63	[TEGRA_REVISION_A03p] = "A03 prime",
	64	[TEGRA_REVISION_A04] = "A04",
	65	};
	66
1f851a26	67	u32 tegra_fuse_readl(unsigned long offset)
73625e3e	68	{
d262f49d	69	return tegra_apb_readl(TEGRA_FUSE_BASE + offset);
73625e3e CC	70	}
73625e3e CC	71
1f851a26	72	bool tegra_spare_fuse(int bit)
73625e3e	73	{
1f851a26	74	return tegra_fuse_readl(tegra_fuse_spare_bit + bit * 4);
73625e3e CC	75	}
73625e3e CC	76
35b1498a	77	static enum tegra_revision tegra_get_revision(u32 id)
73625e3e	78	{
9a1086da	79	u32 minor_rev = (id >> 16) & 0xf;
9a1086da OJ	80
	81	switch (minor_rev) {
	82	case 1:
	83	return TEGRA_REVISION_A01;
	84	case 2:
	85	return TEGRA_REVISION_A02;
	86	case 3:
35b1498a	87	if (tegra_chip_id == TEGRA20 &&
1f851a26	88	(tegra_spare_fuse(18) \|\| tegra_spare_fuse(19)))
9a1086da OJ	89	return TEGRA_REVISION_A03p;
	90	else
	91	return TEGRA_REVISION_A03;
	92	case 4:
	93	return TEGRA_REVISION_A04;
	94	default:
	95	return TEGRA_REVISION_UNKNOWN;
	96	}
73625e3e CC	97	}
73625e3e CC	98
25cd5a39 DH	99	static void tegra_get_process_id(void)
	100	{
	101	u32 reg;
	102
	103	reg = tegra_fuse_readl(tegra_fuse_spare_bit);
	104	tegra_cpu_process_id = (reg >> 6) & 3;
	105	reg = tegra_fuse_readl(tegra_fuse_spare_bit);
	106	tegra_core_process_id = (reg >> 12) & 3;
	107	}
	108
c7736edf PG	109	u32 tegra_read_chipid(void)
	110	{
	111	return readl_relaxed(IO_ADDRESS(TEGRA_APB_MISC_BASE) + 0x804);
	112	}
	113
73625e3e CC	114	void tegra_init_fuse(void)
73625e3e CC	115	{
35b1498a PDS	116	u32 id;
35b1498a PDS	117
f8e798a9	118	u32 reg = readl(IO_ADDRESS(TEGRA_CLK_RESET_BASE + 0x48));
73625e3e	119	reg \|= 1 << 28;
f8e798a9	120	writel(reg, IO_ADDRESS(TEGRA_CLK_RESET_BASE + 0x48));
73625e3e	121
9a1086da OJ	122	reg = tegra_fuse_readl(FUSE_SKU_INFO);
	123	tegra_sku_id = reg & 0xFF;
	124
dee47183 OJ	125	reg = tegra_apb_readl(TEGRA_APB_MISC_BASE + STRAP_OPT);
	126	tegra_bct_strapping = (reg & RAM_ID_MASK) >> RAM_CODE_SHIFT;
	127
c7736edf	128	id = tegra_read_chipid();
35b1498a PDS	129	tegra_chip_id = (id >> 8) & 0xff;
35b1498a PDS	130
25cd5a39 DH	131	switch (tegra_chip_id) {
25cd5a39 DH	132	case TEGRA20:
f8ddda71	133	tegra_fuse_spare_bit = TEGRA20_FUSE_SPARE_BIT;
25cd5a39 DH	134	tegra_init_speedo_data = &tegra20_init_speedo_data;
25cd5a39 DH	135	break;
f8ddda71 DH	136	case TEGRA30:
	137	tegra_fuse_spare_bit = TEGRA30_FUSE_SPARE_BIT;
	138	tegra_init_speedo_data = &tegra30_init_speedo_data;
	139	break;
25cd5a39	140	default:
f8ddda71 DH	141	pr_warn("Tegra: unknown chip id %d\n", tegra_chip_id);
f8ddda71 DH	142	tegra_fuse_spare_bit = TEGRA20_FUSE_SPARE_BIT;
25cd5a39 DH	143	tegra_init_speedo_data = &tegra_get_process_id;
	144	}
	145
35b1498a	146	tegra_revision = tegra_get_revision(id);
25cd5a39	147	tegra_init_speedo_data();
9a1086da OJ	148
9a1086da OJ	149	pr_info("Tegra Revision: %s SKU: %d CPU Process: %d Core Process: %d\n",
35b1498a	150	tegra_revision_name[tegra_revision],
9a1086da OJ	151	tegra_sku_id, tegra_cpu_process_id,
9a1086da OJ	152	tegra_core_process_id);
73625e3e CC	153	}
	154
	155	unsigned long long tegra_chip_uid(void)
	156	{
	157	unsigned long long lo, hi;
	158
d262f49d OJ	159	lo = tegra_fuse_readl(FUSE_UID_LOW);
d262f49d OJ	160	hi = tegra_fuse_readl(FUSE_UID_HIGH);
73625e3e CC	161	return (hi << 32ull) \| lo;
73625e3e CC	162	}
e87e06cd	163	EXPORT_SYMBOL(tegra_chip_uid);