Commit | Line | Data |
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73625e3e | 1 | /* |
73625e3e | 2 | * Copyright (C) 2010 Google, Inc. |
7495b2eb | 3 | * Copyright (c) 2013, NVIDIA CORPORATION. All rights reserved. |
73625e3e CC |
4 | * |
5 | * Author: | |
6 | * Colin Cross <ccross@android.com> | |
7 | * | |
8 | * This software is licensed under the terms of the GNU General Public | |
9 | * License version 2, as published by the Free Software Foundation, and | |
10 | * may be copied, distributed, and modified under those terms. | |
11 | * | |
12 | * This program is distributed in the hope that it will be useful, | |
13 | * but WITHOUT ANY WARRANTY; without even the implied warranty of | |
14 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
15 | * GNU General Public License for more details. | |
16 | * | |
17 | */ | |
18 | ||
9a1086da OJ |
19 | #ifndef __MACH_TEGRA_FUSE_H |
20 | #define __MACH_TEGRA_FUSE_H | |
21 | ||
22 | enum tegra_revision { | |
23 | TEGRA_REVISION_UNKNOWN = 0, | |
24 | TEGRA_REVISION_A01, | |
25 | TEGRA_REVISION_A02, | |
26 | TEGRA_REVISION_A03, | |
27 | TEGRA_REVISION_A03p, | |
28 | TEGRA_REVISION_A04, | |
29 | TEGRA_REVISION_MAX, | |
30 | }; | |
31 | ||
32 | #define SKU_ID_T20 8 | |
33 | #define SKU_ID_T25SE 20 | |
34 | #define SKU_ID_AP25 23 | |
35 | #define SKU_ID_T25 24 | |
36 | #define SKU_ID_AP25E 27 | |
37 | #define SKU_ID_T25E 28 | |
38 | ||
35b1498a PDS |
39 | #define TEGRA20 0x20 |
40 | #define TEGRA30 0x30 | |
7b30d457 | 41 | #define TEGRA114 0x35 |
35b1498a | 42 | |
9a1086da OJ |
43 | extern int tegra_sku_id; |
44 | extern int tegra_cpu_process_id; | |
45 | extern int tegra_core_process_id; | |
4c4ad669 | 46 | extern int tegra_chip_id; |
f8ddda71 | 47 | extern int tegra_cpu_speedo_id; /* only exist in Tegra30 and later */ |
25cd5a39 | 48 | extern int tegra_soc_speedo_id; |
9a1086da OJ |
49 | extern enum tegra_revision tegra_revision; |
50 | ||
dee47183 OJ |
51 | extern int tegra_bct_strapping; |
52 | ||
73625e3e | 53 | unsigned long long tegra_chip_uid(void); |
73625e3e | 54 | void tegra_init_fuse(void); |
1f851a26 DH |
55 | bool tegra_spare_fuse(int bit); |
56 | u32 tegra_fuse_readl(unsigned long offset); | |
9a1086da | 57 | |
25cd5a39 DH |
58 | #ifdef CONFIG_ARCH_TEGRA_2x_SOC |
59 | void tegra20_init_speedo_data(void); | |
60 | #else | |
61 | static inline void tegra20_init_speedo_data(void) {} | |
62 | #endif | |
63 | ||
f8ddda71 DH |
64 | #ifdef CONFIG_ARCH_TEGRA_3x_SOC |
65 | void tegra30_init_speedo_data(void); | |
66 | #else | |
67 | static inline void tegra30_init_speedo_data(void) {} | |
68 | #endif | |
69 | ||
7495b2eb DH |
70 | #ifdef CONFIG_ARCH_TEGRA_114_SOC |
71 | void tegra114_init_speedo_data(void); | |
72 | #else | |
73 | static inline void tegra114_init_speedo_data(void) {} | |
74 | #endif | |
75 | ||
9a1086da | 76 | #endif |