projects / deliverable / linux.git / blame
| Commit | Line | Data |
|---|---|---|
| 5ad36c5f | 1 | /* |
| 938fa349 | 2 | * Copyright (C) 2011 Google, Inc. |
| 5ad36c5f EG |
3 | * |
| 4 | * Author: | |
| 938fa349 | 5 | * Colin Cross <ccross@android.com> |
| 5ad36c5f | 6 | * |
| e307cc89 | 7 | * Copyright (C) 2010,2013, NVIDIA Corporation |
| 460907bc | 8 | * |
| 5ad36c5f EG |
9 | * This software is licensed under the terms of the GNU General Public |
| 10 | * License version 2, as published by the Free Software Foundation, and | |
| 11 | * may be copied, distributed, and modified under those terms. | |
| 12 | * | |
| 13 | * This program is distributed in the hope that it will be useful, | |
| 14 | * but WITHOUT ANY WARRANTY; without even the implied warranty of | |
| 15 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
| 16 | * GNU General Public License for more details. | |
| 17 | * | |
| 18 | */ | |
| 19 | ||
| 7e8b15db | 20 | #include <linux/cpu_pm.h> |
| 5ad36c5f | 21 | #include <linux/interrupt.h> |
| 5ad36c5f | 22 | #include <linux/io.h> |
| 520f7bd7 | 23 | #include <linux/irqchip/arm-gic.h> |
| a0524acc TR |
24 | #include <linux/irq.h> |
| 25 | #include <linux/kernel.h> | |
| 26 | #include <linux/of_address.h> | |
| 27 | #include <linux/of.h> | |
| e307cc89 | 28 | #include <linux/syscore_ops.h> |
| 5ad36c5f | 29 | |
| 5ad36c5f | 30 | #include "board.h" |
| 2be39c07 | 31 | #include "iomap.h" |
| 4f71a888 | 32 | #include "irq.h" |
| 5ad36c5f | 33 | |
| d4b92fb2 JL |
34 | #define SGI_MASK 0xFFFF |
| 35 | ||
| e307cc89 | 36 | #ifdef CONFIG_PM_SLEEP |
| 7e8b15db | 37 | static void __iomem *tegra_gic_cpu_base; |
| e307cc89 JL |
38 | #endif |
| 39 | ||
| d4b92fb2 JL |
40 | bool tegra_pending_sgi(void) |
| 41 | { | |
| 42 | u32 pending_set; | |
| 43 | void __iomem *distbase = IO_ADDRESS(TEGRA_ARM_INT_DIST_BASE); | |
| 44 | ||
| 45 | pending_set = readl_relaxed(distbase + GIC_DIST_PENDING_SET); | |
| 46 | ||
| 47 | if (pending_set & SGI_MASK) | |
| 48 | return true; | |
| 49 | ||
| 50 | return false; | |
| 51 | } | |
| 52 | ||
| e307cc89 | 53 | #ifdef CONFIG_PM_SLEEP |
| 7e8b15db JL |
54 | static int tegra_gic_notifier(struct notifier_block *self, |
| 55 | unsigned long cmd, void *v) | |
| 56 | { | |
| 57 | switch (cmd) { | |
| 58 | case CPU_PM_ENTER: | |
| 59 | writel_relaxed(0x1E0, tegra_gic_cpu_base + GIC_CPU_CTRL); | |
| 60 | break; | |
| 61 | } | |
| 62 | ||
| 63 | return NOTIFY_OK; | |
| 64 | } | |
| 65 | ||
| 66 | static struct notifier_block tegra_gic_notifier_block = { | |
| 67 | .notifier_call = tegra_gic_notifier, | |
| 68 | }; | |
| 69 | ||
| 70 | static const struct of_device_id tegra114_dt_gic_match[] __initconst = { | |
| 71 | { .compatible = "arm,cortex-a15-gic" }, | |
| 72 | { } | |
| 73 | }; | |
| 74 | ||
| 75 | static void tegra114_gic_cpu_pm_registration(void) | |
| 76 | { | |
| 77 | struct device_node *dn; | |
| 78 | ||
| 79 | dn = of_find_matching_node(NULL, tegra114_dt_gic_match); | |
| 80 | if (!dn) | |
| 81 | return; | |
| 82 | ||
| 83 | tegra_gic_cpu_base = of_iomap(dn, 1); | |
| 84 | ||
| 85 | cpu_pm_register_notifier(&tegra_gic_notifier_block); | |
| 86 | } | |
| e307cc89 | 87 | #else |
| 7e8b15db | 88 | static void tegra114_gic_cpu_pm_registration(void) { } |
| e307cc89 JL |
89 | #endif |
| 90 | ||
| e9479e0e MZ |
91 | static const struct of_device_id tegra_ictlr_match[] __initconst = { |
| 92 | { .compatible = "nvidia,tegra20-ictlr" }, | |
| 93 | { .compatible = "nvidia,tegra30-ictlr" }, | |
| 94 | { } | |
| 95 | }; | |
| 96 | ||
| 5ad36c5f EG |
97 | void __init tegra_init_irq(void) |
| 98 | { | |
| 1a703bff MZ |
99 | if (WARN_ON(!of_find_matching_node(NULL, tegra_ictlr_match))) |
| 100 | pr_warn("Outdated DT detected, suspend/resume will NOT work\n"); | |
| 938fa349 | 101 | |
| 7e8b15db | 102 | tegra114_gic_cpu_pm_registration(); |
| 460907bc | 103 | } |