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Merge branch 'stable' of git://git.kernel.org/pub/scm/linux/kernel/git/cmetcalf/linux...
[deliverable/linux.git] / arch / arm / mach-tegra / pcie.c
CommitLineData
77ffc146
MR		 1/*
2 * arch/arm/mach-tegra/pci.c
3 *
4 * PCIe host controller driver for TEGRA(2) SOCs
5 *
6 * Copyright (c) 2010, CompuLab, Ltd.
7 * Author: Mike Rapoport <mike@compulab.co.il>
8 *
9 * Based on NVIDIA PCIe driver
10 * Copyright (c) 2008-2009, NVIDIA Corporation.
11 *
12 * Bits taken from arch/arm/mach-dove/pcie.c
13 *
14 * This program is free software; you can redistribute it and/or modify
15 * it under the terms of the GNU General Public License as published by
16 * the Free Software Foundation; either version 2 of the License, or
17 * (at your option) any later version.
18 *
19 * This program is distributed in the hope that it will be useful, but WITHOUT
20 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
21 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
22 * more details.
23 *
24 * You should have received a copy of the GNU General Public License along
25 * with this program; if not, write to the Free Software Foundation, Inc.,
26 * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA.
27 */
28
29#include <linux/kernel.h>
30#include <linux/pci.h>
31#include <linux/interrupt.h>
32#include <linux/irq.h>
33#include <linux/clk.h>
34#include <linux/delay.h>
dc28094b 35#include <linux/export.h>
61fd290d 36#include <linux/clk/tegra.h>
e4bcda28 37#include <linux/tegra-powergate.h>
77ffc146
MR		 38
39#include <asm/sizes.h>
40#include <asm/mach/pci.h>
41
3ead5137 42#include "board.h"
2be39c07 43#include "iomap.h"
3ead5137 44
c5a4d6b0
SW		 45/* Hack - need to parse this from DT */
46#define INT_PCIE_INTR 130
47
77ffc146
MR		 48/* register definitions */
49#define AFI_OFFSET 0x3800
50#define PADS_OFFSET 0x3000
51#define RP0_OFFSET 0x0000
52#define RP1_OFFSET 0x1000
53
54#define AFI_AXI_BAR0_SZ 0x00
55#define AFI_AXI_BAR1_SZ 0x04
56#define AFI_AXI_BAR2_SZ 0x08
57#define AFI_AXI_BAR3_SZ 0x0c
58#define AFI_AXI_BAR4_SZ 0x10
59#define AFI_AXI_BAR5_SZ 0x14
60
61#define AFI_AXI_BAR0_START 0x18
62#define AFI_AXI_BAR1_START 0x1c
63#define AFI_AXI_BAR2_START 0x20
64#define AFI_AXI_BAR3_START 0x24
65#define AFI_AXI_BAR4_START 0x28
66#define AFI_AXI_BAR5_START 0x2c
67
68#define AFI_FPCI_BAR0 0x30
69#define AFI_FPCI_BAR1 0x34
70#define AFI_FPCI_BAR2 0x38
71#define AFI_FPCI_BAR3 0x3c
72#define AFI_FPCI_BAR4 0x40
73#define AFI_FPCI_BAR5 0x44
74
75#define AFI_CACHE_BAR0_SZ 0x48
76#define AFI_CACHE_BAR0_ST 0x4c
77#define AFI_CACHE_BAR1_SZ 0x50
78#define AFI_CACHE_BAR1_ST 0x54
79
80#define AFI_MSI_BAR_SZ 0x60
81#define AFI_MSI_FPCI_BAR_ST 0x64
82#define AFI_MSI_AXI_BAR_ST 0x68
83
84#define AFI_CONFIGURATION 0xac
85#define AFI_CONFIGURATION_EN_FPCI (1 << 0)
86
87#define AFI_FPCI_ERROR_MASKS 0xb0
88
89#define AFI_INTR_MASK 0xb4
90#define AFI_INTR_MASK_INT_MASK (1 << 0)
91#define AFI_INTR_MASK_MSI_MASK (1 << 8)
92
93#define AFI_INTR_CODE 0xb8
94#define AFI_INTR_CODE_MASK 0xf
95#define AFI_INTR_MASTER_ABORT 4
96#define AFI_INTR_LEGACY 6
97
98#define AFI_INTR_SIGNATURE 0xbc
99#define AFI_SM_INTR_ENABLE 0xc4
100
101#define AFI_AFI_INTR_ENABLE 0xc8
102#define AFI_INTR_EN_INI_SLVERR (1 << 0)
103#define AFI_INTR_EN_INI_DECERR (1 << 1)
104#define AFI_INTR_EN_TGT_SLVERR (1 << 2)
105#define AFI_INTR_EN_TGT_DECERR (1 << 3)
106#define AFI_INTR_EN_TGT_WRERR (1 << 4)
107#define AFI_INTR_EN_DFPCI_DECERR (1 << 5)
108#define AFI_INTR_EN_AXI_DECERR (1 << 6)
109#define AFI_INTR_EN_FPCI_TIMEOUT (1 << 7)
110
111#define AFI_PCIE_CONFIG 0x0f8
112#define AFI_PCIE_CONFIG_PCIEC0_DISABLE_DEVICE (1 << 1)
113#define AFI_PCIE_CONFIG_PCIEC1_DISABLE_DEVICE (1 << 2)
114#define AFI_PCIE_CONFIG_SM2TMS0_XBAR_CONFIG_MASK (0xf << 20)
115#define AFI_PCIE_CONFIG_SM2TMS0_XBAR_CONFIG_SINGLE (0x0 << 20)
116#define AFI_PCIE_CONFIG_SM2TMS0_XBAR_CONFIG_DUAL (0x1 << 20)
117
118#define AFI_FUSE 0x104
119#define AFI_FUSE_PCIE_T0_GEN2_DIS (1 << 2)
120
121#define AFI_PEX0_CTRL 0x110
122#define AFI_PEX1_CTRL 0x118
123#define AFI_PEX_CTRL_RST (1 << 0)
124#define AFI_PEX_CTRL_REFCLK_EN (1 << 3)
125
126#define RP_VEND_XP 0x00000F00
127#define RP_VEND_XP_DL_UP (1 << 30)
128
129#define RP_LINK_CONTROL_STATUS 0x00000090
130#define RP_LINK_CONTROL_STATUS_LINKSTAT_MASK 0x3fff0000
131
132#define PADS_CTL_SEL 0x0000009C
133
134#define PADS_CTL 0x000000A0
135#define PADS_CTL_IDDQ_1L (1 << 0)
136#define PADS_CTL_TX_DATA_EN_1L (1 << 6)
137#define PADS_CTL_RX_DATA_EN_1L (1 << 10)
138
139#define PADS_PLL_CTL 0x000000B8
140#define PADS_PLL_CTL_RST_B4SM (1 << 1)
141#define PADS_PLL_CTL_LOCKDET (1 << 8)
142#define PADS_PLL_CTL_REFCLK_MASK (0x3 << 16)
143#define PADS_PLL_CTL_REFCLK_INTERNAL_CML (0 << 16)
144#define PADS_PLL_CTL_REFCLK_INTERNAL_CMOS (1 << 16)
145#define PADS_PLL_CTL_REFCLK_EXTERNAL (2 << 16)
146#define PADS_PLL_CTL_TXCLKREF_MASK (0x1 << 20)
147#define PADS_PLL_CTL_TXCLKREF_DIV10 (0 << 20)
148#define PADS_PLL_CTL_TXCLKREF_DIV5 (1 << 20)
149
150/* PMC access is required for PCIE xclk (un)clamping */
151#define PMC_SCRATCH42 0x144
152#define PMC_SCRATCH42_PCX_CLAMP (1 << 0)
153
154static void __iomem *reg_pmc_base = IO_ADDRESS(TEGRA_PMC_BASE);
155
156#define pmc_writel(value, reg) \
efaa19a5 157 __raw_writel(value, reg_pmc_base + (reg))
77ffc146 158#define pmc_readl(reg) \
efaa19a5 159 __raw_readl(reg_pmc_base + (reg))
77ffc146
MR		 160
161/*
162 * Tegra2 defines 1GB in the AXI address map for PCIe.
163 *
164 * That address space is split into different regions, with sizes and
165 * offsets as follows:
166 *
167 * 0x80000000 - 0x80003fff - PCI controller registers
168 * 0x80004000 - 0x80103fff - PCI configuration space
169 * 0x80104000 - 0x80203fff - PCI extended configuration space
170 * 0x80203fff - 0x803fffff - unused
171 * 0x80400000 - 0x8040ffff - downstream IO
172 * 0x80410000 - 0x8fffffff - unused
173 * 0x90000000 - 0x9fffffff - non-prefetchable memory
174 * 0xa0000000 - 0xbfffffff - prefetchable memory
175 */
77ffc146
MR		 176#define PCIE_REGS_SZ SZ_16K
177#define PCIE_CFG_OFF PCIE_REGS_SZ
178#define PCIE_CFG_SZ SZ_1M
179#define PCIE_EXT_CFG_OFF (PCIE_CFG_SZ + PCIE_CFG_OFF)
180#define PCIE_EXT_CFG_SZ SZ_1M
181#define PCIE_IOMAP_SZ (PCIE_REGS_SZ + PCIE_CFG_SZ + PCIE_EXT_CFG_SZ)
182
77ffc146
MR		 183#define MEM_BASE_0 (TEGRA_PCIE_BASE + SZ_256M)
184#define MEM_SIZE_0 SZ_128M
185#define MEM_BASE_1 (MEM_BASE_0 + MEM_SIZE_0)
186#define MEM_SIZE_1 SZ_128M
187#define PREFETCH_MEM_BASE_0 (MEM_BASE_1 + MEM_SIZE_1)
188#define PREFETCH_MEM_SIZE_0 SZ_128M
189#define PREFETCH_MEM_BASE_1 (PREFETCH_MEM_BASE_0 + PREFETCH_MEM_SIZE_0)
190#define PREFETCH_MEM_SIZE_1 SZ_128M
191
192#define PCIE_CONF_BUS(b) ((b) << 16)
193#define PCIE_CONF_DEV(d) ((d) << 11)
194#define PCIE_CONF_FUNC(f) ((f) << 8)
195#define PCIE_CONF_REG(r) \
196 (((r) & ~0x3) | (((r) < 256) ? PCIE_CFG_OFF : PCIE_EXT_CFG_OFF))
197
198struct tegra_pcie_port {
199 int index;
200 u8 root_bus_nr;
201 void __iomem *base;
202
203 bool link_up;
204
77ffc146
MR		 205 char mem_space_name[16];
206 char prefetch_space_name[20];
d94c7a04 207 struct resource res[2];
77ffc146
MR		 208};
209
210struct tegra_pcie_info {
211 struct tegra_pcie_port port[2];
212 int num_ports;
213
214 void __iomem *regs;
215 struct resource res_mmio;
216
217 struct clk *pex_clk;
218 struct clk *afi_clk;
219 struct clk *pcie_xclk;
220 struct clk *pll_e;
221};
222
d94c7a04 223static struct tegra_pcie_info tegra_pcie;
77ffc146
MR		 224
225static inline void afi_writel(u32 value, unsigned long offset)
226{
227 writel(value, offset + AFI_OFFSET + tegra_pcie.regs);
228}
229
230static inline u32 afi_readl(unsigned long offset)
231{
232 return readl(offset + AFI_OFFSET + tegra_pcie.regs);
233}
234
235static inline void pads_writel(u32 value, unsigned long offset)
236{
237 writel(value, offset + PADS_OFFSET + tegra_pcie.regs);
238}
239
240static inline u32 pads_readl(unsigned long offset)
241{
242 return readl(offset + PADS_OFFSET + tegra_pcie.regs);
243}
244
245static struct tegra_pcie_port *bus_to_port(int bus)
246{
247 int i;
248
249 for (i = tegra_pcie.num_ports - 1; i >= 0; i--) {
250 int rbus = tegra_pcie.port[i].root_bus_nr;
251 if (rbus != -1 && rbus == bus)
252 break;
253 }
254
255 return i >= 0 ? tegra_pcie.port + i : NULL;
256}
257
258static int tegra_pcie_read_conf(struct pci_bus *bus, unsigned int devfn,
259 int where, int size, u32 *val)
260{
261 struct tegra_pcie_port *pp = bus_to_port(bus->number);
262 void __iomem *addr;
263
264 if (pp) {
265 if (devfn != 0) {
266 *val = 0xffffffff;
267 return PCIBIOS_DEVICE_NOT_FOUND;
268 }
269
270 addr = pp->base + (where & ~0x3);
271 } else {
272 addr = tegra_pcie.regs + (PCIE_CONF_BUS(bus->number) +
273 PCIE_CONF_DEV(PCI_SLOT(devfn)) +
274 PCIE_CONF_FUNC(PCI_FUNC(devfn)) +
275 PCIE_CONF_REG(where));
276 }
277
278 *val = readl(addr);
279
280 if (size == 1)
281 *val = (*val >> (8 * (where & 3))) & 0xff;
282 else if (size == 2)
283 *val = (*val >> (8 * (where & 3))) & 0xffff;
284
285 return PCIBIOS_SUCCESSFUL;
286}
287
288static int tegra_pcie_write_conf(struct pci_bus *bus, unsigned int devfn,
289 int where, int size, u32 val)
290{
291 struct tegra_pcie_port *pp = bus_to_port(bus->number);
292 void __iomem *addr;
293
294 u32 mask;
295 u32 tmp;
296
297 if (pp) {
298 if (devfn != 0)
299 return PCIBIOS_DEVICE_NOT_FOUND;
300
301 addr = pp->base + (where & ~0x3);
302 } else {
303 addr = tegra_pcie.regs + (PCIE_CONF_BUS(bus->number) +
304 PCIE_CONF_DEV(PCI_SLOT(devfn)) +
305 PCIE_CONF_FUNC(PCI_FUNC(devfn)) +
306 PCIE_CONF_REG(where));
307 }
308
309 if (size == 4) {
310 writel(val, addr);
311 return PCIBIOS_SUCCESSFUL;
312 }
313
314 if (size == 2)
315 mask = ~(0xffff << ((where & 0x3) * 8));
316 else if (size == 1)
317 mask = ~(0xff << ((where & 0x3) * 8));
318 else
319 return PCIBIOS_BAD_REGISTER_NUMBER;
320
321 tmp = readl(addr) & mask;
322 tmp |= val << ((where & 0x3) * 8);
323 writel(tmp, addr);
324
325 return PCIBIOS_SUCCESSFUL;
326}
327
328static struct pci_ops tegra_pcie_ops = {
329 .read = tegra_pcie_read_conf,
330 .write = tegra_pcie_write_conf,
331};
332
351a102d 333static void tegra_pcie_fixup_bridge(struct pci_dev *dev)
77ffc146
MR		 334{
335 u16 reg;
336
337 if ((dev->class >> 16) == PCI_BASE_CLASS_BRIDGE) {
338 pci_read_config_word(dev, PCI_COMMAND, &reg);
339 reg |= (PCI_COMMAND_IO | PCI_COMMAND_MEMORY |
340 PCI_COMMAND_MASTER | PCI_COMMAND_SERR);
341 pci_write_config_word(dev, PCI_COMMAND, reg);
342 }
343}
344DECLARE_PCI_FIXUP_FINAL(PCI_ANY_ID, PCI_ANY_ID, tegra_pcie_fixup_bridge);
345
346/* Tegra PCIE root complex wrongly reports device class */
351a102d 347static void tegra_pcie_fixup_class(struct pci_dev *dev)
77ffc146
MR		 348{
349 dev->class = PCI_CLASS_BRIDGE_PCI << 8;
350}
351DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_NVIDIA, 0x0bf0, tegra_pcie_fixup_class);
352DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_NVIDIA, 0x0bf1, tegra_pcie_fixup_class);
353
354/* Tegra PCIE requires relaxed ordering */
351a102d 355static void tegra_pcie_relax_enable(struct pci_dev *dev)
77ffc146 356{
3b87011d 357 pcie_capability_set_word(dev, PCI_EXP_DEVCTL, PCI_EXP_DEVCTL_RELAX_EN);
77ffc146
MR		 358}
359DECLARE_PCI_FIXUP_FINAL(PCI_ANY_ID, PCI_ANY_ID, tegra_pcie_relax_enable);
360
361static int tegra_pcie_setup(int nr, struct pci_sys_data *sys)
362{
363 struct tegra_pcie_port *pp;
364
365 if (nr >= tegra_pcie.num_ports)
366 return 0;
367
368 pp = tegra_pcie.port + nr;
369 pp->root_bus_nr = sys->busnr;
370
d94c7a04 371 pci_ioremap_io(nr * SZ_64K, TEGRA_PCIE_IO_BASE);
77ffc146
MR		 372
373 /*
374 * IORESOURCE_MEM
375 */
376 snprintf(pp->mem_space_name, sizeof(pp->mem_space_name),
377 "PCIe %d MEM", pp->index);
378 pp->mem_space_name[sizeof(pp->mem_space_name) - 1] = 0;
d94c7a04 379 pp->res[0].name = pp->mem_space_name;
77ffc146 380 if (pp->index == 0) {
d94c7a04
RH		 381 pp->res[0].start = MEM_BASE_0;
382 pp->res[0].end = pp->res[0].start + MEM_SIZE_0 - 1;
77ffc146 383 } else {
d94c7a04
RH		 384 pp->res[0].start = MEM_BASE_1;
385 pp->res[0].end = pp->res[0].start + MEM_SIZE_1 - 1;
77ffc146 386 }
d94c7a04
RH		 387 pp->res[0].flags = IORESOURCE_MEM;
388 if (request_resource(&iomem_resource, &pp->res[0]))
77ffc146 389 panic("Request PCIe Memory resource failed\n");
d94c7a04 390 pci_add_resource_offset(&sys->resources, &pp->res[0], sys->mem_offset);
77ffc146
MR		 391
392 /*
393 * IORESOURCE_MEM | IORESOURCE_PREFETCH
394 */
395 snprintf(pp->prefetch_space_name, sizeof(pp->prefetch_space_name),
396 "PCIe %d PREFETCH MEM", pp->index);
397 pp->prefetch_space_name[sizeof(pp->prefetch_space_name) - 1] = 0;
d94c7a04 398 pp->res[1].name = pp->prefetch_space_name;
77ffc146 399 if (pp->index == 0) {
d94c7a04
RH		 400 pp->res[1].start = PREFETCH_MEM_BASE_0;
401 pp->res[1].end = pp->res[1].start + PREFETCH_MEM_SIZE_0 - 1;
77ffc146 402 } else {
d94c7a04
RH		 403 pp->res[1].start = PREFETCH_MEM_BASE_1;
404 pp->res[1].end = pp->res[1].start + PREFETCH_MEM_SIZE_1 - 1;
77ffc146 405 }
d94c7a04
RH		 406 pp->res[1].flags = IORESOURCE_MEM | IORESOURCE_PREFETCH;
407 if (request_resource(&iomem_resource, &pp->res[1]))
77ffc146 408 panic("Request PCIe Prefetch Memory resource failed\n");
d94c7a04 409 pci_add_resource_offset(&sys->resources, &pp->res[1], sys->mem_offset);
77ffc146
MR		 410
411 return 1;
412}
413
d5341942 414static int tegra_pcie_map_irq(const struct pci_dev *dev, u8 slot, u8 pin)
77ffc146
MR		 415{
416 return INT_PCIE_INTR;
417}
418
419static struct pci_bus __init *tegra_pcie_scan_bus(int nr,
420 struct pci_sys_data *sys)
421{
422 struct tegra_pcie_port *pp;
423
424 if (nr >= tegra_pcie.num_ports)
31e66068 425 return NULL;
77ffc146
MR		 426
427 pp = tegra_pcie.port + nr;
428 pp->root_bus_nr = sys->busnr;
429
37d15909
BH		 430 return pci_scan_root_bus(NULL, sys->busnr, &tegra_pcie_ops, sys,
431 &sys->resources);
77ffc146
MR		 432}
433
434static struct hw_pci tegra_pcie_hw __initdata = {
435 .nr_controllers = 2,
436 .setup = tegra_pcie_setup,
437 .scan = tegra_pcie_scan_bus,
77ffc146
MR		 438 .map_irq = tegra_pcie_map_irq,
439};
440
441
442static irqreturn_t tegra_pcie_isr(int irq, void *arg)
443{
444 const char *err_msg[] = {
445 "Unknown",
446 "AXI slave error",
447 "AXI decode error",
448 "Target abort",
449 "Master abort",
450 "Invalid write",
451 "Response decoding error",
452 "AXI response decoding error",
453 "Transcation timeout",
454 };
455
456 u32 code, signature;
457
458 code = afi_readl(AFI_INTR_CODE) & AFI_INTR_CODE_MASK;
459 signature = afi_readl(AFI_INTR_SIGNATURE);
460 afi_writel(0, AFI_INTR_CODE);
461
462 if (code == AFI_INTR_LEGACY)
463 return IRQ_NONE;
464
465 if (code >= ARRAY_SIZE(err_msg))
466 code = 0;
467
468 /*
469 * do not pollute kernel log with master abort reports since they
470 * happen a lot during enumeration
471 */
472 if (code == AFI_INTR_MASTER_ABORT)
473 pr_debug("PCIE: %s, signature: %08x\n", err_msg[code], signature);
474 else
475 pr_err("PCIE: %s, signature: %08x\n", err_msg[code], signature);
476
477 return IRQ_HANDLED;
478}
479
480static void tegra_pcie_setup_translations(void)
481{
482 u32 fpci_bar;
483 u32 size;
484 u32 axi_address;
485
486 /* Bar 0: config Bar */
487 fpci_bar = ((u32)0xfdff << 16);
488 size = PCIE_CFG_SZ;
489 axi_address = TEGRA_PCIE_BASE + PCIE_CFG_OFF;
490 afi_writel(axi_address, AFI_AXI_BAR0_START);
491 afi_writel(size >> 12, AFI_AXI_BAR0_SZ);
492 afi_writel(fpci_bar, AFI_FPCI_BAR0);
493
494 /* Bar 1: extended config Bar */
495 fpci_bar = ((u32)0xfe1 << 20);
496 size = PCIE_EXT_CFG_SZ;
497 axi_address = TEGRA_PCIE_BASE + PCIE_EXT_CFG_OFF;
498 afi_writel(axi_address, AFI_AXI_BAR1_START);
499 afi_writel(size >> 12, AFI_AXI_BAR1_SZ);
500 afi_writel(fpci_bar, AFI_FPCI_BAR1);
501
502 /* Bar 2: downstream IO bar */
503 fpci_bar = ((__u32)0xfdfc << 16);
d94c7a04
RH		 504 size = SZ_128K;
505 axi_address = TEGRA_PCIE_IO_BASE;
77ffc146
MR		 506 afi_writel(axi_address, AFI_AXI_BAR2_START);
507 afi_writel(size >> 12, AFI_AXI_BAR2_SZ);
508 afi_writel(fpci_bar, AFI_FPCI_BAR2);
509
510 /* Bar 3: prefetchable memory BAR */
511 fpci_bar = (((PREFETCH_MEM_BASE_0 >> 12) & 0x0fffffff) << 4) | 0x1;
512 size = PREFETCH_MEM_SIZE_0 + PREFETCH_MEM_SIZE_1;
513 axi_address = PREFETCH_MEM_BASE_0;
514 afi_writel(axi_address, AFI_AXI_BAR3_START);
515 afi_writel(size >> 12, AFI_AXI_BAR3_SZ);
516 afi_writel(fpci_bar, AFI_FPCI_BAR3);
517
518 /* Bar 4: non prefetchable memory BAR */
519 fpci_bar = (((MEM_BASE_0 >> 12) & 0x0FFFFFFF) << 4) | 0x1;
520 size = MEM_SIZE_0 + MEM_SIZE_1;
521 axi_address = MEM_BASE_0;
522 afi_writel(axi_address, AFI_AXI_BAR4_START);
523 afi_writel(size >> 12, AFI_AXI_BAR4_SZ);
524 afi_writel(fpci_bar, AFI_FPCI_BAR4);
525
526 /* Bar 5: NULL out the remaining BAR as it is not used */
527 fpci_bar = 0;
528 size = 0;
529 axi_address = 0;
530 afi_writel(axi_address, AFI_AXI_BAR5_START);
531 afi_writel(size >> 12, AFI_AXI_BAR5_SZ);
532 afi_writel(fpci_bar, AFI_FPCI_BAR5);
533
534 /* map all upstream transactions as uncached */
535 afi_writel(PHYS_OFFSET, AFI_CACHE_BAR0_ST);
536 afi_writel(0, AFI_CACHE_BAR0_SZ);
537 afi_writel(0, AFI_CACHE_BAR1_ST);
538 afi_writel(0, AFI_CACHE_BAR1_SZ);
539
540 /* No MSI */
541 afi_writel(0, AFI_MSI_FPCI_BAR_ST);
542 afi_writel(0, AFI_MSI_BAR_SZ);
543 afi_writel(0, AFI_MSI_AXI_BAR_ST);
544 afi_writel(0, AFI_MSI_BAR_SZ);
545}
546
795d5fd4 547static int tegra_pcie_enable_controller(void)
77ffc146
MR		 548{
549 u32 val, reg;
795d5fd4 550 int i, timeout;
77ffc146
MR		 551
552 /* Enable slot clock and pulse the reset signals */
553 for (i = 0, reg = AFI_PEX0_CTRL; i < 2; i++, reg += 0x8) {
554 val = afi_readl(reg) | AFI_PEX_CTRL_REFCLK_EN;
555 afi_writel(val, reg);
556 val &= ~AFI_PEX_CTRL_RST;
557 afi_writel(val, reg);
558
559 val = afi_readl(reg) | AFI_PEX_CTRL_RST;
560 afi_writel(val, reg);
561 }
562
563 /* Enable dual controller and both ports */
564 val = afi_readl(AFI_PCIE_CONFIG);
565 val &= ~(AFI_PCIE_CONFIG_PCIEC0_DISABLE_DEVICE |
566 AFI_PCIE_CONFIG_PCIEC1_DISABLE_DEVICE |
567 AFI_PCIE_CONFIG_SM2TMS0_XBAR_CONFIG_MASK);
568 val |= AFI_PCIE_CONFIG_SM2TMS0_XBAR_CONFIG_DUAL;
569 afi_writel(val, AFI_PCIE_CONFIG);
570
571 val = afi_readl(AFI_FUSE) & ~AFI_FUSE_PCIE_T0_GEN2_DIS;
572 afi_writel(val, AFI_FUSE);
573
574 /* Initialze internal PHY, enable up to 16 PCIE lanes */
575 pads_writel(0x0, PADS_CTL_SEL);
576
577 /* override IDDQ to 1 on all 4 lanes */
578 val = pads_readl(PADS_CTL) | PADS_CTL_IDDQ_1L;
579 pads_writel(val, PADS_CTL);
580
581 /*
582 * set up PHY PLL inputs select PLLE output as refclock,
583 * set TX ref sel to div10 (not div5)
584 */
585 val = pads_readl(PADS_PLL_CTL);
586 val &= ~(PADS_PLL_CTL_REFCLK_MASK | PADS_PLL_CTL_TXCLKREF_MASK);
587 val |= (PADS_PLL_CTL_REFCLK_INTERNAL_CML | PADS_PLL_CTL_TXCLKREF_DIV10);
588 pads_writel(val, PADS_PLL_CTL);
589
590 /* take PLL out of reset */
591 val = pads_readl(PADS_PLL_CTL) | PADS_PLL_CTL_RST_B4SM;
592 pads_writel(val, PADS_PLL_CTL);
593
594 /*
595 * Hack, set the clock voltage to the DEFAULT provided by hw folks.
596 * This doesn't exist in the documentation
597 */
598 pads_writel(0xfa5cfa5c, 0xc8);
599
600 /* Wait for the PLL to lock */
2f926eec 601 timeout = 300;
77ffc146
MR		 602 do {
603 val = pads_readl(PADS_PLL_CTL);
2f926eec 604 usleep_range(1000, 1000);
795d5fd4
DA		 605 if (--timeout == 0) {
606 pr_err("Tegra PCIe error: timeout waiting for PLL\n");
607 return -EBUSY;
608 }
77ffc146
MR		 609 } while (!(val & PADS_PLL_CTL_LOCKDET));
610
611 /* turn off IDDQ override */
612 val = pads_readl(PADS_CTL) & ~PADS_CTL_IDDQ_1L;
613 pads_writel(val, PADS_CTL);
614
615 /* enable TX/RX data */
616 val = pads_readl(PADS_CTL);
617 val |= (PADS_CTL_TX_DATA_EN_1L | PADS_CTL_RX_DATA_EN_1L);
618 pads_writel(val, PADS_CTL);
619
620 /* Take the PCIe interface module out of reset */
621 tegra_periph_reset_deassert(tegra_pcie.pcie_xclk);
622
623 /* Finally enable PCIe */
624 val = afi_readl(AFI_CONFIGURATION) | AFI_CONFIGURATION_EN_FPCI;
625 afi_writel(val, AFI_CONFIGURATION);
626
627 val = (AFI_INTR_EN_INI_SLVERR | AFI_INTR_EN_INI_DECERR |
628 AFI_INTR_EN_TGT_SLVERR | AFI_INTR_EN_TGT_DECERR |
629 AFI_INTR_EN_TGT_WRERR | AFI_INTR_EN_DFPCI_DECERR);
630 afi_writel(val, AFI_AFI_INTR_ENABLE);
631 afi_writel(0xffffffff, AFI_SM_INTR_ENABLE);
632
633 /* FIXME: No MSI for now, only INT */
634 afi_writel(AFI_INTR_MASK_INT_MASK, AFI_INTR_MASK);
635
636 /* Disable all execptions */
637 afi_writel(0, AFI_FPCI_ERROR_MASKS);
638
2f926eec 639 return 0;
77ffc146
MR		 640}
641
642static void tegra_pcie_xclk_clamp(bool clamp)
643{
644 u32 reg;
645
646 reg = pmc_readl(PMC_SCRATCH42) & ~PMC_SCRATCH42_PCX_CLAMP;
647
648 if (clamp)
649 reg |= PMC_SCRATCH42_PCX_CLAMP;
650
651 pmc_writel(reg, PMC_SCRATCH42);
652}
653
1e40a97e
MR		 654static void tegra_pcie_power_off(void)
655{
656 tegra_periph_reset_assert(tegra_pcie.pcie_xclk);
657 tegra_periph_reset_assert(tegra_pcie.afi_clk);
658 tegra_periph_reset_assert(tegra_pcie.pex_clk);
659
b96cc7fe 660 tegra_powergate_power_off(TEGRA_POWERGATE_PCIE);
1e40a97e
MR		 661 tegra_pcie_xclk_clamp(true);
662}
663
b96cc7fe 664static int tegra_pcie_power_regate(void)
77ffc146 665{
b96cc7fe
MR		 666 int err;
667
668 tegra_pcie_power_off();
669
77ffc146 670 tegra_pcie_xclk_clamp(true);
b96cc7fe 671
77ffc146 672 tegra_periph_reset_assert(tegra_pcie.pcie_xclk);
b96cc7fe
MR		 673 tegra_periph_reset_assert(tegra_pcie.afi_clk);
674
675 err = tegra_powergate_sequence_power_up(TEGRA_POWERGATE_PCIE,
676 tegra_pcie.pex_clk);
677 if (err) {
678 pr_err("PCIE: powerup sequence failed: %d\n", err);
679 return err;
680 }
681
682 tegra_periph_reset_deassert(tegra_pcie.afi_clk);
683
77ffc146
MR		 684 tegra_pcie_xclk_clamp(false);
685
6a5278d0
PG		 686 clk_prepare_enable(tegra_pcie.afi_clk);
687 clk_prepare_enable(tegra_pcie.pex_clk);
688 return clk_prepare_enable(tegra_pcie.pll_e);
77ffc146
MR		 689}
690
77ffc146
MR		 691static int tegra_pcie_clocks_get(void)
692{
693 int err;
694
695 tegra_pcie.pex_clk = clk_get(NULL, "pex");
696 if (IS_ERR(tegra_pcie.pex_clk))
697 return PTR_ERR(tegra_pcie.pex_clk);
698
699 tegra_pcie.afi_clk = clk_get(NULL, "afi");
700 if (IS_ERR(tegra_pcie.afi_clk)) {
701 err = PTR_ERR(tegra_pcie.afi_clk);
702 goto err_afi_clk;
703 }
704
705 tegra_pcie.pcie_xclk = clk_get(NULL, "pcie_xclk");
706 if (IS_ERR(tegra_pcie.pcie_xclk)) {
707 err = PTR_ERR(tegra_pcie.pcie_xclk);
708 goto err_pcie_xclk;
709 }
710
711 tegra_pcie.pll_e = clk_get_sys(NULL, "pll_e");
712 if (IS_ERR(tegra_pcie.pll_e)) {
713 err = PTR_ERR(tegra_pcie.pll_e);
714 goto err_pll_e;
715 }
716
717 return 0;
718
719err_pll_e:
720 clk_put(tegra_pcie.pcie_xclk);
721err_pcie_xclk:
722 clk_put(tegra_pcie.afi_clk);
723err_afi_clk:
724 clk_put(tegra_pcie.pex_clk);
725
726 return err;
727}
728
729static void tegra_pcie_clocks_put(void)
730{
731 clk_put(tegra_pcie.pll_e);
732 clk_put(tegra_pcie.pcie_xclk);
733 clk_put(tegra_pcie.afi_clk);
734 clk_put(tegra_pcie.pex_clk);
735}
736
737static int __init tegra_pcie_get_resources(void)
738{
77ffc146
MR		 739 int err;
740
741 err = tegra_pcie_clocks_get();
742 if (err) {
743 pr_err("PCIE: failed to get clocks: %d\n", err);
744 return err;
745 }
746
b96cc7fe 747 err = tegra_pcie_power_regate();
77ffc146
MR		 748 if (err) {
749 pr_err("PCIE: failed to power up: %d\n", err);
750 goto err_pwr_on;
751 }
752
753 tegra_pcie.regs = ioremap_nocache(TEGRA_PCIE_BASE, PCIE_IOMAP_SZ);
754 if (tegra_pcie.regs == NULL) {
755 pr_err("PCIE: Failed to map PCI/AFI registers\n");
756 err = -ENOMEM;
757 goto err_map_reg;
758 }
759
77ffc146
MR		 760 err = request_irq(INT_PCIE_INTR, tegra_pcie_isr,
761 IRQF_SHARED, "PCIE", &tegra_pcie);
762 if (err) {
763 pr_err("PCIE: Failed to register IRQ: %d\n", err);
d94c7a04 764 goto err_req_io;
77ffc146
MR		 765 }
766 set_irq_flags(INT_PCIE_INTR, IRQF_VALID);
767
768 return 0;
769
77ffc146
MR		 770err_req_io:
771 iounmap(tegra_pcie.regs);
772err_map_reg:
773 tegra_pcie_power_off();
774err_pwr_on:
775 tegra_pcie_clocks_put();
776
777 return err;
778}
779
780/*
781 * FIXME: If there are no PCIe cards attached, then calling this function
782 * can result in the increase of the bootup time as there are big timeout
783 * loops.
784 */
785#define TEGRA_PCIE_LINKUP_TIMEOUT 200 /* up to 1.2 seconds */
786static bool tegra_pcie_check_link(struct tegra_pcie_port *pp, int idx,
787 u32 reset_reg)
788{
789 u32 reg;
790 int retries = 3;
791 int timeout;
792
793 do {
794 timeout = TEGRA_PCIE_LINKUP_TIMEOUT;
795 while (timeout) {
796 reg = readl(pp->base + RP_VEND_XP);
797
798 if (reg & RP_VEND_XP_DL_UP)
799 break;
800
801 mdelay(1);
802 timeout--;
803 }
804
805 if (!timeout) {
806 pr_err("PCIE: port %d: link down, retrying\n", idx);
807 goto retry;
808 }
809
810 timeout = TEGRA_PCIE_LINKUP_TIMEOUT;
811 while (timeout) {
812 reg = readl(pp->base + RP_LINK_CONTROL_STATUS);
813
814 if (reg & 0x20000000)
815 return true;
816
817 mdelay(1);
818 timeout--;
819 }
820
821retry:
822 /* Pulse the PEX reset */
823 reg = afi_readl(reset_reg) | AFI_PEX_CTRL_RST;
824 afi_writel(reg, reset_reg);
825 mdelay(1);
826 reg = afi_readl(reset_reg) & ~AFI_PEX_CTRL_RST;
827 afi_writel(reg, reset_reg);
828
829 retries--;
830 } while (retries);
831
832 return false;
833}
834
835static void __init tegra_pcie_add_port(int index, u32 offset, u32 reset_reg)
836{
837 struct tegra_pcie_port *pp;
838
839 pp = tegra_pcie.port + tegra_pcie.num_ports;
840
841 pp->index = -1;
842 pp->base = tegra_pcie.regs + offset;
843 pp->link_up = tegra_pcie_check_link(pp, index, reset_reg);
844
845 if (!pp->link_up) {
846 pp->base = NULL;
847 printk(KERN_INFO "PCIE: port %d: link down, ignoring\n", index);
848 return;
849 }
850
851 tegra_pcie.num_ports++;
852 pp->index = index;
853 pp->root_bus_nr = -1;
854 memset(pp->res, 0, sizeof(pp->res));
855}
856
857int __init tegra_pcie_init(bool init_port0, bool init_port1)
858{
859 int err;
860
861 if (!(init_port0 || init_port1))
862 return -ENODEV;
863
c9d95fbe
RH		 864 pcibios_min_mem = 0;
865
77ffc146
MR		 866 err = tegra_pcie_get_resources();
867 if (err)
868 return err;
869
795d5fd4
DA		 870 err = tegra_pcie_enable_controller();
871 if (err)
872 return err;
77ffc146
MR		 873
874 /* setup the AFI address translations */
875 tegra_pcie_setup_translations();
876
877 if (init_port0)
878 tegra_pcie_add_port(0, RP0_OFFSET, AFI_PEX0_CTRL);
879
880 if (init_port1)
881 tegra_pcie_add_port(1, RP1_OFFSET, AFI_PEX1_CTRL);
882
883 pci_common_init(&tegra_pcie_hw);
884
885 return 0;
886}
Linux kernel - Deliverables
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