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77ffc146 MR |
1 | /* |
2 | * arch/arm/mach-tegra/pci.c | |
3 | * | |
4 | * PCIe host controller driver for TEGRA(2) SOCs | |
5 | * | |
6 | * Copyright (c) 2010, CompuLab, Ltd. | |
7 | * Author: Mike Rapoport <mike@compulab.co.il> | |
8 | * | |
9 | * Based on NVIDIA PCIe driver | |
10 | * Copyright (c) 2008-2009, NVIDIA Corporation. | |
11 | * | |
12 | * Bits taken from arch/arm/mach-dove/pcie.c | |
13 | * | |
14 | * This program is free software; you can redistribute it and/or modify | |
15 | * it under the terms of the GNU General Public License as published by | |
16 | * the Free Software Foundation; either version 2 of the License, or | |
17 | * (at your option) any later version. | |
18 | * | |
19 | * This program is distributed in the hope that it will be useful, but WITHOUT | |
20 | * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or | |
21 | * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for | |
22 | * more details. | |
23 | * | |
24 | * You should have received a copy of the GNU General Public License along | |
25 | * with this program; if not, write to the Free Software Foundation, Inc., | |
26 | * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA. | |
27 | */ | |
28 | ||
29 | #include <linux/kernel.h> | |
30 | #include <linux/pci.h> | |
31 | #include <linux/interrupt.h> | |
32 | #include <linux/irq.h> | |
33 | #include <linux/clk.h> | |
34 | #include <linux/delay.h> | |
35 | ||
36 | #include <asm/sizes.h> | |
37 | #include <asm/mach/pci.h> | |
38 | ||
39 | #include <mach/pinmux.h> | |
40 | #include <mach/iomap.h> | |
41 | #include <mach/clk.h> | |
b96cc7fe | 42 | #include <mach/powergate.h> |
77ffc146 MR |
43 | |
44 | /* register definitions */ | |
45 | #define AFI_OFFSET 0x3800 | |
46 | #define PADS_OFFSET 0x3000 | |
47 | #define RP0_OFFSET 0x0000 | |
48 | #define RP1_OFFSET 0x1000 | |
49 | ||
50 | #define AFI_AXI_BAR0_SZ 0x00 | |
51 | #define AFI_AXI_BAR1_SZ 0x04 | |
52 | #define AFI_AXI_BAR2_SZ 0x08 | |
53 | #define AFI_AXI_BAR3_SZ 0x0c | |
54 | #define AFI_AXI_BAR4_SZ 0x10 | |
55 | #define AFI_AXI_BAR5_SZ 0x14 | |
56 | ||
57 | #define AFI_AXI_BAR0_START 0x18 | |
58 | #define AFI_AXI_BAR1_START 0x1c | |
59 | #define AFI_AXI_BAR2_START 0x20 | |
60 | #define AFI_AXI_BAR3_START 0x24 | |
61 | #define AFI_AXI_BAR4_START 0x28 | |
62 | #define AFI_AXI_BAR5_START 0x2c | |
63 | ||
64 | #define AFI_FPCI_BAR0 0x30 | |
65 | #define AFI_FPCI_BAR1 0x34 | |
66 | #define AFI_FPCI_BAR2 0x38 | |
67 | #define AFI_FPCI_BAR3 0x3c | |
68 | #define AFI_FPCI_BAR4 0x40 | |
69 | #define AFI_FPCI_BAR5 0x44 | |
70 | ||
71 | #define AFI_CACHE_BAR0_SZ 0x48 | |
72 | #define AFI_CACHE_BAR0_ST 0x4c | |
73 | #define AFI_CACHE_BAR1_SZ 0x50 | |
74 | #define AFI_CACHE_BAR1_ST 0x54 | |
75 | ||
76 | #define AFI_MSI_BAR_SZ 0x60 | |
77 | #define AFI_MSI_FPCI_BAR_ST 0x64 | |
78 | #define AFI_MSI_AXI_BAR_ST 0x68 | |
79 | ||
80 | #define AFI_CONFIGURATION 0xac | |
81 | #define AFI_CONFIGURATION_EN_FPCI (1 << 0) | |
82 | ||
83 | #define AFI_FPCI_ERROR_MASKS 0xb0 | |
84 | ||
85 | #define AFI_INTR_MASK 0xb4 | |
86 | #define AFI_INTR_MASK_INT_MASK (1 << 0) | |
87 | #define AFI_INTR_MASK_MSI_MASK (1 << 8) | |
88 | ||
89 | #define AFI_INTR_CODE 0xb8 | |
90 | #define AFI_INTR_CODE_MASK 0xf | |
91 | #define AFI_INTR_MASTER_ABORT 4 | |
92 | #define AFI_INTR_LEGACY 6 | |
93 | ||
94 | #define AFI_INTR_SIGNATURE 0xbc | |
95 | #define AFI_SM_INTR_ENABLE 0xc4 | |
96 | ||
97 | #define AFI_AFI_INTR_ENABLE 0xc8 | |
98 | #define AFI_INTR_EN_INI_SLVERR (1 << 0) | |
99 | #define AFI_INTR_EN_INI_DECERR (1 << 1) | |
100 | #define AFI_INTR_EN_TGT_SLVERR (1 << 2) | |
101 | #define AFI_INTR_EN_TGT_DECERR (1 << 3) | |
102 | #define AFI_INTR_EN_TGT_WRERR (1 << 4) | |
103 | #define AFI_INTR_EN_DFPCI_DECERR (1 << 5) | |
104 | #define AFI_INTR_EN_AXI_DECERR (1 << 6) | |
105 | #define AFI_INTR_EN_FPCI_TIMEOUT (1 << 7) | |
106 | ||
107 | #define AFI_PCIE_CONFIG 0x0f8 | |
108 | #define AFI_PCIE_CONFIG_PCIEC0_DISABLE_DEVICE (1 << 1) | |
109 | #define AFI_PCIE_CONFIG_PCIEC1_DISABLE_DEVICE (1 << 2) | |
110 | #define AFI_PCIE_CONFIG_SM2TMS0_XBAR_CONFIG_MASK (0xf << 20) | |
111 | #define AFI_PCIE_CONFIG_SM2TMS0_XBAR_CONFIG_SINGLE (0x0 << 20) | |
112 | #define AFI_PCIE_CONFIG_SM2TMS0_XBAR_CONFIG_DUAL (0x1 << 20) | |
113 | ||
114 | #define AFI_FUSE 0x104 | |
115 | #define AFI_FUSE_PCIE_T0_GEN2_DIS (1 << 2) | |
116 | ||
117 | #define AFI_PEX0_CTRL 0x110 | |
118 | #define AFI_PEX1_CTRL 0x118 | |
119 | #define AFI_PEX_CTRL_RST (1 << 0) | |
120 | #define AFI_PEX_CTRL_REFCLK_EN (1 << 3) | |
121 | ||
122 | #define RP_VEND_XP 0x00000F00 | |
123 | #define RP_VEND_XP_DL_UP (1 << 30) | |
124 | ||
125 | #define RP_LINK_CONTROL_STATUS 0x00000090 | |
126 | #define RP_LINK_CONTROL_STATUS_LINKSTAT_MASK 0x3fff0000 | |
127 | ||
128 | #define PADS_CTL_SEL 0x0000009C | |
129 | ||
130 | #define PADS_CTL 0x000000A0 | |
131 | #define PADS_CTL_IDDQ_1L (1 << 0) | |
132 | #define PADS_CTL_TX_DATA_EN_1L (1 << 6) | |
133 | #define PADS_CTL_RX_DATA_EN_1L (1 << 10) | |
134 | ||
135 | #define PADS_PLL_CTL 0x000000B8 | |
136 | #define PADS_PLL_CTL_RST_B4SM (1 << 1) | |
137 | #define PADS_PLL_CTL_LOCKDET (1 << 8) | |
138 | #define PADS_PLL_CTL_REFCLK_MASK (0x3 << 16) | |
139 | #define PADS_PLL_CTL_REFCLK_INTERNAL_CML (0 << 16) | |
140 | #define PADS_PLL_CTL_REFCLK_INTERNAL_CMOS (1 << 16) | |
141 | #define PADS_PLL_CTL_REFCLK_EXTERNAL (2 << 16) | |
142 | #define PADS_PLL_CTL_TXCLKREF_MASK (0x1 << 20) | |
143 | #define PADS_PLL_CTL_TXCLKREF_DIV10 (0 << 20) | |
144 | #define PADS_PLL_CTL_TXCLKREF_DIV5 (1 << 20) | |
145 | ||
146 | /* PMC access is required for PCIE xclk (un)clamping */ | |
147 | #define PMC_SCRATCH42 0x144 | |
148 | #define PMC_SCRATCH42_PCX_CLAMP (1 << 0) | |
149 | ||
150 | static void __iomem *reg_pmc_base = IO_ADDRESS(TEGRA_PMC_BASE); | |
151 | ||
152 | #define pmc_writel(value, reg) \ | |
153 | __raw_writel(value, (u32)reg_pmc_base + (reg)) | |
154 | #define pmc_readl(reg) \ | |
155 | __raw_readl((u32)reg_pmc_base + (reg)) | |
156 | ||
157 | /* | |
158 | * Tegra2 defines 1GB in the AXI address map for PCIe. | |
159 | * | |
160 | * That address space is split into different regions, with sizes and | |
161 | * offsets as follows: | |
162 | * | |
163 | * 0x80000000 - 0x80003fff - PCI controller registers | |
164 | * 0x80004000 - 0x80103fff - PCI configuration space | |
165 | * 0x80104000 - 0x80203fff - PCI extended configuration space | |
166 | * 0x80203fff - 0x803fffff - unused | |
167 | * 0x80400000 - 0x8040ffff - downstream IO | |
168 | * 0x80410000 - 0x8fffffff - unused | |
169 | * 0x90000000 - 0x9fffffff - non-prefetchable memory | |
170 | * 0xa0000000 - 0xbfffffff - prefetchable memory | |
171 | */ | |
172 | #define TEGRA_PCIE_BASE 0x80000000 | |
173 | ||
174 | #define PCIE_REGS_SZ SZ_16K | |
175 | #define PCIE_CFG_OFF PCIE_REGS_SZ | |
176 | #define PCIE_CFG_SZ SZ_1M | |
177 | #define PCIE_EXT_CFG_OFF (PCIE_CFG_SZ + PCIE_CFG_OFF) | |
178 | #define PCIE_EXT_CFG_SZ SZ_1M | |
179 | #define PCIE_IOMAP_SZ (PCIE_REGS_SZ + PCIE_CFG_SZ + PCIE_EXT_CFG_SZ) | |
180 | ||
181 | #define MMIO_BASE (TEGRA_PCIE_BASE + SZ_4M) | |
182 | #define MMIO_SIZE SZ_64K | |
183 | #define MEM_BASE_0 (TEGRA_PCIE_BASE + SZ_256M) | |
184 | #define MEM_SIZE_0 SZ_128M | |
185 | #define MEM_BASE_1 (MEM_BASE_0 + MEM_SIZE_0) | |
186 | #define MEM_SIZE_1 SZ_128M | |
187 | #define PREFETCH_MEM_BASE_0 (MEM_BASE_1 + MEM_SIZE_1) | |
188 | #define PREFETCH_MEM_SIZE_0 SZ_128M | |
189 | #define PREFETCH_MEM_BASE_1 (PREFETCH_MEM_BASE_0 + PREFETCH_MEM_SIZE_0) | |
190 | #define PREFETCH_MEM_SIZE_1 SZ_128M | |
191 | ||
192 | #define PCIE_CONF_BUS(b) ((b) << 16) | |
193 | #define PCIE_CONF_DEV(d) ((d) << 11) | |
194 | #define PCIE_CONF_FUNC(f) ((f) << 8) | |
195 | #define PCIE_CONF_REG(r) \ | |
196 | (((r) & ~0x3) | (((r) < 256) ? PCIE_CFG_OFF : PCIE_EXT_CFG_OFF)) | |
197 | ||
198 | struct tegra_pcie_port { | |
199 | int index; | |
200 | u8 root_bus_nr; | |
201 | void __iomem *base; | |
202 | ||
203 | bool link_up; | |
204 | ||
205 | char io_space_name[16]; | |
206 | char mem_space_name[16]; | |
207 | char prefetch_space_name[20]; | |
208 | struct resource res[3]; | |
209 | }; | |
210 | ||
211 | struct tegra_pcie_info { | |
212 | struct tegra_pcie_port port[2]; | |
213 | int num_ports; | |
214 | ||
215 | void __iomem *regs; | |
216 | struct resource res_mmio; | |
217 | ||
218 | struct clk *pex_clk; | |
219 | struct clk *afi_clk; | |
220 | struct clk *pcie_xclk; | |
221 | struct clk *pll_e; | |
222 | }; | |
223 | ||
224 | static struct tegra_pcie_info tegra_pcie = { | |
225 | .res_mmio = { | |
226 | .name = "PCI IO", | |
227 | .start = MMIO_BASE, | |
228 | .end = MMIO_BASE + MMIO_SIZE - 1, | |
229 | .flags = IORESOURCE_MEM, | |
230 | }, | |
231 | }; | |
232 | ||
233 | void __iomem *tegra_pcie_io_base; | |
234 | EXPORT_SYMBOL(tegra_pcie_io_base); | |
235 | ||
236 | static inline void afi_writel(u32 value, unsigned long offset) | |
237 | { | |
238 | writel(value, offset + AFI_OFFSET + tegra_pcie.regs); | |
239 | } | |
240 | ||
241 | static inline u32 afi_readl(unsigned long offset) | |
242 | { | |
243 | return readl(offset + AFI_OFFSET + tegra_pcie.regs); | |
244 | } | |
245 | ||
246 | static inline void pads_writel(u32 value, unsigned long offset) | |
247 | { | |
248 | writel(value, offset + PADS_OFFSET + tegra_pcie.regs); | |
249 | } | |
250 | ||
251 | static inline u32 pads_readl(unsigned long offset) | |
252 | { | |
253 | return readl(offset + PADS_OFFSET + tegra_pcie.regs); | |
254 | } | |
255 | ||
256 | static struct tegra_pcie_port *bus_to_port(int bus) | |
257 | { | |
258 | int i; | |
259 | ||
260 | for (i = tegra_pcie.num_ports - 1; i >= 0; i--) { | |
261 | int rbus = tegra_pcie.port[i].root_bus_nr; | |
262 | if (rbus != -1 && rbus == bus) | |
263 | break; | |
264 | } | |
265 | ||
266 | return i >= 0 ? tegra_pcie.port + i : NULL; | |
267 | } | |
268 | ||
269 | static int tegra_pcie_read_conf(struct pci_bus *bus, unsigned int devfn, | |
270 | int where, int size, u32 *val) | |
271 | { | |
272 | struct tegra_pcie_port *pp = bus_to_port(bus->number); | |
273 | void __iomem *addr; | |
274 | ||
275 | if (pp) { | |
276 | if (devfn != 0) { | |
277 | *val = 0xffffffff; | |
278 | return PCIBIOS_DEVICE_NOT_FOUND; | |
279 | } | |
280 | ||
281 | addr = pp->base + (where & ~0x3); | |
282 | } else { | |
283 | addr = tegra_pcie.regs + (PCIE_CONF_BUS(bus->number) + | |
284 | PCIE_CONF_DEV(PCI_SLOT(devfn)) + | |
285 | PCIE_CONF_FUNC(PCI_FUNC(devfn)) + | |
286 | PCIE_CONF_REG(where)); | |
287 | } | |
288 | ||
289 | *val = readl(addr); | |
290 | ||
291 | if (size == 1) | |
292 | *val = (*val >> (8 * (where & 3))) & 0xff; | |
293 | else if (size == 2) | |
294 | *val = (*val >> (8 * (where & 3))) & 0xffff; | |
295 | ||
296 | return PCIBIOS_SUCCESSFUL; | |
297 | } | |
298 | ||
299 | static int tegra_pcie_write_conf(struct pci_bus *bus, unsigned int devfn, | |
300 | int where, int size, u32 val) | |
301 | { | |
302 | struct tegra_pcie_port *pp = bus_to_port(bus->number); | |
303 | void __iomem *addr; | |
304 | ||
305 | u32 mask; | |
306 | u32 tmp; | |
307 | ||
308 | if (pp) { | |
309 | if (devfn != 0) | |
310 | return PCIBIOS_DEVICE_NOT_FOUND; | |
311 | ||
312 | addr = pp->base + (where & ~0x3); | |
313 | } else { | |
314 | addr = tegra_pcie.regs + (PCIE_CONF_BUS(bus->number) + | |
315 | PCIE_CONF_DEV(PCI_SLOT(devfn)) + | |
316 | PCIE_CONF_FUNC(PCI_FUNC(devfn)) + | |
317 | PCIE_CONF_REG(where)); | |
318 | } | |
319 | ||
320 | if (size == 4) { | |
321 | writel(val, addr); | |
322 | return PCIBIOS_SUCCESSFUL; | |
323 | } | |
324 | ||
325 | if (size == 2) | |
326 | mask = ~(0xffff << ((where & 0x3) * 8)); | |
327 | else if (size == 1) | |
328 | mask = ~(0xff << ((where & 0x3) * 8)); | |
329 | else | |
330 | return PCIBIOS_BAD_REGISTER_NUMBER; | |
331 | ||
332 | tmp = readl(addr) & mask; | |
333 | tmp |= val << ((where & 0x3) * 8); | |
334 | writel(tmp, addr); | |
335 | ||
336 | return PCIBIOS_SUCCESSFUL; | |
337 | } | |
338 | ||
339 | static struct pci_ops tegra_pcie_ops = { | |
340 | .read = tegra_pcie_read_conf, | |
341 | .write = tegra_pcie_write_conf, | |
342 | }; | |
343 | ||
344 | static void __devinit tegra_pcie_fixup_bridge(struct pci_dev *dev) | |
345 | { | |
346 | u16 reg; | |
347 | ||
348 | if ((dev->class >> 16) == PCI_BASE_CLASS_BRIDGE) { | |
349 | pci_read_config_word(dev, PCI_COMMAND, ®); | |
350 | reg |= (PCI_COMMAND_IO | PCI_COMMAND_MEMORY | | |
351 | PCI_COMMAND_MASTER | PCI_COMMAND_SERR); | |
352 | pci_write_config_word(dev, PCI_COMMAND, reg); | |
353 | } | |
354 | } | |
355 | DECLARE_PCI_FIXUP_FINAL(PCI_ANY_ID, PCI_ANY_ID, tegra_pcie_fixup_bridge); | |
356 | ||
357 | /* Tegra PCIE root complex wrongly reports device class */ | |
358 | static void __devinit tegra_pcie_fixup_class(struct pci_dev *dev) | |
359 | { | |
360 | dev->class = PCI_CLASS_BRIDGE_PCI << 8; | |
361 | } | |
362 | DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_NVIDIA, 0x0bf0, tegra_pcie_fixup_class); | |
363 | DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_NVIDIA, 0x0bf1, tegra_pcie_fixup_class); | |
364 | ||
365 | /* Tegra PCIE requires relaxed ordering */ | |
366 | static void __devinit tegra_pcie_relax_enable(struct pci_dev *dev) | |
367 | { | |
368 | u16 val16; | |
369 | int pos = pci_find_capability(dev, PCI_CAP_ID_EXP); | |
370 | ||
371 | if (pos <= 0) { | |
372 | dev_err(&dev->dev, "skipping relaxed ordering fixup\n"); | |
373 | return; | |
374 | } | |
375 | ||
376 | pci_read_config_word(dev, pos + PCI_EXP_DEVCTL, &val16); | |
377 | val16 |= PCI_EXP_DEVCTL_RELAX_EN; | |
378 | pci_write_config_word(dev, pos + PCI_EXP_DEVCTL, val16); | |
379 | } | |
380 | DECLARE_PCI_FIXUP_FINAL(PCI_ANY_ID, PCI_ANY_ID, tegra_pcie_relax_enable); | |
381 | ||
382 | static int tegra_pcie_setup(int nr, struct pci_sys_data *sys) | |
383 | { | |
384 | struct tegra_pcie_port *pp; | |
385 | ||
386 | if (nr >= tegra_pcie.num_ports) | |
387 | return 0; | |
388 | ||
389 | pp = tegra_pcie.port + nr; | |
390 | pp->root_bus_nr = sys->busnr; | |
391 | ||
392 | /* | |
393 | * IORESOURCE_IO | |
394 | */ | |
395 | snprintf(pp->io_space_name, sizeof(pp->io_space_name), | |
396 | "PCIe %d I/O", pp->index); | |
397 | pp->io_space_name[sizeof(pp->io_space_name) - 1] = 0; | |
398 | pp->res[0].name = pp->io_space_name; | |
399 | if (pp->index == 0) { | |
400 | pp->res[0].start = PCIBIOS_MIN_IO; | |
401 | pp->res[0].end = pp->res[0].start + SZ_32K - 1; | |
402 | } else { | |
403 | pp->res[0].start = PCIBIOS_MIN_IO + SZ_32K; | |
404 | pp->res[0].end = IO_SPACE_LIMIT; | |
405 | } | |
406 | pp->res[0].flags = IORESOURCE_IO; | |
407 | if (request_resource(&ioport_resource, &pp->res[0])) | |
408 | panic("Request PCIe IO resource failed\n"); | |
409 | sys->resource[0] = &pp->res[0]; | |
410 | ||
411 | /* | |
412 | * IORESOURCE_MEM | |
413 | */ | |
414 | snprintf(pp->mem_space_name, sizeof(pp->mem_space_name), | |
415 | "PCIe %d MEM", pp->index); | |
416 | pp->mem_space_name[sizeof(pp->mem_space_name) - 1] = 0; | |
417 | pp->res[1].name = pp->mem_space_name; | |
418 | if (pp->index == 0) { | |
419 | pp->res[1].start = MEM_BASE_0; | |
420 | pp->res[1].end = pp->res[1].start + MEM_SIZE_0 - 1; | |
421 | } else { | |
422 | pp->res[1].start = MEM_BASE_1; | |
423 | pp->res[1].end = pp->res[1].start + MEM_SIZE_1 - 1; | |
424 | } | |
425 | pp->res[1].flags = IORESOURCE_MEM; | |
426 | if (request_resource(&iomem_resource, &pp->res[1])) | |
427 | panic("Request PCIe Memory resource failed\n"); | |
428 | sys->resource[1] = &pp->res[1]; | |
429 | ||
430 | /* | |
431 | * IORESOURCE_MEM | IORESOURCE_PREFETCH | |
432 | */ | |
433 | snprintf(pp->prefetch_space_name, sizeof(pp->prefetch_space_name), | |
434 | "PCIe %d PREFETCH MEM", pp->index); | |
435 | pp->prefetch_space_name[sizeof(pp->prefetch_space_name) - 1] = 0; | |
436 | pp->res[2].name = pp->prefetch_space_name; | |
437 | if (pp->index == 0) { | |
438 | pp->res[2].start = PREFETCH_MEM_BASE_0; | |
439 | pp->res[2].end = pp->res[2].start + PREFETCH_MEM_SIZE_0 - 1; | |
440 | } else { | |
441 | pp->res[2].start = PREFETCH_MEM_BASE_1; | |
442 | pp->res[2].end = pp->res[2].start + PREFETCH_MEM_SIZE_1 - 1; | |
443 | } | |
444 | pp->res[2].flags = IORESOURCE_MEM | IORESOURCE_PREFETCH; | |
445 | if (request_resource(&iomem_resource, &pp->res[2])) | |
446 | panic("Request PCIe Prefetch Memory resource failed\n"); | |
447 | sys->resource[2] = &pp->res[2]; | |
448 | ||
449 | return 1; | |
450 | } | |
451 | ||
d5341942 | 452 | static int tegra_pcie_map_irq(const struct pci_dev *dev, u8 slot, u8 pin) |
77ffc146 MR |
453 | { |
454 | return INT_PCIE_INTR; | |
455 | } | |
456 | ||
457 | static struct pci_bus __init *tegra_pcie_scan_bus(int nr, | |
458 | struct pci_sys_data *sys) | |
459 | { | |
460 | struct tegra_pcie_port *pp; | |
461 | ||
462 | if (nr >= tegra_pcie.num_ports) | |
463 | return 0; | |
464 | ||
465 | pp = tegra_pcie.port + nr; | |
466 | pp->root_bus_nr = sys->busnr; | |
467 | ||
468 | return pci_scan_bus(sys->busnr, &tegra_pcie_ops, sys); | |
469 | } | |
470 | ||
471 | static struct hw_pci tegra_pcie_hw __initdata = { | |
472 | .nr_controllers = 2, | |
473 | .setup = tegra_pcie_setup, | |
474 | .scan = tegra_pcie_scan_bus, | |
475 | .swizzle = pci_std_swizzle, | |
476 | .map_irq = tegra_pcie_map_irq, | |
477 | }; | |
478 | ||
479 | ||
480 | static irqreturn_t tegra_pcie_isr(int irq, void *arg) | |
481 | { | |
482 | const char *err_msg[] = { | |
483 | "Unknown", | |
484 | "AXI slave error", | |
485 | "AXI decode error", | |
486 | "Target abort", | |
487 | "Master abort", | |
488 | "Invalid write", | |
489 | "Response decoding error", | |
490 | "AXI response decoding error", | |
491 | "Transcation timeout", | |
492 | }; | |
493 | ||
494 | u32 code, signature; | |
495 | ||
496 | code = afi_readl(AFI_INTR_CODE) & AFI_INTR_CODE_MASK; | |
497 | signature = afi_readl(AFI_INTR_SIGNATURE); | |
498 | afi_writel(0, AFI_INTR_CODE); | |
499 | ||
500 | if (code == AFI_INTR_LEGACY) | |
501 | return IRQ_NONE; | |
502 | ||
503 | if (code >= ARRAY_SIZE(err_msg)) | |
504 | code = 0; | |
505 | ||
506 | /* | |
507 | * do not pollute kernel log with master abort reports since they | |
508 | * happen a lot during enumeration | |
509 | */ | |
510 | if (code == AFI_INTR_MASTER_ABORT) | |
511 | pr_debug("PCIE: %s, signature: %08x\n", err_msg[code], signature); | |
512 | else | |
513 | pr_err("PCIE: %s, signature: %08x\n", err_msg[code], signature); | |
514 | ||
515 | return IRQ_HANDLED; | |
516 | } | |
517 | ||
518 | static void tegra_pcie_setup_translations(void) | |
519 | { | |
520 | u32 fpci_bar; | |
521 | u32 size; | |
522 | u32 axi_address; | |
523 | ||
524 | /* Bar 0: config Bar */ | |
525 | fpci_bar = ((u32)0xfdff << 16); | |
526 | size = PCIE_CFG_SZ; | |
527 | axi_address = TEGRA_PCIE_BASE + PCIE_CFG_OFF; | |
528 | afi_writel(axi_address, AFI_AXI_BAR0_START); | |
529 | afi_writel(size >> 12, AFI_AXI_BAR0_SZ); | |
530 | afi_writel(fpci_bar, AFI_FPCI_BAR0); | |
531 | ||
532 | /* Bar 1: extended config Bar */ | |
533 | fpci_bar = ((u32)0xfe1 << 20); | |
534 | size = PCIE_EXT_CFG_SZ; | |
535 | axi_address = TEGRA_PCIE_BASE + PCIE_EXT_CFG_OFF; | |
536 | afi_writel(axi_address, AFI_AXI_BAR1_START); | |
537 | afi_writel(size >> 12, AFI_AXI_BAR1_SZ); | |
538 | afi_writel(fpci_bar, AFI_FPCI_BAR1); | |
539 | ||
540 | /* Bar 2: downstream IO bar */ | |
541 | fpci_bar = ((__u32)0xfdfc << 16); | |
542 | size = MMIO_SIZE; | |
543 | axi_address = MMIO_BASE; | |
544 | afi_writel(axi_address, AFI_AXI_BAR2_START); | |
545 | afi_writel(size >> 12, AFI_AXI_BAR2_SZ); | |
546 | afi_writel(fpci_bar, AFI_FPCI_BAR2); | |
547 | ||
548 | /* Bar 3: prefetchable memory BAR */ | |
549 | fpci_bar = (((PREFETCH_MEM_BASE_0 >> 12) & 0x0fffffff) << 4) | 0x1; | |
550 | size = PREFETCH_MEM_SIZE_0 + PREFETCH_MEM_SIZE_1; | |
551 | axi_address = PREFETCH_MEM_BASE_0; | |
552 | afi_writel(axi_address, AFI_AXI_BAR3_START); | |
553 | afi_writel(size >> 12, AFI_AXI_BAR3_SZ); | |
554 | afi_writel(fpci_bar, AFI_FPCI_BAR3); | |
555 | ||
556 | /* Bar 4: non prefetchable memory BAR */ | |
557 | fpci_bar = (((MEM_BASE_0 >> 12) & 0x0FFFFFFF) << 4) | 0x1; | |
558 | size = MEM_SIZE_0 + MEM_SIZE_1; | |
559 | axi_address = MEM_BASE_0; | |
560 | afi_writel(axi_address, AFI_AXI_BAR4_START); | |
561 | afi_writel(size >> 12, AFI_AXI_BAR4_SZ); | |
562 | afi_writel(fpci_bar, AFI_FPCI_BAR4); | |
563 | ||
564 | /* Bar 5: NULL out the remaining BAR as it is not used */ | |
565 | fpci_bar = 0; | |
566 | size = 0; | |
567 | axi_address = 0; | |
568 | afi_writel(axi_address, AFI_AXI_BAR5_START); | |
569 | afi_writel(size >> 12, AFI_AXI_BAR5_SZ); | |
570 | afi_writel(fpci_bar, AFI_FPCI_BAR5); | |
571 | ||
572 | /* map all upstream transactions as uncached */ | |
573 | afi_writel(PHYS_OFFSET, AFI_CACHE_BAR0_ST); | |
574 | afi_writel(0, AFI_CACHE_BAR0_SZ); | |
575 | afi_writel(0, AFI_CACHE_BAR1_ST); | |
576 | afi_writel(0, AFI_CACHE_BAR1_SZ); | |
577 | ||
578 | /* No MSI */ | |
579 | afi_writel(0, AFI_MSI_FPCI_BAR_ST); | |
580 | afi_writel(0, AFI_MSI_BAR_SZ); | |
581 | afi_writel(0, AFI_MSI_AXI_BAR_ST); | |
582 | afi_writel(0, AFI_MSI_BAR_SZ); | |
583 | } | |
584 | ||
585 | static void tegra_pcie_enable_controller(void) | |
586 | { | |
587 | u32 val, reg; | |
588 | int i; | |
589 | ||
590 | /* Enable slot clock and pulse the reset signals */ | |
591 | for (i = 0, reg = AFI_PEX0_CTRL; i < 2; i++, reg += 0x8) { | |
592 | val = afi_readl(reg) | AFI_PEX_CTRL_REFCLK_EN; | |
593 | afi_writel(val, reg); | |
594 | val &= ~AFI_PEX_CTRL_RST; | |
595 | afi_writel(val, reg); | |
596 | ||
597 | val = afi_readl(reg) | AFI_PEX_CTRL_RST; | |
598 | afi_writel(val, reg); | |
599 | } | |
600 | ||
601 | /* Enable dual controller and both ports */ | |
602 | val = afi_readl(AFI_PCIE_CONFIG); | |
603 | val &= ~(AFI_PCIE_CONFIG_PCIEC0_DISABLE_DEVICE | | |
604 | AFI_PCIE_CONFIG_PCIEC1_DISABLE_DEVICE | | |
605 | AFI_PCIE_CONFIG_SM2TMS0_XBAR_CONFIG_MASK); | |
606 | val |= AFI_PCIE_CONFIG_SM2TMS0_XBAR_CONFIG_DUAL; | |
607 | afi_writel(val, AFI_PCIE_CONFIG); | |
608 | ||
609 | val = afi_readl(AFI_FUSE) & ~AFI_FUSE_PCIE_T0_GEN2_DIS; | |
610 | afi_writel(val, AFI_FUSE); | |
611 | ||
612 | /* Initialze internal PHY, enable up to 16 PCIE lanes */ | |
613 | pads_writel(0x0, PADS_CTL_SEL); | |
614 | ||
615 | /* override IDDQ to 1 on all 4 lanes */ | |
616 | val = pads_readl(PADS_CTL) | PADS_CTL_IDDQ_1L; | |
617 | pads_writel(val, PADS_CTL); | |
618 | ||
619 | /* | |
620 | * set up PHY PLL inputs select PLLE output as refclock, | |
621 | * set TX ref sel to div10 (not div5) | |
622 | */ | |
623 | val = pads_readl(PADS_PLL_CTL); | |
624 | val &= ~(PADS_PLL_CTL_REFCLK_MASK | PADS_PLL_CTL_TXCLKREF_MASK); | |
625 | val |= (PADS_PLL_CTL_REFCLK_INTERNAL_CML | PADS_PLL_CTL_TXCLKREF_DIV10); | |
626 | pads_writel(val, PADS_PLL_CTL); | |
627 | ||
628 | /* take PLL out of reset */ | |
629 | val = pads_readl(PADS_PLL_CTL) | PADS_PLL_CTL_RST_B4SM; | |
630 | pads_writel(val, PADS_PLL_CTL); | |
631 | ||
632 | /* | |
633 | * Hack, set the clock voltage to the DEFAULT provided by hw folks. | |
634 | * This doesn't exist in the documentation | |
635 | */ | |
636 | pads_writel(0xfa5cfa5c, 0xc8); | |
637 | ||
638 | /* Wait for the PLL to lock */ | |
639 | do { | |
640 | val = pads_readl(PADS_PLL_CTL); | |
641 | } while (!(val & PADS_PLL_CTL_LOCKDET)); | |
642 | ||
643 | /* turn off IDDQ override */ | |
644 | val = pads_readl(PADS_CTL) & ~PADS_CTL_IDDQ_1L; | |
645 | pads_writel(val, PADS_CTL); | |
646 | ||
647 | /* enable TX/RX data */ | |
648 | val = pads_readl(PADS_CTL); | |
649 | val |= (PADS_CTL_TX_DATA_EN_1L | PADS_CTL_RX_DATA_EN_1L); | |
650 | pads_writel(val, PADS_CTL); | |
651 | ||
652 | /* Take the PCIe interface module out of reset */ | |
653 | tegra_periph_reset_deassert(tegra_pcie.pcie_xclk); | |
654 | ||
655 | /* Finally enable PCIe */ | |
656 | val = afi_readl(AFI_CONFIGURATION) | AFI_CONFIGURATION_EN_FPCI; | |
657 | afi_writel(val, AFI_CONFIGURATION); | |
658 | ||
659 | val = (AFI_INTR_EN_INI_SLVERR | AFI_INTR_EN_INI_DECERR | | |
660 | AFI_INTR_EN_TGT_SLVERR | AFI_INTR_EN_TGT_DECERR | | |
661 | AFI_INTR_EN_TGT_WRERR | AFI_INTR_EN_DFPCI_DECERR); | |
662 | afi_writel(val, AFI_AFI_INTR_ENABLE); | |
663 | afi_writel(0xffffffff, AFI_SM_INTR_ENABLE); | |
664 | ||
665 | /* FIXME: No MSI for now, only INT */ | |
666 | afi_writel(AFI_INTR_MASK_INT_MASK, AFI_INTR_MASK); | |
667 | ||
668 | /* Disable all execptions */ | |
669 | afi_writel(0, AFI_FPCI_ERROR_MASKS); | |
670 | ||
671 | return; | |
672 | } | |
673 | ||
674 | static void tegra_pcie_xclk_clamp(bool clamp) | |
675 | { | |
676 | u32 reg; | |
677 | ||
678 | reg = pmc_readl(PMC_SCRATCH42) & ~PMC_SCRATCH42_PCX_CLAMP; | |
679 | ||
680 | if (clamp) | |
681 | reg |= PMC_SCRATCH42_PCX_CLAMP; | |
682 | ||
683 | pmc_writel(reg, PMC_SCRATCH42); | |
684 | } | |
685 | ||
1e40a97e MR |
686 | static void tegra_pcie_power_off(void) |
687 | { | |
688 | tegra_periph_reset_assert(tegra_pcie.pcie_xclk); | |
689 | tegra_periph_reset_assert(tegra_pcie.afi_clk); | |
690 | tegra_periph_reset_assert(tegra_pcie.pex_clk); | |
691 | ||
b96cc7fe | 692 | tegra_powergate_power_off(TEGRA_POWERGATE_PCIE); |
1e40a97e MR |
693 | tegra_pcie_xclk_clamp(true); |
694 | } | |
695 | ||
b96cc7fe | 696 | static int tegra_pcie_power_regate(void) |
77ffc146 | 697 | { |
b96cc7fe MR |
698 | int err; |
699 | ||
700 | tegra_pcie_power_off(); | |
701 | ||
77ffc146 | 702 | tegra_pcie_xclk_clamp(true); |
b96cc7fe | 703 | |
77ffc146 | 704 | tegra_periph_reset_assert(tegra_pcie.pcie_xclk); |
b96cc7fe MR |
705 | tegra_periph_reset_assert(tegra_pcie.afi_clk); |
706 | ||
707 | err = tegra_powergate_sequence_power_up(TEGRA_POWERGATE_PCIE, | |
708 | tegra_pcie.pex_clk); | |
709 | if (err) { | |
710 | pr_err("PCIE: powerup sequence failed: %d\n", err); | |
711 | return err; | |
712 | } | |
713 | ||
714 | tegra_periph_reset_deassert(tegra_pcie.afi_clk); | |
715 | ||
77ffc146 MR |
716 | tegra_pcie_xclk_clamp(false); |
717 | ||
718 | clk_enable(tegra_pcie.afi_clk); | |
719 | clk_enable(tegra_pcie.pex_clk); | |
720 | return clk_enable(tegra_pcie.pll_e); | |
721 | } | |
722 | ||
77ffc146 MR |
723 | static int tegra_pcie_clocks_get(void) |
724 | { | |
725 | int err; | |
726 | ||
727 | tegra_pcie.pex_clk = clk_get(NULL, "pex"); | |
728 | if (IS_ERR(tegra_pcie.pex_clk)) | |
729 | return PTR_ERR(tegra_pcie.pex_clk); | |
730 | ||
731 | tegra_pcie.afi_clk = clk_get(NULL, "afi"); | |
732 | if (IS_ERR(tegra_pcie.afi_clk)) { | |
733 | err = PTR_ERR(tegra_pcie.afi_clk); | |
734 | goto err_afi_clk; | |
735 | } | |
736 | ||
737 | tegra_pcie.pcie_xclk = clk_get(NULL, "pcie_xclk"); | |
738 | if (IS_ERR(tegra_pcie.pcie_xclk)) { | |
739 | err = PTR_ERR(tegra_pcie.pcie_xclk); | |
740 | goto err_pcie_xclk; | |
741 | } | |
742 | ||
743 | tegra_pcie.pll_e = clk_get_sys(NULL, "pll_e"); | |
744 | if (IS_ERR(tegra_pcie.pll_e)) { | |
745 | err = PTR_ERR(tegra_pcie.pll_e); | |
746 | goto err_pll_e; | |
747 | } | |
748 | ||
749 | return 0; | |
750 | ||
751 | err_pll_e: | |
752 | clk_put(tegra_pcie.pcie_xclk); | |
753 | err_pcie_xclk: | |
754 | clk_put(tegra_pcie.afi_clk); | |
755 | err_afi_clk: | |
756 | clk_put(tegra_pcie.pex_clk); | |
757 | ||
758 | return err; | |
759 | } | |
760 | ||
761 | static void tegra_pcie_clocks_put(void) | |
762 | { | |
763 | clk_put(tegra_pcie.pll_e); | |
764 | clk_put(tegra_pcie.pcie_xclk); | |
765 | clk_put(tegra_pcie.afi_clk); | |
766 | clk_put(tegra_pcie.pex_clk); | |
767 | } | |
768 | ||
769 | static int __init tegra_pcie_get_resources(void) | |
770 | { | |
771 | struct resource *res_mmio = &tegra_pcie.res_mmio; | |
772 | int err; | |
773 | ||
774 | err = tegra_pcie_clocks_get(); | |
775 | if (err) { | |
776 | pr_err("PCIE: failed to get clocks: %d\n", err); | |
777 | return err; | |
778 | } | |
779 | ||
b96cc7fe | 780 | err = tegra_pcie_power_regate(); |
77ffc146 MR |
781 | if (err) { |
782 | pr_err("PCIE: failed to power up: %d\n", err); | |
783 | goto err_pwr_on; | |
784 | } | |
785 | ||
786 | tegra_pcie.regs = ioremap_nocache(TEGRA_PCIE_BASE, PCIE_IOMAP_SZ); | |
787 | if (tegra_pcie.regs == NULL) { | |
788 | pr_err("PCIE: Failed to map PCI/AFI registers\n"); | |
789 | err = -ENOMEM; | |
790 | goto err_map_reg; | |
791 | } | |
792 | ||
793 | err = request_resource(&iomem_resource, res_mmio); | |
794 | if (err) { | |
795 | pr_err("PCIE: Failed to request resources: %d\n", err); | |
796 | goto err_req_io; | |
797 | } | |
798 | ||
799 | tegra_pcie_io_base = ioremap_nocache(res_mmio->start, | |
800 | resource_size(res_mmio)); | |
801 | if (tegra_pcie_io_base == NULL) { | |
802 | pr_err("PCIE: Failed to map IO\n"); | |
803 | err = -ENOMEM; | |
804 | goto err_map_io; | |
805 | } | |
806 | ||
807 | err = request_irq(INT_PCIE_INTR, tegra_pcie_isr, | |
808 | IRQF_SHARED, "PCIE", &tegra_pcie); | |
809 | if (err) { | |
810 | pr_err("PCIE: Failed to register IRQ: %d\n", err); | |
811 | goto err_irq; | |
812 | } | |
813 | set_irq_flags(INT_PCIE_INTR, IRQF_VALID); | |
814 | ||
815 | return 0; | |
816 | ||
817 | err_irq: | |
818 | iounmap(tegra_pcie_io_base); | |
819 | err_map_io: | |
820 | release_resource(&tegra_pcie.res_mmio); | |
821 | err_req_io: | |
822 | iounmap(tegra_pcie.regs); | |
823 | err_map_reg: | |
824 | tegra_pcie_power_off(); | |
825 | err_pwr_on: | |
826 | tegra_pcie_clocks_put(); | |
827 | ||
828 | return err; | |
829 | } | |
830 | ||
831 | /* | |
832 | * FIXME: If there are no PCIe cards attached, then calling this function | |
833 | * can result in the increase of the bootup time as there are big timeout | |
834 | * loops. | |
835 | */ | |
836 | #define TEGRA_PCIE_LINKUP_TIMEOUT 200 /* up to 1.2 seconds */ | |
837 | static bool tegra_pcie_check_link(struct tegra_pcie_port *pp, int idx, | |
838 | u32 reset_reg) | |
839 | { | |
840 | u32 reg; | |
841 | int retries = 3; | |
842 | int timeout; | |
843 | ||
844 | do { | |
845 | timeout = TEGRA_PCIE_LINKUP_TIMEOUT; | |
846 | while (timeout) { | |
847 | reg = readl(pp->base + RP_VEND_XP); | |
848 | ||
849 | if (reg & RP_VEND_XP_DL_UP) | |
850 | break; | |
851 | ||
852 | mdelay(1); | |
853 | timeout--; | |
854 | } | |
855 | ||
856 | if (!timeout) { | |
857 | pr_err("PCIE: port %d: link down, retrying\n", idx); | |
858 | goto retry; | |
859 | } | |
860 | ||
861 | timeout = TEGRA_PCIE_LINKUP_TIMEOUT; | |
862 | while (timeout) { | |
863 | reg = readl(pp->base + RP_LINK_CONTROL_STATUS); | |
864 | ||
865 | if (reg & 0x20000000) | |
866 | return true; | |
867 | ||
868 | mdelay(1); | |
869 | timeout--; | |
870 | } | |
871 | ||
872 | retry: | |
873 | /* Pulse the PEX reset */ | |
874 | reg = afi_readl(reset_reg) | AFI_PEX_CTRL_RST; | |
875 | afi_writel(reg, reset_reg); | |
876 | mdelay(1); | |
877 | reg = afi_readl(reset_reg) & ~AFI_PEX_CTRL_RST; | |
878 | afi_writel(reg, reset_reg); | |
879 | ||
880 | retries--; | |
881 | } while (retries); | |
882 | ||
883 | return false; | |
884 | } | |
885 | ||
886 | static void __init tegra_pcie_add_port(int index, u32 offset, u32 reset_reg) | |
887 | { | |
888 | struct tegra_pcie_port *pp; | |
889 | ||
890 | pp = tegra_pcie.port + tegra_pcie.num_ports; | |
891 | ||
892 | pp->index = -1; | |
893 | pp->base = tegra_pcie.regs + offset; | |
894 | pp->link_up = tegra_pcie_check_link(pp, index, reset_reg); | |
895 | ||
896 | if (!pp->link_up) { | |
897 | pp->base = NULL; | |
898 | printk(KERN_INFO "PCIE: port %d: link down, ignoring\n", index); | |
899 | return; | |
900 | } | |
901 | ||
902 | tegra_pcie.num_ports++; | |
903 | pp->index = index; | |
904 | pp->root_bus_nr = -1; | |
905 | memset(pp->res, 0, sizeof(pp->res)); | |
906 | } | |
907 | ||
908 | int __init tegra_pcie_init(bool init_port0, bool init_port1) | |
909 | { | |
910 | int err; | |
911 | ||
912 | if (!(init_port0 || init_port1)) | |
913 | return -ENODEV; | |
914 | ||
c9d95fbe RH |
915 | pcibios_min_mem = 0; |
916 | ||
77ffc146 MR |
917 | err = tegra_pcie_get_resources(); |
918 | if (err) | |
919 | return err; | |
920 | ||
921 | tegra_pcie_enable_controller(); | |
922 | ||
923 | /* setup the AFI address translations */ | |
924 | tegra_pcie_setup_translations(); | |
925 | ||
926 | if (init_port0) | |
927 | tegra_pcie_add_port(0, RP0_OFFSET, AFI_PEX0_CTRL); | |
928 | ||
929 | if (init_port1) | |
930 | tegra_pcie_add_port(1, RP1_OFFSET, AFI_PEX1_CTRL); | |
931 | ||
932 | pci_common_init(&tegra_pcie_hw); | |
933 | ||
934 | return 0; | |
935 | } |