[deliverable/linux.git] / arch / arm / mach-tegra / platsmp.c

/*
 *  linux/arch/arm/mach-tegra/platsmp.c
 *
 *  Copyright (C) 2002 ARM Ltd.
 *  All Rights Reserved
 *
 *  Copyright (C) 2009 Palm
 *  All Rights Reserved
 *
 * This program is free software; you can redistribute it and/or modify
 * it under the terms of the GNU General Public License version 2 as
 * published by the Free Software Foundation.
 */
#include <linux/init.h>
#include <linux/errno.h>
#include <linux/delay.h>
#include <linux/device.h>
#include <linux/jiffies.h>
#include <linux/smp.h>
#include <linux/io.h>

#include <asm/cacheflush.h>
#include <asm/hardware/gic.h>
#include <asm/mach-types.h>
#include <asm/smp_scu.h>

#include <mach/iomap.h>

extern void tegra_secondary_startup(void);

static DEFINE_SPINLOCK(boot_lock);
static void __iomem *scu_base = IO_ADDRESS(TEGRA_ARM_PERIF_BASE);

#define EVP_CPU_RESET_VECTOR \
	(IO_ADDRESS(TEGRA_EXCEPTION_VECTORS_BASE) + 0x100)
#define CLK_RST_CONTROLLER_CLK_CPU_CMPLX \
	(IO_ADDRESS(TEGRA_CLK_RESET_BASE) + 0x4c)
#define CLK_RST_CONTROLLER_RST_CPU_CMPLX_CLR \
	(IO_ADDRESS(TEGRA_CLK_RESET_BASE) + 0x344)

void __cpuinit platform_secondary_init(unsigned int cpu)
{
	/*
	 * if any interrupts are already enabled for the primary
	 * core (e.g. timer irq), then they will not have been enabled
	 * for us: do so
	 */
	gic_secondary_init(0);

	/*
	 * Synchronise with the boot thread.
	 */
	spin_lock(&boot_lock);
	spin_unlock(&boot_lock);
}

int __cpuinit boot_secondary(unsigned int cpu, struct task_struct *idle)
{
	unsigned long old_boot_vector;
	unsigned long boot_vector;
	unsigned long timeout;
	u32 reg;

	/*
	 * set synchronisation state between this boot processor
	 * and the secondary one
	 */
	spin_lock(&boot_lock);


	/* set the reset vector to point to the secondary_startup routine */

	boot_vector = virt_to_phys(tegra_secondary_startup);
	old_boot_vector = readl(EVP_CPU_RESET_VECTOR);
	writel(boot_vector, EVP_CPU_RESET_VECTOR);

	/* enable cpu clock on cpu1 */
	reg = readl(CLK_RST_CONTROLLER_CLK_CPU_CMPLX);
	writel(reg & ~(1<<9), CLK_RST_CONTROLLER_CLK_CPU_CMPLX);

	reg = (1<<13) | (1<<9) | (1<<5) | (1<<1);
	writel(reg, CLK_RST_CONTROLLER_RST_CPU_CMPLX_CLR);

	smp_wmb();
	flush_cache_all();

	/* unhalt the cpu */
	writel(0, IO_ADDRESS(TEGRA_FLOW_CTRL_BASE) + 0x14);

	timeout = jiffies + (1 * HZ);
	while (time_before(jiffies, timeout)) {
		if (readl(EVP_CPU_RESET_VECTOR) != boot_vector)
			break;
		udelay(10);
	}

	/* put the old boot vector back */
	writel(old_boot_vector, EVP_CPU_RESET_VECTOR);

	/*
	 * now the secondary core is starting up let it run its
	 * calibrations, then wait for it to finish
	 */
	spin_unlock(&boot_lock);

	return 0;
}

/*
 * Initialise the CPU possible map early - this describes the CPUs
 * which may be present or become present in the system.
 */
void __init smp_init_cpus(void)
{
	unsigned int i, ncores = scu_get_core_count(scu_base);

	if (ncores > NR_CPUS) {
		printk(KERN_ERR "Tegra: no. of cores (%u) greater than configured (%u), clipping\n",
			ncores, NR_CPUS);
		ncores = NR_CPUS;
	}

	for (i = 0; i < ncores; i++)
		cpu_set(i, cpu_possible_map);

	set_smp_cross_call(gic_raise_softirq);
}

void __init platform_smp_prepare_cpus(unsigned int max_cpus)
{
	int i;

	/*
	 * Initialise the present map, which describes the set of CPUs
	 * actually populated at the present time.
	 */
	for (i = 0; i < max_cpus; i++)
		set_cpu_present(i, true);

	scu_enable(scu_base);
}
Commit	Line	Data
1cea7326 CC	1	/*
	2	* linux/arch/arm/mach-tegra/platsmp.c
	3	*
	4	* Copyright (C) 2002 ARM Ltd.
	5	* All Rights Reserved
	6	*
	7	* Copyright (C) 2009 Palm
	8	* All Rights Reserved
	9	*
	10	* This program is free software; you can redistribute it and/or modify
	11	* it under the terms of the GNU General Public License version 2 as
	12	* published by the Free Software Foundation.
	13	*/
	14	#include <linux/init.h>
	15	#include <linux/errno.h>
	16	#include <linux/delay.h>
	17	#include <linux/device.h>
	18	#include <linux/jiffies.h>
	19	#include <linux/smp.h>
	20	#include <linux/io.h>
	21
	22	#include <asm/cacheflush.h>
0f7b332f	23	#include <asm/hardware/gic.h>
1cea7326	24	#include <asm/mach-types.h>
1cea7326 CC	25	#include <asm/smp_scu.h>
	26
	27	#include <mach/iomap.h>
	28
	29	extern void tegra_secondary_startup(void);
	30
	31	static DEFINE_SPINLOCK(boot_lock);
	32	static void __iomem *scu_base = IO_ADDRESS(TEGRA_ARM_PERIF_BASE);
	33
	34	#define EVP_CPU_RESET_VECTOR \
	35	(IO_ADDRESS(TEGRA_EXCEPTION_VECTORS_BASE) + 0x100)
	36	#define CLK_RST_CONTROLLER_CLK_CPU_CMPLX \
	37	(IO_ADDRESS(TEGRA_CLK_RESET_BASE) + 0x4c)
	38	#define CLK_RST_CONTROLLER_RST_CPU_CMPLX_CLR \
	39	(IO_ADDRESS(TEGRA_CLK_RESET_BASE) + 0x344)
	40
	41	void __cpuinit platform_secondary_init(unsigned int cpu)
	42	{
1cea7326 CC	43	/*
	44	* if any interrupts are already enabled for the primary
	45	* core (e.g. timer irq), then they will not have been enabled
	46	* for us: do so
	47	*/
38489533	48	gic_secondary_init(0);
1cea7326 CC	49
	50	/*
	51	* Synchronise with the boot thread.
	52	*/
	53	spin_lock(&boot_lock);
	54	spin_unlock(&boot_lock);
	55	}
	56
	57	int __cpuinit boot_secondary(unsigned int cpu, struct task_struct *idle)
	58	{
	59	unsigned long old_boot_vector;
	60	unsigned long boot_vector;
	61	unsigned long timeout;
	62	u32 reg;
	63
	64	/*
	65	* set synchronisation state between this boot processor
	66	* and the secondary one
	67	*/
	68	spin_lock(&boot_lock);
	69
	70
	71	/* set the reset vector to point to the secondary_startup routine */
	72
	73	boot_vector = virt_to_phys(tegra_secondary_startup);
	74	old_boot_vector = readl(EVP_CPU_RESET_VECTOR);
	75	writel(boot_vector, EVP_CPU_RESET_VECTOR);
	76
	77	/* enable cpu clock on cpu1 */
	78	reg = readl(CLK_RST_CONTROLLER_CLK_CPU_CMPLX);
	79	writel(reg & ~(1<<9), CLK_RST_CONTROLLER_CLK_CPU_CMPLX);
	80
	81	reg = (1<<13) \| (1<<9) \| (1<<5) \| (1<<1);
	82	writel(reg, CLK_RST_CONTROLLER_RST_CPU_CMPLX_CLR);
	83
	84	smp_wmb();
	85	flush_cache_all();
	86
	87	/* unhalt the cpu */
	88	writel(0, IO_ADDRESS(TEGRA_FLOW_CTRL_BASE) + 0x14);
	89
	90	timeout = jiffies + (1 * HZ);
	91	while (time_before(jiffies, timeout)) {
	92	if (readl(EVP_CPU_RESET_VECTOR) != boot_vector)
	93	break;
	94	udelay(10);
	95	}
	96
	97	/* put the old boot vector back */
	98	writel(old_boot_vector, EVP_CPU_RESET_VECTOR);
	99
	100	/*
	101	* now the secondary core is starting up let it run its
	102	* calibrations, then wait for it to finish
	103	*/
	104	spin_unlock(&boot_lock);
	105
	106	return 0;
	107	}
	108
	109	/*
	110	* Initialise the CPU possible map early - this describes the CPUs
	111	* which may be present or become present in the system.
	112	*/
113	void __init smp_init_cpus(void)
114	{
115	unsigned int i, ncores = scu_get_core_count(scu_base);
116
8975b6c0 RK	117	if (ncores > NR_CPUS) {
	118	printk(KERN_ERR "Tegra: no. of cores (%u) greater than configured (%u), clipping\n",
	119	ncores, NR_CPUS);
	120	ncores = NR_CPUS;
	121	}
	122
1cea7326 CC	123	for (i = 0; i < ncores; i++)
1cea7326 CC	124	cpu_set(i, cpu_possible_map);
0f7b332f RK	125
0f7b332f RK	126	set_smp_cross_call(gic_raise_softirq);
1cea7326 CC	127	}
1cea7326 CC	128
05c74a6c	129	void __init platform_smp_prepare_cpus(unsigned int max_cpus)
1cea7326	130	{
1cea7326 CC	131	int i;
1cea7326 CC	132
1cea7326 CC	133	/*
	134	* Initialise the present map, which describes the set of CPUs
	135	* actually populated at the present time.
	136	*/
	137	for (i = 0; i < max_cpus; i++)
	138	set_cpu_present(i, true);
	139
05c74a6c	140	scu_enable(scu_base);
1cea7326	141	}