[deliverable/linux.git] / arch / arm / mach-tegra / pm.c

/*
 * CPU complex suspend & resume functions for Tegra SoCs
 *
 * Copyright (c) 2009-2012, NVIDIA Corporation. All rights reserved.
 *
 * This program is free software; you can redistribute it and/or modify it
 * under the terms and conditions of the GNU General Public License,
 * version 2, as published by the Free Software Foundation.
 *
 * This program is distributed in the hope it will be useful, but WITHOUT
 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
 * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
 * more details.
 *
 * You should have received a copy of the GNU General Public License
 * along with this program.  If not, see <http://www.gnu.org/licenses/>.
 */

#include <linux/kernel.h>
#include <linux/spinlock.h>
#include <linux/io.h>
#include <linux/cpumask.h>
#include <linux/delay.h>
#include <linux/cpu_pm.h>
#include <linux/suspend.h>
#include <linux/err.h>
#include <linux/slab.h>
#include <linux/clk/tegra.h>

#include <asm/smp_plat.h>
#include <asm/cacheflush.h>
#include <asm/suspend.h>
#include <asm/idmap.h>
#include <asm/proc-fns.h>
#include <asm/tlbflush.h>

#include "iomap.h"
#include "reset.h"
#include "flowctrl.h"
#include "fuse.h"
#include "pm.h"
#include "pmc.h"
#include "sleep.h"

#ifdef CONFIG_PM_SLEEP
static DEFINE_SPINLOCK(tegra_lp2_lock);
static u32 iram_save_size;
static void *iram_save_addr;
struct tegra_lp1_iram tegra_lp1_iram;
void (*tegra_tear_down_cpu)(void);
void (*tegra_sleep_core_finish)(unsigned long v2p);
static int (*tegra_sleep_func)(unsigned long v2p);

static void tegra_tear_down_cpu_init(void)
{
	switch (tegra_chip_id) {
	case TEGRA20:
		if (IS_ENABLED(CONFIG_ARCH_TEGRA_2x_SOC))
			tegra_tear_down_cpu = tegra20_tear_down_cpu;
		break;
	case TEGRA30:
	case TEGRA114:
	case TEGRA124:
		if (IS_ENABLED(CONFIG_ARCH_TEGRA_3x_SOC) ||
		    IS_ENABLED(CONFIG_ARCH_TEGRA_114_SOC) ||
		    IS_ENABLED(CONFIG_ARCH_TEGRA_124_SOC))
			tegra_tear_down_cpu = tegra30_tear_down_cpu;
		break;
	}
}

/*
 * restore_cpu_complex
 *
 * restores cpu clock setting, clears flow controller
 *
 * Always called on CPU 0.
 */
static void restore_cpu_complex(void)
{
	int cpu = smp_processor_id();

	BUG_ON(cpu != 0);

#ifdef CONFIG_SMP
	cpu = cpu_logical_map(cpu);
#endif

	/* Restore the CPU clock settings */
	tegra_cpu_clock_resume();

	flowctrl_cpu_suspend_exit(cpu);
}

/*
 * suspend_cpu_complex
 *
 * saves pll state for use by restart_plls, prepares flow controller for
 * transition to suspend state
 *
 * Must always be called on cpu 0.
 */
static void suspend_cpu_complex(void)
{
	int cpu = smp_processor_id();

	BUG_ON(cpu != 0);

#ifdef CONFIG_SMP
	cpu = cpu_logical_map(cpu);
#endif

	/* Save the CPU clock settings */
	tegra_cpu_clock_suspend();

	flowctrl_cpu_suspend_enter(cpu);
}

void tegra_clear_cpu_in_lp2(void)
{
	int phy_cpu_id = cpu_logical_map(smp_processor_id());
	u32 *cpu_in_lp2 = tegra_cpu_lp2_mask;

	spin_lock(&tegra_lp2_lock);

	BUG_ON(!(*cpu_in_lp2 & BIT(phy_cpu_id)));
	*cpu_in_lp2 &= ~BIT(phy_cpu_id);

	spin_unlock(&tegra_lp2_lock);
}

bool tegra_set_cpu_in_lp2(void)
{
	int phy_cpu_id = cpu_logical_map(smp_processor_id());
	bool last_cpu = false;
	cpumask_t *cpu_lp2_mask = tegra_cpu_lp2_mask;
	u32 *cpu_in_lp2 = tegra_cpu_lp2_mask;

	spin_lock(&tegra_lp2_lock);

	BUG_ON((*cpu_in_lp2 & BIT(phy_cpu_id)));
	*cpu_in_lp2 |= BIT(phy_cpu_id);

	if ((phy_cpu_id == 0) && cpumask_equal(cpu_lp2_mask, cpu_online_mask))
		last_cpu = true;
	else if (tegra_chip_id == TEGRA20 && phy_cpu_id == 1)
		tegra20_cpu_set_resettable_soon();

	spin_unlock(&tegra_lp2_lock);
	return last_cpu;
}

int tegra_cpu_do_idle(void)
{
	return cpu_do_idle();
}

static int tegra_sleep_cpu(unsigned long v2p)
{
	setup_mm_for_reboot();
	tegra_sleep_cpu_finish(v2p);

	/* should never here */
	BUG();

	return 0;
}

void tegra_idle_lp2_last(void)
{
	tegra_pmc_pm_set(TEGRA_SUSPEND_LP2);

	cpu_cluster_pm_enter();
	suspend_cpu_complex();

	cpu_suspend(PHYS_OFFSET - PAGE_OFFSET, &tegra_sleep_cpu);

	restore_cpu_complex();
	cpu_cluster_pm_exit();
}

enum tegra_suspend_mode tegra_pm_validate_suspend_mode(
				enum tegra_suspend_mode mode)
{
	/*
	 * The Tegra devices support suspending to LP1 or lower currently.
	 */
	if (mode > TEGRA_SUSPEND_LP1)
		return TEGRA_SUSPEND_LP1;

	return mode;
}

static int tegra_sleep_core(unsigned long v2p)
{
	setup_mm_for_reboot();
	tegra_sleep_core_finish(v2p);

	/* should never here */
	BUG();

	return 0;
}

/*
 * tegra_lp1_iram_hook
 *
 * Hooking the address of LP1 reset vector and SDRAM self-refresh code in
 * SDRAM. These codes not be copied to IRAM in this fuction. We need to
 * copy these code to IRAM before LP0/LP1 suspend and restore the content
 * of IRAM after resume.
 */
static bool tegra_lp1_iram_hook(void)
{
	switch (tegra_chip_id) {
	case TEGRA20:
		if (IS_ENABLED(CONFIG_ARCH_TEGRA_2x_SOC))
			tegra20_lp1_iram_hook();
		break;
	case TEGRA30:
	case TEGRA114:
	case TEGRA124:
		if (IS_ENABLED(CONFIG_ARCH_TEGRA_3x_SOC) ||
		    IS_ENABLED(CONFIG_ARCH_TEGRA_114_SOC) ||
		    IS_ENABLED(CONFIG_ARCH_TEGRA_124_SOC))
			tegra30_lp1_iram_hook();
		break;
	default:
		break;
	}

	if (!tegra_lp1_iram.start_addr || !tegra_lp1_iram.end_addr)
		return false;

	iram_save_size = tegra_lp1_iram.end_addr - tegra_lp1_iram.start_addr;
	iram_save_addr = kmalloc(iram_save_size, GFP_KERNEL);
	if (!iram_save_addr)
		return false;

	return true;
}

static bool tegra_sleep_core_init(void)
{
	switch (tegra_chip_id) {
	case TEGRA20:
		if (IS_ENABLED(CONFIG_ARCH_TEGRA_2x_SOC))
			tegra20_sleep_core_init();
		break;
	case TEGRA30:
	case TEGRA114:
	case TEGRA124:
		if (IS_ENABLED(CONFIG_ARCH_TEGRA_3x_SOC) ||
		    IS_ENABLED(CONFIG_ARCH_TEGRA_114_SOC) ||
		    IS_ENABLED(CONFIG_ARCH_TEGRA_124_SOC))
			tegra30_sleep_core_init();
		break;
	default:
		break;
	}

	if (!tegra_sleep_core_finish)
		return false;

	return true;
}

static void tegra_suspend_enter_lp1(void)
{
	tegra_pmc_suspend();

	/* copy the reset vector & SDRAM shutdown code into IRAM */
	memcpy(iram_save_addr, IO_ADDRESS(TEGRA_IRAM_LPx_RESUME_AREA),
		iram_save_size);
	memcpy(IO_ADDRESS(TEGRA_IRAM_LPx_RESUME_AREA),
		tegra_lp1_iram.start_addr, iram_save_size);

	*((u32 *)tegra_cpu_lp1_mask) = 1;
}

static void tegra_suspend_exit_lp1(void)
{
	tegra_pmc_resume();

	/* restore IRAM */
	memcpy(IO_ADDRESS(TEGRA_IRAM_LPx_RESUME_AREA), iram_save_addr,
		iram_save_size);

	*(u32 *)tegra_cpu_lp1_mask = 0;
}

static const char *lp_state[TEGRA_MAX_SUSPEND_MODE] = {
	[TEGRA_SUSPEND_NONE] = "none",
	[TEGRA_SUSPEND_LP2] = "LP2",
	[TEGRA_SUSPEND_LP1] = "LP1",
	[TEGRA_SUSPEND_LP0] = "LP0",
};

static int tegra_suspend_enter(suspend_state_t state)
{
	enum tegra_suspend_mode mode = tegra_pmc_get_suspend_mode();

	if (WARN_ON(mode < TEGRA_SUSPEND_NONE ||
		    mode >= TEGRA_MAX_SUSPEND_MODE))
		return -EINVAL;

	pr_info("Entering suspend state %s\n", lp_state[mode]);

	tegra_pmc_pm_set(mode);

	local_fiq_disable();

	suspend_cpu_complex();
	switch (mode) {
	case TEGRA_SUSPEND_LP1:
		tegra_suspend_enter_lp1();
		break;
	case TEGRA_SUSPEND_LP2:
		tegra_set_cpu_in_lp2();
		break;
	default:
		break;
	}

	cpu_suspend(PHYS_OFFSET - PAGE_OFFSET, tegra_sleep_func);

	switch (mode) {
	case TEGRA_SUSPEND_LP1:
		tegra_suspend_exit_lp1();
		break;
	case TEGRA_SUSPEND_LP2:
		tegra_clear_cpu_in_lp2();
		break;
	default:
		break;
	}
	restore_cpu_complex();

	local_fiq_enable();

	return 0;
}

static const struct platform_suspend_ops tegra_suspend_ops = {
	.valid		= suspend_valid_only_mem,
	.enter		= tegra_suspend_enter,
};

void __init tegra_init_suspend(void)
{
	enum tegra_suspend_mode mode = tegra_pmc_get_suspend_mode();

	if (mode == TEGRA_SUSPEND_NONE)
		return;

	tegra_tear_down_cpu_init();
	tegra_pmc_suspend_init();

	if (mode >= TEGRA_SUSPEND_LP1) {
		if (!tegra_lp1_iram_hook() || !tegra_sleep_core_init()) {
			pr_err("%s: unable to allocate memory for SDRAM"
			       "self-refresh -- LP0/LP1 unavailable\n",
			       __func__);
			tegra_pmc_set_suspend_mode(TEGRA_SUSPEND_LP2);
			mode = TEGRA_SUSPEND_LP2;
		}
	}

	/* set up sleep function for cpu_suspend */
	switch (mode) {
	case TEGRA_SUSPEND_LP1:
		tegra_sleep_func = tegra_sleep_core;
		break;
	case TEGRA_SUSPEND_LP2:
		tegra_sleep_func = tegra_sleep_cpu;
		break;
	default:
		break;
	}

	suspend_set_ops(&tegra_suspend_ops);
}
#endif
Commit	Line	Data
d457ef35 JL	1	/*
	2	* CPU complex suspend & resume functions for Tegra SoCs
	3	*
	4	* Copyright (c) 2009-2012, NVIDIA Corporation. All rights reserved.
	5	*
	6	* This program is free software; you can redistribute it and/or modify it
	7	* under the terms and conditions of the GNU General Public License,
	8	* version 2, as published by the Free Software Foundation.
	9	*
	10	* This program is distributed in the hope it will be useful, but WITHOUT
	11	* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
	12	* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
	13	* more details.
	14	*
	15	* You should have received a copy of the GNU General Public License
	16	* along with this program. If not, see <http://www.gnu.org/licenses/>.
	17	*/
	18
	19	#include <linux/kernel.h>
	20	#include <linux/spinlock.h>
	21	#include <linux/io.h>
	22	#include <linux/cpumask.h>
d552920a JL	23	#include <linux/delay.h>
d552920a JL	24	#include <linux/cpu_pm.h>
c8c2e606	25	#include <linux/suspend.h>
d552920a	26	#include <linux/err.h>
1ff6bbfd	27	#include <linux/slab.h>
89572c77	28	#include <linux/clk/tegra.h>
d552920a JL	29
	30	#include <asm/smp_plat.h>
	31	#include <asm/cacheflush.h>
	32	#include <asm/suspend.h>
	33	#include <asm/idmap.h>
	34	#include <asm/proc-fns.h>
	35	#include <asm/tlbflush.h>
d457ef35 JL	36
	37	#include "iomap.h"
	38	#include "reset.h"
d552920a	39	#include "flowctrl.h"
5c1350bd	40	#include "fuse.h"
95872f42	41	#include "pm.h"
0337c3e0	42	#include "pmc.h"
d552920a	43	#include "sleep.h"
d552920a	44
d457ef35	45	#ifdef CONFIG_PM_SLEEP
d457ef35	46	static DEFINE_SPINLOCK(tegra_lp2_lock);
95872f42 JL	47	static u32 iram_save_size;
	48	static void *iram_save_addr;
	49	struct tegra_lp1_iram tegra_lp1_iram;
d552920a	50	void (*tegra_tear_down_cpu)(void);
95872f42 JL	51	void (*tegra_sleep_core_finish)(unsigned long v2p);
95872f42 JL	52	static int (*tegra_sleep_func)(unsigned long v2p);
d457ef35	53
bf91add4 JL	54	static void tegra_tear_down_cpu_init(void)
	55	{
	56	switch (tegra_chip_id) {
	57	case TEGRA20:
	58	if (IS_ENABLED(CONFIG_ARCH_TEGRA_2x_SOC))
	59	tegra_tear_down_cpu = tegra20_tear_down_cpu;
	60	break;
	61	case TEGRA30:
b573ad9f	62	case TEGRA114:
f0c4ac13	63	case TEGRA124:
b573ad9f	64	if (IS_ENABLED(CONFIG_ARCH_TEGRA_3x_SOC) \|\|
f0c4ac13 JL	65	IS_ENABLED(CONFIG_ARCH_TEGRA_114_SOC) \|\|
f0c4ac13 JL	66	IS_ENABLED(CONFIG_ARCH_TEGRA_124_SOC))
bf91add4 JL	67	tegra_tear_down_cpu = tegra30_tear_down_cpu;
	68	break;
	69	}
	70	}
	71
d552920a JL	72	/*
	73	* restore_cpu_complex
	74	*
	75	* restores cpu clock setting, clears flow controller
	76	*
	77	* Always called on CPU 0.
	78	*/
	79	static void restore_cpu_complex(void)
	80	{
	81	int cpu = smp_processor_id();
	82
	83	BUG_ON(cpu != 0);
	84
	85	#ifdef CONFIG_SMP
	86	cpu = cpu_logical_map(cpu);
	87	#endif
	88
	89	/* Restore the CPU clock settings */
	90	tegra_cpu_clock_resume();
	91
	92	flowctrl_cpu_suspend_exit(cpu);
d552920a JL	93	}
	94
	95	/*
	96	* suspend_cpu_complex
	97	*
	98	* saves pll state for use by restart_plls, prepares flow controller for
	99	* transition to suspend state
	100	*
	101	* Must always be called on cpu 0.
	102	*/
	103	static void suspend_cpu_complex(void)
	104	{
	105	int cpu = smp_processor_id();
	106
	107	BUG_ON(cpu != 0);
	108
	109	#ifdef CONFIG_SMP
	110	cpu = cpu_logical_map(cpu);
	111	#endif
	112
	113	/* Save the CPU clock settings */
	114	tegra_cpu_clock_suspend();
	115
	116	flowctrl_cpu_suspend_enter(cpu);
d552920a JL	117	}
d552920a JL	118
8f6a0b65	119	void tegra_clear_cpu_in_lp2(void)
d457ef35	120	{
8f6a0b65	121	int phy_cpu_id = cpu_logical_map(smp_processor_id());
d457ef35 JL	122	u32 *cpu_in_lp2 = tegra_cpu_lp2_mask;
	123
	124	spin_lock(&tegra_lp2_lock);
	125
	126	BUG_ON(!(*cpu_in_lp2 & BIT(phy_cpu_id)));
	127	*cpu_in_lp2 &= ~BIT(phy_cpu_id);
	128
	129	spin_unlock(&tegra_lp2_lock);
	130	}
	131
8f6a0b65	132	bool tegra_set_cpu_in_lp2(void)
d457ef35	133	{
8f6a0b65	134	int phy_cpu_id = cpu_logical_map(smp_processor_id());
d457ef35 JL	135	bool last_cpu = false;
	136	cpumask_t *cpu_lp2_mask = tegra_cpu_lp2_mask;
	137	u32 *cpu_in_lp2 = tegra_cpu_lp2_mask;
	138
	139	spin_lock(&tegra_lp2_lock);
	140
	141	BUG_ON((*cpu_in_lp2 & BIT(phy_cpu_id)));
	142	*cpu_in_lp2 \|= BIT(phy_cpu_id);
	143
	144	if ((phy_cpu_id == 0) && cpumask_equal(cpu_lp2_mask, cpu_online_mask))
	145	last_cpu = true;
5c1350bd JL	146	else if (tegra_chip_id == TEGRA20 && phy_cpu_id == 1)
5c1350bd JL	147	tegra20_cpu_set_resettable_soon();
d457ef35 JL	148
	149	spin_unlock(&tegra_lp2_lock);
	150	return last_cpu;
	151	}
d552920a	152
2058842e AB	153	int tegra_cpu_do_idle(void)
	154	{
	155	return cpu_do_idle();
	156	}
	157
d552920a JL	158	static int tegra_sleep_cpu(unsigned long v2p)
d552920a JL	159	{
6affb482	160	setup_mm_for_reboot();
d552920a JL	161	tegra_sleep_cpu_finish(v2p);
	162
	163	/* should never here */
	164	BUG();
	165
	166	return 0;
	167	}
	168
4d82d058	169	void tegra_idle_lp2_last(void)
d552920a	170	{
c8c2e606	171	tegra_pmc_pm_set(TEGRA_SUSPEND_LP2);
d552920a JL	172
	173	cpu_cluster_pm_enter();
	174	suspend_cpu_complex();
d552920a JL	175
	176	cpu_suspend(PHYS_OFFSET - PAGE_OFFSET, &tegra_sleep_cpu);
	177
d552920a JL	178	restore_cpu_complex();
	179	cpu_cluster_pm_exit();
	180	}
c8c2e606 JL	181
	182	enum tegra_suspend_mode tegra_pm_validate_suspend_mode(
	183	enum tegra_suspend_mode mode)
	184	{
c8c2e606	185	/*
95872f42	186	* The Tegra devices support suspending to LP1 or lower currently.
c8c2e606	187	*/
95872f42 JL	188	if (mode > TEGRA_SUSPEND_LP1)
95872f42 JL	189	return TEGRA_SUSPEND_LP1;
c8c2e606 JL	190
	191	return mode;
	192	}
	193
95872f42 JL	194	static int tegra_sleep_core(unsigned long v2p)
	195	{
	196	setup_mm_for_reboot();
	197	tegra_sleep_core_finish(v2p);
	198
	199	/* should never here */
	200	BUG();
	201
	202	return 0;
	203	}
	204
	205	/*
	206	* tegra_lp1_iram_hook
	207	*
	208	* Hooking the address of LP1 reset vector and SDRAM self-refresh code in
	209	* SDRAM. These codes not be copied to IRAM in this fuction. We need to
	210	* copy these code to IRAM before LP0/LP1 suspend and restore the content
	211	* of IRAM after resume.
	212	*/
	213	static bool tegra_lp1_iram_hook(void)
	214	{
e7a932b1	215	switch (tegra_chip_id) {
731a9274 JL	216	case TEGRA20:
	217	if (IS_ENABLED(CONFIG_ARCH_TEGRA_2x_SOC))
	218	tegra20_lp1_iram_hook();
	219	break;
e7a932b1	220	case TEGRA30:
e9f62449	221	case TEGRA114:
f0c4ac13	222	case TEGRA124:
e9f62449	223	if (IS_ENABLED(CONFIG_ARCH_TEGRA_3x_SOC) \|\|
f0c4ac13 JL	224	IS_ENABLED(CONFIG_ARCH_TEGRA_114_SOC) \|\|
f0c4ac13 JL	225	IS_ENABLED(CONFIG_ARCH_TEGRA_124_SOC))
e7a932b1 JL	226	tegra30_lp1_iram_hook();
	227	break;
	228	default:
	229	break;
	230	}
	231
95872f42 JL	232	if (!tegra_lp1_iram.start_addr \|\| !tegra_lp1_iram.end_addr)
	233	return false;
	234
	235	iram_save_size = tegra_lp1_iram.end_addr - tegra_lp1_iram.start_addr;
	236	iram_save_addr = kmalloc(iram_save_size, GFP_KERNEL);
	237	if (!iram_save_addr)
	238	return false;
	239
	240	return true;
	241	}
	242
	243	static bool tegra_sleep_core_init(void)
	244	{
e7a932b1	245	switch (tegra_chip_id) {
731a9274 JL	246	case TEGRA20:
	247	if (IS_ENABLED(CONFIG_ARCH_TEGRA_2x_SOC))
	248	tegra20_sleep_core_init();
	249	break;
e7a932b1	250	case TEGRA30:
e9f62449	251	case TEGRA114:
f0c4ac13	252	case TEGRA124:
e9f62449	253	if (IS_ENABLED(CONFIG_ARCH_TEGRA_3x_SOC) \|\|
f0c4ac13 JL	254	IS_ENABLED(CONFIG_ARCH_TEGRA_114_SOC) \|\|
f0c4ac13 JL	255	IS_ENABLED(CONFIG_ARCH_TEGRA_124_SOC))
e7a932b1 JL	256	tegra30_sleep_core_init();
	257	break;
	258	default:
	259	break;
	260	}
	261
95872f42 JL	262	if (!tegra_sleep_core_finish)
	263	return false;
	264
	265	return true;
	266	}
	267
	268	static void tegra_suspend_enter_lp1(void)
	269	{
	270	tegra_pmc_suspend();
	271
	272	/* copy the reset vector & SDRAM shutdown code into IRAM */
fddb770d	273	memcpy(iram_save_addr, IO_ADDRESS(TEGRA_IRAM_LPx_RESUME_AREA),
95872f42	274	iram_save_size);
fddb770d SW	275	memcpy(IO_ADDRESS(TEGRA_IRAM_LPx_RESUME_AREA),
fddb770d SW	276	tegra_lp1_iram.start_addr, iram_save_size);
95872f42 JL	277
	278	((u32 )tegra_cpu_lp1_mask) = 1;
	279	}
	280
	281	static void tegra_suspend_exit_lp1(void)
	282	{
	283	tegra_pmc_resume();
	284
	285	/* restore IRAM */
fddb770d	286	memcpy(IO_ADDRESS(TEGRA_IRAM_LPx_RESUME_AREA), iram_save_addr,
95872f42 JL	287	iram_save_size);
	288
	289	(u32 )tegra_cpu_lp1_mask = 0;
	290	}
	291
c8c2e606 JL	292	static const char *lp_state[TEGRA_MAX_SUSPEND_MODE] = {
	293	[TEGRA_SUSPEND_NONE] = "none",
	294	[TEGRA_SUSPEND_LP2] = "LP2",
	295	[TEGRA_SUSPEND_LP1] = "LP1",
	296	[TEGRA_SUSPEND_LP0] = "LP0",
	297	};
	298
8bd26e3a	299	static int tegra_suspend_enter(suspend_state_t state)
c8c2e606 JL	300	{
	301	enum tegra_suspend_mode mode = tegra_pmc_get_suspend_mode();
	302
	303	if (WARN_ON(mode < TEGRA_SUSPEND_NONE \|\|
	304	mode >= TEGRA_MAX_SUSPEND_MODE))
	305	return -EINVAL;
	306
	307	pr_info("Entering suspend state %s\n", lp_state[mode]);
	308
	309	tegra_pmc_pm_set(mode);
	310
	311	local_fiq_disable();
	312
	313	suspend_cpu_complex();
	314	switch (mode) {
95872f42 JL	315	case TEGRA_SUSPEND_LP1:
	316	tegra_suspend_enter_lp1();
	317	break;
c8c2e606	318	case TEGRA_SUSPEND_LP2:
8f6a0b65	319	tegra_set_cpu_in_lp2();
c8c2e606 JL	320	break;
	321	default:
	322	break;
	323	}
	324
95872f42	325	cpu_suspend(PHYS_OFFSET - PAGE_OFFSET, tegra_sleep_func);
c8c2e606 JL	326
c8c2e606 JL	327	switch (mode) {
95872f42 JL	328	case TEGRA_SUSPEND_LP1:
	329	tegra_suspend_exit_lp1();
	330	break;
c8c2e606	331	case TEGRA_SUSPEND_LP2:
8f6a0b65	332	tegra_clear_cpu_in_lp2();
c8c2e606 JL	333	break;
	334	default:
	335	break;
	336	}
	337	restore_cpu_complex();
	338
	339	local_fiq_enable();
	340
	341	return 0;
	342	}
	343
	344	static const struct platform_suspend_ops tegra_suspend_ops = {
	345	.valid = suspend_valid_only_mem,
	346	.enter = tegra_suspend_enter,
	347	};
	348
	349	void __init tegra_init_suspend(void)
	350	{
95872f42 JL	351	enum tegra_suspend_mode mode = tegra_pmc_get_suspend_mode();
	352
	353	if (mode == TEGRA_SUSPEND_NONE)
c8c2e606 JL	354	return;
c8c2e606 JL	355
bf91add4	356	tegra_tear_down_cpu_init();
c8c2e606 JL	357	tegra_pmc_suspend_init();
c8c2e606 JL	358
95872f42 JL	359	if (mode >= TEGRA_SUSPEND_LP1) {
	360	if (!tegra_lp1_iram_hook() \|\| !tegra_sleep_core_init()) {
	361	pr_err("%s: unable to allocate memory for SDRAM"
	362	"self-refresh -- LP0/LP1 unavailable\n",
	363	__func__);
	364	tegra_pmc_set_suspend_mode(TEGRA_SUSPEND_LP2);
	365	mode = TEGRA_SUSPEND_LP2;
	366	}
	367	}
	368
	369	/* set up sleep function for cpu_suspend */
	370	switch (mode) {
	371	case TEGRA_SUSPEND_LP1:
	372	tegra_sleep_func = tegra_sleep_core;
	373	break;
	374	case TEGRA_SUSPEND_LP2:
	375	tegra_sleep_func = tegra_sleep_cpu;
	376	break;
	377	default:
	378	break;
	379	}
	380
c8c2e606 JL	381	suspend_set_ops(&tegra_suspend_ops);
c8c2e606 JL	382	}
d457ef35	383	#endif