[deliverable/linux.git] / arch / arm / mach-tegra / reset-handler.S

/*
 * Copyright (c) 2012, NVIDIA Corporation. All rights reserved.
 *
 * This program is free software; you can redistribute it and/or modify it
 * under the terms and conditions of the GNU General Public License,
 * version 2, as published by the Free Software Foundation.
 *
 * This program is distributed in the hope it will be useful, but WITHOUT
 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
 * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
 * more details.
 *
 * You should have received a copy of the GNU General Public License
 * along with this program.  If not, see <http://www.gnu.org/licenses/>.
 */

#include <linux/linkage.h>
#include <linux/init.h>

#include <asm/cache.h>
#include <asm/asm-offsets.h>
#include <asm/hardware/cache-l2x0.h>

#include "flowctrl.h"
#include "fuse.h"
#include "iomap.h"
#include "reset.h"
#include "sleep.h"

#define PMC_SCRATCH41	0x140

#define RESET_DATA(x)	((TEGRA_RESET_##x)*4)

#ifdef CONFIG_PM_SLEEP
/*
 *	tegra_resume
 *
 *	  CPU boot vector when restarting the a CPU following
 *	  an LP2 transition. Also branched to by LP0 and LP1 resume after
 *	  re-enabling sdram.
 *
 *	r6: SoC ID
 */
ENTRY(tegra_resume)
	bl	v7_invalidate_l1

	cpu_id	r0
	tegra_get_soc_id TEGRA_APB_MISC_BASE, r6
	cmp	r6, #TEGRA114
	beq	no_cpu0_chk

	cmp	r0, #0				@ CPU0?
 THUMB(	it	ne )
	bne	cpu_resume			@ no
no_cpu0_chk:

#ifndef CONFIG_ARCH_TEGRA_2x_SOC
	/* Are we on Tegra20? */
	cmp	r6, #TEGRA20
	beq	1f				@ Yes
	/* Clear the flow controller flags for this CPU. */
	cpu_to_csr_req r1, r0
	mov32	r2, TEGRA_FLOW_CTRL_BASE
	ldr	r1, [r2, r1]
	/* Clear event & intr flag */
	orr	r1, r1, \
		#FLOW_CTRL_CSR_INTR_FLAG | FLOW_CTRL_CSR_EVENT_FLAG
	movw	r0, #0x3FFD	@ enable, cluster_switch, immed, bitmaps
				@ & ext flags for CPU power mgnt
	bic	r1, r1, r0
	str	r1, [r2]
1:
#endif

	check_cpu_part_num 0xc09, r8, r9
	bne	not_ca9
#ifdef CONFIG_HAVE_ARM_SCU
	/* enable SCU */
	mov32	r0, TEGRA_ARM_PERIF_BASE
	ldr	r1, [r0]
	orr	r1, r1, #1
	str	r1, [r0]
#endif

	/* L2 cache resume & re-enable */
	l2_cache_resume r0, r1, r2, l2x0_saved_regs_addr
not_ca9:

	b	cpu_resume
ENDPROC(tegra_resume)
#endif

#ifdef CONFIG_CACHE_L2X0
	.globl	l2x0_saved_regs_addr
l2x0_saved_regs_addr:
	.long	0
#endif

	.align L1_CACHE_SHIFT
ENTRY(__tegra_cpu_reset_handler_start)

/*
 * __tegra_cpu_reset_handler:
 *
 * Common handler for all CPU reset events.
 *
 * Register usage within the reset handler:
 *
 *      Others: scratch
 *      R6  = SoC ID
 *      R7  = CPU present (to the OS) mask
 *      R8  = CPU in LP1 state mask
 *      R9  = CPU in LP2 state mask
 *      R10 = CPU number
 *      R11 = CPU mask
 *      R12 = pointer to reset handler data
 *
 * NOTE: This code is copied to IRAM. All code and data accesses
 *       must be position-independent.
 */

	.align L1_CACHE_SHIFT
ENTRY(__tegra_cpu_reset_handler)

	cpsid	aif, 0x13			@ SVC mode, interrupts disabled

	tegra_get_soc_id TEGRA_APB_MISC_BASE, r6
#ifdef CONFIG_ARCH_TEGRA_2x_SOC
t20_check:
	cmp	r6, #TEGRA20
	bne	after_t20_check
t20_errata:
	# Tegra20 is a Cortex-A9 r1p1
	mrc	p15, 0, r0, c1, c0, 0   @ read system control register
	orr	r0, r0, #1 << 14        @ erratum 716044
	mcr	p15, 0, r0, c1, c0, 0   @ write system control register
	mrc	p15, 0, r0, c15, c0, 1  @ read diagnostic register
	orr	r0, r0, #1 << 4         @ erratum 742230
	orr	r0, r0, #1 << 11        @ erratum 751472
	mcr	p15, 0, r0, c15, c0, 1  @ write diagnostic register
	b	after_errata
after_t20_check:
#endif
#ifdef CONFIG_ARCH_TEGRA_3x_SOC
t30_check:
	cmp	r6, #TEGRA30
	bne	after_t30_check
t30_errata:
	# Tegra30 is a Cortex-A9 r2p9
	mrc	p15, 0, r0, c15, c0, 1  @ read diagnostic register
	orr	r0, r0, #1 << 6         @ erratum 743622
	orr	r0, r0, #1 << 11        @ erratum 751472
	mcr	p15, 0, r0, c15, c0, 1  @ write diagnostic register
	b	after_errata
after_t30_check:
#endif
after_errata:
	mrc	p15, 0, r10, c0, c0, 5		@ MPIDR
	and	r10, r10, #0x3			@ R10 = CPU number
	mov	r11, #1
	mov	r11, r11, lsl r10  		@ R11 = CPU mask
	adr	r12, __tegra_cpu_reset_handler_data

#ifdef CONFIG_SMP
	/* Does the OS know about this CPU? */
	ldr	r7, [r12, #RESET_DATA(MASK_PRESENT)]
	tst	r7, r11 			@ if !present
	bleq	__die				@ CPU not present (to OS)
#endif

#ifdef CONFIG_ARCH_TEGRA_2x_SOC
	/* Are we on Tegra20? */
	cmp	r6, #TEGRA20
	bne	1f
	/* If not CPU0, don't let CPU0 reset CPU1 now that CPU1 is coming up. */
	mov32	r5, TEGRA_PMC_BASE
	mov	r0, #0
	cmp	r10, #0
	strne	r0, [r5, #PMC_SCRATCH41]
1:
#endif

	/* Waking up from LP2? */
	ldr	r9, [r12, #RESET_DATA(MASK_LP2)]
	tst	r9, r11				@ if in_lp2
	beq	__is_not_lp2
	ldr	lr, [r12, #RESET_DATA(STARTUP_LP2)]
	cmp	lr, #0
	bleq	__die				@ no LP2 startup handler
	bx	lr

__is_not_lp2:

#ifdef CONFIG_SMP
	/*
	 * Can only be secondary boot (initial or hotplug)
	 * CPU0 can't be here for Tegra20/30
	 */
	cmp	r6, #TEGRA114
	beq	__no_cpu0_chk
	cmp	r10, #0
	bleq	__die				@ CPU0 cannot be here
__no_cpu0_chk:
	ldr	lr, [r12, #RESET_DATA(STARTUP_SECONDARY)]
	cmp	lr, #0
	bleq	__die				@ no secondary startup handler
	bx	lr
#endif

/*
 * We don't know why the CPU reset. Just kill it.
 * The LR register will contain the address we died at + 4.
 */

__die:
	sub	lr, lr, #4
	mov32	r7, TEGRA_PMC_BASE
	str	lr, [r7, #PMC_SCRATCH41]

	mov32	r7, TEGRA_CLK_RESET_BASE

	/* Are we on Tegra20? */
	cmp	r6, #TEGRA20
	bne	1f

#ifdef CONFIG_ARCH_TEGRA_2x_SOC
	mov32	r0, 0x1111
	mov	r1, r0, lsl r10
	str	r1, [r7, #0x340]		@ CLK_RST_CPU_CMPLX_SET
#endif
1:
#ifdef CONFIG_ARCH_TEGRA_3x_SOC
	mov32	r6, TEGRA_FLOW_CTRL_BASE

	cmp	r10, #0
	moveq	r1, #FLOW_CTRL_HALT_CPU0_EVENTS
	moveq	r2, #FLOW_CTRL_CPU0_CSR
	movne	r1, r10, lsl #3
	addne	r2, r1, #(FLOW_CTRL_CPU1_CSR-8)
	addne	r1, r1, #(FLOW_CTRL_HALT_CPU1_EVENTS-8)

	/* Clear CPU "event" and "interrupt" flags and power gate
	   it when halting but not before it is in the "WFI" state. */
	ldr	r0, [r6, +r2]
	orr	r0, r0, #FLOW_CTRL_CSR_INTR_FLAG | FLOW_CTRL_CSR_EVENT_FLAG
	orr	r0, r0, #FLOW_CTRL_CSR_ENABLE
	str	r0, [r6, +r2]

	/* Unconditionally halt this CPU */
	mov	r0, #FLOW_CTRL_WAITEVENT
	str	r0, [r6, +r1]
	ldr	r0, [r6, +r1]			@ memory barrier

	dsb
	isb
	wfi					@ CPU should be power gated here

	/* If the CPU didn't power gate above just kill it's clock. */

	mov	r0, r11, lsl #8
	str	r0, [r7, #348]			@ CLK_CPU_CMPLX_SET
#endif

	/* If the CPU still isn't dead, just spin here. */
	b	.
ENDPROC(__tegra_cpu_reset_handler)

	.align L1_CACHE_SHIFT
	.type	__tegra_cpu_reset_handler_data, %object
	.globl	__tegra_cpu_reset_handler_data
__tegra_cpu_reset_handler_data:
	.rept	TEGRA_RESET_DATA_SIZE
	.long	0
	.endr
	.align L1_CACHE_SHIFT

ENTRY(__tegra_cpu_reset_handler_end)
Commit	Line	Data
9e32366f JL	1	/*
	2	* Copyright (c) 2012, NVIDIA Corporation. All rights reserved.
	3	*
	4	* This program is free software; you can redistribute it and/or modify it
	5	* under the terms and conditions of the GNU General Public License,
	6	* version 2, as published by the Free Software Foundation.
	7	*
	8	* This program is distributed in the hope it will be useful, but WITHOUT
	9	* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
	10	* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
	11	* more details.
	12	*
	13	* You should have received a copy of the GNU General Public License
	14	* along with this program. If not, see <http://www.gnu.org/licenses/>.
	15	*/
	16
	17	#include <linux/linkage.h>
	18	#include <linux/init.h>
	19
	20	#include <asm/cache.h>
	21	#include <asm/asm-offsets.h>
	22	#include <asm/hardware/cache-l2x0.h>
	23
	24	#include "flowctrl.h"
4b3e2eda	25	#include "fuse.h"
9e32366f JL	26	#include "iomap.h"
	27	#include "reset.h"
	28	#include "sleep.h"
	29
9e32366f JL	30	#define PMC_SCRATCH41 0x140
	31
	32	#define RESET_DATA(x) ((TEGRA_RESET_##x)*4)
	33
	34	#ifdef CONFIG_PM_SLEEP
	35	/*
	36	* tegra_resume
	37	*
	38	* CPU boot vector when restarting the a CPU following
	39	* an LP2 transition. Also branched to by LP0 and LP1 resume after
	40	* re-enabling sdram.
33d5c019 JL	41	*
33d5c019 JL	42	* r6: SoC ID
9e32366f JL	43	*/
	44	ENTRY(tegra_resume)
	45	bl v7_invalidate_l1
9e32366f JL	46
9e32366f JL	47	cpu_id r0
33d5c019 JL	48	tegra_get_soc_id TEGRA_APB_MISC_BASE, r6
	49	cmp r6, #TEGRA114
	50	beq no_cpu0_chk
	51
9e32366f	52	cmp r0, #0 @ CPU0?
a65dc10f	53	THUMB( it ne )
9e32366f	54	bne cpu_resume @ no
33d5c019	55	no_cpu0_chk:
9e32366f	56
ecc4d9da	57	#ifndef CONFIG_ARCH_TEGRA_2x_SOC
9e32366f	58	/* Are we on Tegra20? */
4b3e2eda	59	cmp r6, #TEGRA20
9e32366f JL	60	beq 1f @ Yes
9e32366f JL	61	/* Clear the flow controller flags for this CPU. */
ecc4d9da JL	62	cpu_to_csr_req r1, r0
	63	mov32 r2, TEGRA_FLOW_CTRL_BASE
	64	ldr r1, [r2, r1]
9e32366f JL	65	/* Clear event & intr flag */
	66	orr r1, r1, \
	67	#FLOW_CTRL_CSR_INTR_FLAG \| FLOW_CTRL_CSR_EVENT_FLAG
ecc4d9da JL	68	movw r0, #0x3FFD @ enable, cluster_switch, immed, bitmaps
ecc4d9da JL	69	@ & ext flags for CPU power mgnt
9e32366f JL	70	bic r1, r1, r0
	71	str r1, [r2]
	72	1:
	73	#endif
	74
ecc4d9da JL	75	check_cpu_part_num 0xc09, r8, r9
ecc4d9da JL	76	bne not_ca9
9e32366f JL	77	#ifdef CONFIG_HAVE_ARM_SCU
	78	/* enable SCU */
	79	mov32 r0, TEGRA_ARM_PERIF_BASE
	80	ldr r1, [r0]
	81	orr r1, r1, #1
	82	str r1, [r0]
	83	#endif
	84
	85	/* L2 cache resume & re-enable */
	86	l2_cache_resume r0, r1, r2, l2x0_saved_regs_addr
ecc4d9da	87	not_ca9:
9e32366f JL	88
	89	b cpu_resume
	90	ENDPROC(tegra_resume)
	91	#endif
	92
	93	#ifdef CONFIG_CACHE_L2X0
	94	.globl l2x0_saved_regs_addr
	95	l2x0_saved_regs_addr:
	96	.long 0
	97	#endif
	98
	99	.align L1_CACHE_SHIFT
	100	ENTRY(__tegra_cpu_reset_handler_start)
	101
	102	/*
	103	* __tegra_cpu_reset_handler:
	104	*
	105	* Common handler for all CPU reset events.
	106	*
	107	* Register usage within the reset handler:
	108	*
c34f30e5	109	* Others: scratch
4b3e2eda	110	* R6 = SoC ID
9e32366f JL	111	* R7 = CPU present (to the OS) mask
	112	* R8 = CPU in LP1 state mask
	113	* R9 = CPU in LP2 state mask
	114	* R10 = CPU number
	115	* R11 = CPU mask
	116	* R12 = pointer to reset handler data
	117	*
	118	* NOTE: This code is copied to IRAM. All code and data accesses
	119	* must be position-independent.
	120	*/
	121
	122	.align L1_CACHE_SHIFT
	123	ENTRY(__tegra_cpu_reset_handler)
	124
	125	cpsid aif, 0x13 @ SVC mode, interrupts disabled
c34f30e5	126
4b3e2eda	127	tegra_get_soc_id TEGRA_APB_MISC_BASE, r6
c34f30e5 SW	128	#ifdef CONFIG_ARCH_TEGRA_2x_SOC
c34f30e5 SW	129	t20_check:
4b3e2eda	130	cmp r6, #TEGRA20
c34f30e5 SW	131	bne after_t20_check
	132	t20_errata:
	133	# Tegra20 is a Cortex-A9 r1p1
	134	mrc p15, 0, r0, c1, c0, 0 @ read system control register
	135	orr r0, r0, #1 << 14 @ erratum 716044
	136	mcr p15, 0, r0, c1, c0, 0 @ write system control register
	137	mrc p15, 0, r0, c15, c0, 1 @ read diagnostic register
	138	orr r0, r0, #1 << 4 @ erratum 742230
	139	orr r0, r0, #1 << 11 @ erratum 751472
	140	mcr p15, 0, r0, c15, c0, 1 @ write diagnostic register
	141	b after_errata
	142	after_t20_check:
	143	#endif
	144	#ifdef CONFIG_ARCH_TEGRA_3x_SOC
	145	t30_check:
4b3e2eda	146	cmp r6, #TEGRA30
c34f30e5 SW	147	bne after_t30_check
	148	t30_errata:
	149	# Tegra30 is a Cortex-A9 r2p9
	150	mrc p15, 0, r0, c15, c0, 1 @ read diagnostic register
	151	orr r0, r0, #1 << 6 @ erratum 743622
	152	orr r0, r0, #1 << 11 @ erratum 751472
	153	mcr p15, 0, r0, c15, c0, 1 @ write diagnostic register
	154	b after_errata
	155	after_t30_check:
	156	#endif
	157	after_errata:
9e32366f JL	158	mrc p15, 0, r10, c0, c0, 5 @ MPIDR
	159	and r10, r10, #0x3 @ R10 = CPU number
	160	mov r11, #1
	161	mov r11, r11, lsl r10 @ R11 = CPU mask
	162	adr r12, __tegra_cpu_reset_handler_data
	163
	164	#ifdef CONFIG_SMP
	165	/* Does the OS know about this CPU? */
	166	ldr r7, [r12, #RESET_DATA(MASK_PRESENT)]
	167	tst r7, r11 @ if !present
	168	bleq __die @ CPU not present (to OS)
	169	#endif
	170
	171	#ifdef CONFIG_ARCH_TEGRA_2x_SOC
	172	/* Are we on Tegra20? */
4b3e2eda	173	cmp r6, #TEGRA20
9e32366f JL	174	bne 1f
9e32366f JL	175	/* If not CPU0, don't let CPU0 reset CPU1 now that CPU1 is coming up. */
c34f30e5	176	mov32 r5, TEGRA_PMC_BASE
9e32366f JL	177	mov r0, #0
9e32366f JL	178	cmp r10, #0
c34f30e5	179	strne r0, [r5, #PMC_SCRATCH41]
9e32366f JL	180	1:
	181	#endif
	182
	183	/* Waking up from LP2? */
	184	ldr r9, [r12, #RESET_DATA(MASK_LP2)]
	185	tst r9, r11 @ if in_lp2
	186	beq __is_not_lp2
	187	ldr lr, [r12, #RESET_DATA(STARTUP_LP2)]
	188	cmp lr, #0
	189	bleq __die @ no LP2 startup handler
	190	bx lr
	191
	192	__is_not_lp2:
	193
	194	#ifdef CONFIG_SMP
	195	/*
33d5c019 JL	196	* Can only be secondary boot (initial or hotplug)
33d5c019 JL	197	* CPU0 can't be here for Tegra20/30
9e32366f	198	*/
33d5c019 JL	199	cmp r6, #TEGRA114
33d5c019 JL	200	beq __no_cpu0_chk
9e32366f JL	201	cmp r10, #0
9e32366f JL	202	bleq __die @ CPU0 cannot be here
33d5c019	203	__no_cpu0_chk:
9e32366f JL	204	ldr lr, [r12, #RESET_DATA(STARTUP_SECONDARY)]
	205	cmp lr, #0
	206	bleq __die @ no secondary startup handler
	207	bx lr
	208	#endif
	209
	210	/*
	211	* We don't know why the CPU reset. Just kill it.
	212	* The LR register will contain the address we died at + 4.
	213	*/
	214
	215	__die:
	216	sub lr, lr, #4
	217	mov32 r7, TEGRA_PMC_BASE
	218	str lr, [r7, #PMC_SCRATCH41]
	219
	220	mov32 r7, TEGRA_CLK_RESET_BASE
	221
	222	/* Are we on Tegra20? */
4b3e2eda	223	cmp r6, #TEGRA20
9e32366f JL	224	bne 1f
	225
	226	#ifdef CONFIG_ARCH_TEGRA_2x_SOC
	227	mov32 r0, 0x1111
	228	mov r1, r0, lsl r10
	229	str r1, [r7, #0x340] @ CLK_RST_CPU_CMPLX_SET
	230	#endif
	231	1:
	232	#ifdef CONFIG_ARCH_TEGRA_3x_SOC
	233	mov32 r6, TEGRA_FLOW_CTRL_BASE
	234
	235	cmp r10, #0
	236	moveq r1, #FLOW_CTRL_HALT_CPU0_EVENTS
	237	moveq r2, #FLOW_CTRL_CPU0_CSR
	238	movne r1, r10, lsl #3
	239	addne r2, r1, #(FLOW_CTRL_CPU1_CSR-8)
	240	addne r1, r1, #(FLOW_CTRL_HALT_CPU1_EVENTS-8)
	241
	242	/* Clear CPU "event" and "interrupt" flags and power gate
	243	it when halting but not before it is in the "WFI" state. */
	244	ldr r0, [r6, +r2]
	245	orr r0, r0, #FLOW_CTRL_CSR_INTR_FLAG \| FLOW_CTRL_CSR_EVENT_FLAG
	246	orr r0, r0, #FLOW_CTRL_CSR_ENABLE
	247	str r0, [r6, +r2]
	248
	249	/* Unconditionally halt this CPU */
	250	mov r0, #FLOW_CTRL_WAITEVENT
	251	str r0, [r6, +r1]
	252	ldr r0, [r6, +r1] @ memory barrier
	253
	254	dsb
	255	isb
	256	wfi @ CPU should be power gated here
	257
	258	/* If the CPU didn't power gate above just kill it's clock. */
	259
	260	mov r0, r11, lsl #8
	261	str r0, [r7, #348] @ CLK_CPU_CMPLX_SET
	262	#endif
	263
	264	/* If the CPU still isn't dead, just spin here. */
	265	b .
	266	ENDPROC(__tegra_cpu_reset_handler)
	267
	268	.align L1_CACHE_SHIFT
	269	.type __tegra_cpu_reset_handler_data, %object
	270	.globl __tegra_cpu_reset_handler_data
	271	__tegra_cpu_reset_handler_data:
	272	.rept TEGRA_RESET_DATA_SIZE
	273	.long 0
	274	.endr
	275	.align L1_CACHE_SHIFT
	276
	277	ENTRY(__tegra_cpu_reset_handler_end)