[deliverable/linux.git] / arch / arm / mach-tegra / reset-handler.S

/*
 * Copyright (c) 2012, NVIDIA Corporation. All rights reserved.
 *
 * This program is free software; you can redistribute it and/or modify it
 * under the terms and conditions of the GNU General Public License,
 * version 2, as published by the Free Software Foundation.
 *
 * This program is distributed in the hope it will be useful, but WITHOUT
 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
 * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
 * more details.
 *
 * You should have received a copy of the GNU General Public License
 * along with this program.  If not, see <http://www.gnu.org/licenses/>.
 */

#include <linux/linkage.h>
#include <linux/init.h>

#include <asm/cache.h>
#include <asm/asm-offsets.h>
#include <asm/hardware/cache-l2x0.h>

#include "flowctrl.h"
#include "iomap.h"
#include "reset.h"
#include "sleep.h"

#define APB_MISC_GP_HIDREV	0x804
#define PMC_SCRATCH41	0x140

#define RESET_DATA(x)	((TEGRA_RESET_##x)*4)

#ifdef CONFIG_PM_SLEEP
/*
 *	tegra_resume
 *
 *	  CPU boot vector when restarting the a CPU following
 *	  an LP2 transition. Also branched to by LP0 and LP1 resume after
 *	  re-enabling sdram.
 */
ENTRY(tegra_resume)
	bl	v7_invalidate_l1

	cpu_id	r0
	cmp	r0, #0				@ CPU0?
	bne	cpu_resume			@ no

#ifdef CONFIG_ARCH_TEGRA_3x_SOC
	/* Are we on Tegra20? */
	mov32	r6, TEGRA_APB_MISC_BASE
	ldr	r0, [r6, #APB_MISC_GP_HIDREV]
	and	r0, r0, #0xff00
	cmp	r0, #(0x20 << 8)
	beq	1f				@ Yes
	/* Clear the flow controller flags for this CPU. */
	mov32	r2, TEGRA_FLOW_CTRL_BASE + FLOW_CTRL_CPU0_CSR	@ CPU0 CSR
	ldr	r1, [r2]
	/* Clear event & intr flag */
	orr	r1, r1, \
		#FLOW_CTRL_CSR_INTR_FLAG | FLOW_CTRL_CSR_EVENT_FLAG
	movw	r0, #0x0FFD	@ enable, cluster_switch, immed, & bitmaps
	bic	r1, r1, r0
	str	r1, [r2]
1:
#endif

#ifdef CONFIG_HAVE_ARM_SCU
	/* enable SCU */
	mov32	r0, TEGRA_ARM_PERIF_BASE
	ldr	r1, [r0]
	orr	r1, r1, #1
	str	r1, [r0]
#endif

	/* L2 cache resume & re-enable */
	l2_cache_resume r0, r1, r2, l2x0_saved_regs_addr

	b	cpu_resume
ENDPROC(tegra_resume)
#endif

#ifdef CONFIG_CACHE_L2X0
	.globl	l2x0_saved_regs_addr
l2x0_saved_regs_addr:
	.long	0
#endif

	.align L1_CACHE_SHIFT
ENTRY(__tegra_cpu_reset_handler_start)

/*
 * __tegra_cpu_reset_handler:
 *
 * Common handler for all CPU reset events.
 *
 * Register usage within the reset handler:
 *
 *      Others: scratch
 *      R6  = SoC ID << 8
 *      R7  = CPU present (to the OS) mask
 *      R8  = CPU in LP1 state mask
 *      R9  = CPU in LP2 state mask
 *      R10 = CPU number
 *      R11 = CPU mask
 *      R12 = pointer to reset handler data
 *
 * NOTE: This code is copied to IRAM. All code and data accesses
 *       must be position-independent.
 */

	.align L1_CACHE_SHIFT
ENTRY(__tegra_cpu_reset_handler)

	cpsid	aif, 0x13			@ SVC mode, interrupts disabled

	mov32	r6, TEGRA_APB_MISC_BASE
	ldr	r6, [r6, #APB_MISC_GP_HIDREV]
	and	r6, r6, #0xff00
#ifdef CONFIG_ARCH_TEGRA_2x_SOC
t20_check:
	cmp	r6, #(0x20 << 8)
	bne	after_t20_check
t20_errata:
	# Tegra20 is a Cortex-A9 r1p1
	mrc	p15, 0, r0, c1, c0, 0   @ read system control register
	orr	r0, r0, #1 << 14        @ erratum 716044
	mcr	p15, 0, r0, c1, c0, 0   @ write system control register
	mrc	p15, 0, r0, c15, c0, 1  @ read diagnostic register
	orr	r0, r0, #1 << 4         @ erratum 742230
	orr	r0, r0, #1 << 11        @ erratum 751472
	mcr	p15, 0, r0, c15, c0, 1  @ write diagnostic register
	b	after_errata
after_t20_check:
#endif
#ifdef CONFIG_ARCH_TEGRA_3x_SOC
t30_check:
	cmp	r6, #(0x30 << 8)
	bne	after_t30_check
t30_errata:
	# Tegra30 is a Cortex-A9 r2p9
	mrc	p15, 0, r0, c15, c0, 1  @ read diagnostic register
	orr	r0, r0, #1 << 6         @ erratum 743622
	orr	r0, r0, #1 << 11        @ erratum 751472
	mcr	p15, 0, r0, c15, c0, 1  @ write diagnostic register
	b	after_errata
after_t30_check:
#endif
after_errata:
	mrc	p15, 0, r10, c0, c0, 5		@ MPIDR
	and	r10, r10, #0x3			@ R10 = CPU number
	mov	r11, #1
	mov	r11, r11, lsl r10  		@ R11 = CPU mask
	adr	r12, __tegra_cpu_reset_handler_data

#ifdef CONFIG_SMP
	/* Does the OS know about this CPU? */
	ldr	r7, [r12, #RESET_DATA(MASK_PRESENT)]
	tst	r7, r11 			@ if !present
	bleq	__die				@ CPU not present (to OS)
#endif

#ifdef CONFIG_ARCH_TEGRA_2x_SOC
	/* Are we on Tegra20? */
	cmp	r6, #(0x20 << 8)
	bne	1f
	/* If not CPU0, don't let CPU0 reset CPU1 now that CPU1 is coming up. */
	mov32	r5, TEGRA_PMC_BASE
	mov	r0, #0
	cmp	r10, #0
	strne	r0, [r5, #PMC_SCRATCH41]
1:
#endif

	/* Waking up from LP2? */
	ldr	r9, [r12, #RESET_DATA(MASK_LP2)]
	tst	r9, r11				@ if in_lp2
	beq	__is_not_lp2
	ldr	lr, [r12, #RESET_DATA(STARTUP_LP2)]
	cmp	lr, #0
	bleq	__die				@ no LP2 startup handler
	bx	lr

__is_not_lp2:

#ifdef CONFIG_SMP
	/*
	 * Can only be secondary boot (initial or hotplug) but CPU 0
	 * cannot be here.
	 */
	cmp	r10, #0
	bleq	__die				@ CPU0 cannot be here
	ldr	lr, [r12, #RESET_DATA(STARTUP_SECONDARY)]
	cmp	lr, #0
	bleq	__die				@ no secondary startup handler
	bx	lr
#endif

/*
 * We don't know why the CPU reset. Just kill it.
 * The LR register will contain the address we died at + 4.
 */

__die:
	sub	lr, lr, #4
	mov32	r7, TEGRA_PMC_BASE
	str	lr, [r7, #PMC_SCRATCH41]

	mov32	r7, TEGRA_CLK_RESET_BASE

	/* Are we on Tegra20? */
	mov32	r6, TEGRA_APB_MISC_BASE
	ldr	r0, [r6, #APB_MISC_GP_HIDREV]
	and	r0, r0, #0xff00
	cmp	r0, #(0x20 << 8)
	bne	1f

#ifdef CONFIG_ARCH_TEGRA_2x_SOC
	mov32	r0, 0x1111
	mov	r1, r0, lsl r10
	str	r1, [r7, #0x340]		@ CLK_RST_CPU_CMPLX_SET
#endif
1:
#ifdef CONFIG_ARCH_TEGRA_3x_SOC
	mov32	r6, TEGRA_FLOW_CTRL_BASE

	cmp	r10, #0
	moveq	r1, #FLOW_CTRL_HALT_CPU0_EVENTS
	moveq	r2, #FLOW_CTRL_CPU0_CSR
	movne	r1, r10, lsl #3
	addne	r2, r1, #(FLOW_CTRL_CPU1_CSR-8)
	addne	r1, r1, #(FLOW_CTRL_HALT_CPU1_EVENTS-8)

	/* Clear CPU "event" and "interrupt" flags and power gate
	   it when halting but not before it is in the "WFI" state. */
	ldr	r0, [r6, +r2]
	orr	r0, r0, #FLOW_CTRL_CSR_INTR_FLAG | FLOW_CTRL_CSR_EVENT_FLAG
	orr	r0, r0, #FLOW_CTRL_CSR_ENABLE
	str	r0, [r6, +r2]

	/* Unconditionally halt this CPU */
	mov	r0, #FLOW_CTRL_WAITEVENT
	str	r0, [r6, +r1]
	ldr	r0, [r6, +r1]			@ memory barrier

	dsb
	isb
	wfi					@ CPU should be power gated here

	/* If the CPU didn't power gate above just kill it's clock. */

	mov	r0, r11, lsl #8
	str	r0, [r7, #348]			@ CLK_CPU_CMPLX_SET
#endif

	/* If the CPU still isn't dead, just spin here. */
	b	.
ENDPROC(__tegra_cpu_reset_handler)

	.align L1_CACHE_SHIFT
	.type	__tegra_cpu_reset_handler_data, %object
	.globl	__tegra_cpu_reset_handler_data
__tegra_cpu_reset_handler_data:
	.rept	TEGRA_RESET_DATA_SIZE
	.long	0
	.endr
	.align L1_CACHE_SHIFT

ENTRY(__tegra_cpu_reset_handler_end)
Commit	Line	Data
9e32366f JL	1	/*
	2	* Copyright (c) 2012, NVIDIA Corporation. All rights reserved.
	3	*
	4	* This program is free software; you can redistribute it and/or modify it
	5	* under the terms and conditions of the GNU General Public License,
	6	* version 2, as published by the Free Software Foundation.
	7	*
	8	* This program is distributed in the hope it will be useful, but WITHOUT
	9	* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
	10	* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
	11	* more details.
	12	*
	13	* You should have received a copy of the GNU General Public License
	14	* along with this program. If not, see <http://www.gnu.org/licenses/>.
	15	*/
	16
	17	#include <linux/linkage.h>
	18	#include <linux/init.h>
	19
	20	#include <asm/cache.h>
	21	#include <asm/asm-offsets.h>
	22	#include <asm/hardware/cache-l2x0.h>
	23
	24	#include "flowctrl.h"
	25	#include "iomap.h"
	26	#include "reset.h"
	27	#include "sleep.h"
	28
	29	#define APB_MISC_GP_HIDREV 0x804
	30	#define PMC_SCRATCH41 0x140
	31
	32	#define RESET_DATA(x) ((TEGRA_RESET_##x)*4)
	33
	34	#ifdef CONFIG_PM_SLEEP
	35	/*
	36	* tegra_resume
	37	*
	38	* CPU boot vector when restarting the a CPU following
	39	* an LP2 transition. Also branched to by LP0 and LP1 resume after
	40	* re-enabling sdram.
	41	*/
	42	ENTRY(tegra_resume)
	43	bl v7_invalidate_l1
9e32366f JL	44
	45	cpu_id r0
	46	cmp r0, #0 @ CPU0?
	47	bne cpu_resume @ no
	48
	49	#ifdef CONFIG_ARCH_TEGRA_3x_SOC
	50	/* Are we on Tegra20? */
	51	mov32 r6, TEGRA_APB_MISC_BASE
	52	ldr r0, [r6, #APB_MISC_GP_HIDREV]
	53	and r0, r0, #0xff00
	54	cmp r0, #(0x20 << 8)
	55	beq 1f @ Yes
	56	/* Clear the flow controller flags for this CPU. */
	57	mov32 r2, TEGRA_FLOW_CTRL_BASE + FLOW_CTRL_CPU0_CSR @ CPU0 CSR
	58	ldr r1, [r2]
	59	/* Clear event & intr flag */
	60	orr r1, r1, \
	61	#FLOW_CTRL_CSR_INTR_FLAG \| FLOW_CTRL_CSR_EVENT_FLAG
	62	movw r0, #0x0FFD @ enable, cluster_switch, immed, & bitmaps
	63	bic r1, r1, r0
	64	str r1, [r2]
	65	1:
	66	#endif
	67
	68	#ifdef CONFIG_HAVE_ARM_SCU
	69	/* enable SCU */
	70	mov32 r0, TEGRA_ARM_PERIF_BASE
	71	ldr r1, [r0]
	72	orr r1, r1, #1
	73	str r1, [r0]
	74	#endif
	75
	76	/* L2 cache resume & re-enable */
	77	l2_cache_resume r0, r1, r2, l2x0_saved_regs_addr
	78
	79	b cpu_resume
	80	ENDPROC(tegra_resume)
	81	#endif
	82
	83	#ifdef CONFIG_CACHE_L2X0
	84	.globl l2x0_saved_regs_addr
	85	l2x0_saved_regs_addr:
	86	.long 0
	87	#endif
	88
	89	.align L1_CACHE_SHIFT
	90	ENTRY(__tegra_cpu_reset_handler_start)
	91
	92	/*
	93	* __tegra_cpu_reset_handler:
	94	*
	95	* Common handler for all CPU reset events.
	96	*
	97	* Register usage within the reset handler:
	98	*
c34f30e5 SW	99	* Others: scratch
c34f30e5 SW	100	* R6 = SoC ID << 8
9e32366f JL	101	* R7 = CPU present (to the OS) mask
	102	* R8 = CPU in LP1 state mask
	103	* R9 = CPU in LP2 state mask
	104	* R10 = CPU number
	105	* R11 = CPU mask
	106	* R12 = pointer to reset handler data
	107	*
	108	* NOTE: This code is copied to IRAM. All code and data accesses
	109	* must be position-independent.
	110	*/
	111
	112	.align L1_CACHE_SHIFT
	113	ENTRY(__tegra_cpu_reset_handler)
	114
	115	cpsid aif, 0x13 @ SVC mode, interrupts disabled
c34f30e5 SW	116
	117	mov32 r6, TEGRA_APB_MISC_BASE
	118	ldr r6, [r6, #APB_MISC_GP_HIDREV]
	119	and r6, r6, #0xff00
	120	#ifdef CONFIG_ARCH_TEGRA_2x_SOC
	121	t20_check:
	122	cmp r6, #(0x20 << 8)
	123	bne after_t20_check
	124	t20_errata:
	125	# Tegra20 is a Cortex-A9 r1p1
	126	mrc p15, 0, r0, c1, c0, 0 @ read system control register
	127	orr r0, r0, #1 << 14 @ erratum 716044
	128	mcr p15, 0, r0, c1, c0, 0 @ write system control register
	129	mrc p15, 0, r0, c15, c0, 1 @ read diagnostic register
	130	orr r0, r0, #1 << 4 @ erratum 742230
	131	orr r0, r0, #1 << 11 @ erratum 751472
	132	mcr p15, 0, r0, c15, c0, 1 @ write diagnostic register
	133	b after_errata
	134	after_t20_check:
	135	#endif
	136	#ifdef CONFIG_ARCH_TEGRA_3x_SOC
	137	t30_check:
	138	cmp r6, #(0x30 << 8)
	139	bne after_t30_check
	140	t30_errata:
	141	# Tegra30 is a Cortex-A9 r2p9
	142	mrc p15, 0, r0, c15, c0, 1 @ read diagnostic register
	143	orr r0, r0, #1 << 6 @ erratum 743622
	144	orr r0, r0, #1 << 11 @ erratum 751472
	145	mcr p15, 0, r0, c15, c0, 1 @ write diagnostic register
	146	b after_errata
	147	after_t30_check:
	148	#endif
	149	after_errata:
9e32366f JL	150	mrc p15, 0, r10, c0, c0, 5 @ MPIDR
	151	and r10, r10, #0x3 @ R10 = CPU number
	152	mov r11, #1
	153	mov r11, r11, lsl r10 @ R11 = CPU mask
	154	adr r12, __tegra_cpu_reset_handler_data
	155
	156	#ifdef CONFIG_SMP
	157	/* Does the OS know about this CPU? */
	158	ldr r7, [r12, #RESET_DATA(MASK_PRESENT)]
	159	tst r7, r11 @ if !present
	160	bleq __die @ CPU not present (to OS)
	161	#endif
	162
	163	#ifdef CONFIG_ARCH_TEGRA_2x_SOC
	164	/* Are we on Tegra20? */
c34f30e5	165	cmp r6, #(0x20 << 8)
9e32366f JL	166	bne 1f
9e32366f JL	167	/* If not CPU0, don't let CPU0 reset CPU1 now that CPU1 is coming up. */
c34f30e5	168	mov32 r5, TEGRA_PMC_BASE
9e32366f JL	169	mov r0, #0
9e32366f JL	170	cmp r10, #0
c34f30e5	171	strne r0, [r5, #PMC_SCRATCH41]
9e32366f JL	172	1:
	173	#endif
	174
	175	/* Waking up from LP2? */
	176	ldr r9, [r12, #RESET_DATA(MASK_LP2)]
	177	tst r9, r11 @ if in_lp2
	178	beq __is_not_lp2
	179	ldr lr, [r12, #RESET_DATA(STARTUP_LP2)]
	180	cmp lr, #0
	181	bleq __die @ no LP2 startup handler
	182	bx lr
	183
	184	__is_not_lp2:
	185
	186	#ifdef CONFIG_SMP
	187	/*
	188	* Can only be secondary boot (initial or hotplug) but CPU 0
	189	* cannot be here.
	190	*/
	191	cmp r10, #0
	192	bleq __die @ CPU0 cannot be here
	193	ldr lr, [r12, #RESET_DATA(STARTUP_SECONDARY)]
	194	cmp lr, #0
	195	bleq __die @ no secondary startup handler
	196	bx lr
	197	#endif
	198
	199	/*
	200	* We don't know why the CPU reset. Just kill it.
	201	* The LR register will contain the address we died at + 4.
	202	*/
	203
	204	__die:
	205	sub lr, lr, #4
	206	mov32 r7, TEGRA_PMC_BASE
	207	str lr, [r7, #PMC_SCRATCH41]
	208
	209	mov32 r7, TEGRA_CLK_RESET_BASE
	210
	211	/* Are we on Tegra20? */
	212	mov32 r6, TEGRA_APB_MISC_BASE
	213	ldr r0, [r6, #APB_MISC_GP_HIDREV]
	214	and r0, r0, #0xff00
	215	cmp r0, #(0x20 << 8)
	216	bne 1f
	217
	218	#ifdef CONFIG_ARCH_TEGRA_2x_SOC
	219	mov32 r0, 0x1111
	220	mov r1, r0, lsl r10
	221	str r1, [r7, #0x340] @ CLK_RST_CPU_CMPLX_SET
	222	#endif
	223	1:
	224	#ifdef CONFIG_ARCH_TEGRA_3x_SOC
	225	mov32 r6, TEGRA_FLOW_CTRL_BASE
	226
	227	cmp r10, #0
	228	moveq r1, #FLOW_CTRL_HALT_CPU0_EVENTS
	229	moveq r2, #FLOW_CTRL_CPU0_CSR
	230	movne r1, r10, lsl #3
	231	addne r2, r1, #(FLOW_CTRL_CPU1_CSR-8)
	232	addne r1, r1, #(FLOW_CTRL_HALT_CPU1_EVENTS-8)
	233
	234	/* Clear CPU "event" and "interrupt" flags and power gate
	235	it when halting but not before it is in the "WFI" state. */
236	ldr r0, [r6, +r2]
237	orr r0, r0, #FLOW_CTRL_CSR_INTR_FLAG \| FLOW_CTRL_CSR_EVENT_FLAG
238	orr r0, r0, #FLOW_CTRL_CSR_ENABLE
239	str r0, [r6, +r2]
240
241	/* Unconditionally halt this CPU */
242	mov r0, #FLOW_CTRL_WAITEVENT
243	str r0, [r6, +r1]
244	ldr r0, [r6, +r1] @ memory barrier
245
246	dsb
247	isb
248	wfi @ CPU should be power gated here
249
250	/* If the CPU didn't power gate above just kill it's clock. */
251
252	mov r0, r11, lsl #8
253	str r0, [r7, #348] @ CLK_CPU_CMPLX_SET
254	#endif
255
256	/* If the CPU still isn't dead, just spin here. */
257	b .
258	ENDPROC(__tegra_cpu_reset_handler)
259
260	.align L1_CACHE_SHIFT
261	.type __tegra_cpu_reset_handler_data, %object
262	.globl __tegra_cpu_reset_handler_data
263	__tegra_cpu_reset_handler_data:
264	.rept TEGRA_RESET_DATA_SIZE
265	.long 0
266	.endr
267	.align L1_CACHE_SHIFT
268
269	ENTRY(__tegra_cpu_reset_handler_end)