[deliverable/linux.git] / arch / arm / mach-tegra / reset-handler.S

/*
 * Copyright (c) 2012, NVIDIA Corporation. All rights reserved.
 *
 * This program is free software; you can redistribute it and/or modify it
 * under the terms and conditions of the GNU General Public License,
 * version 2, as published by the Free Software Foundation.
 *
 * This program is distributed in the hope it will be useful, but WITHOUT
 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
 * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
 * more details.
 *
 * You should have received a copy of the GNU General Public License
 * along with this program.  If not, see <http://www.gnu.org/licenses/>.
 */

#include <linux/linkage.h>
#include <linux/init.h>

#include <asm/cache.h>
#include <asm/asm-offsets.h>
#include <asm/hardware/cache-l2x0.h>

#include "flowctrl.h"
#include "fuse.h"
#include "iomap.h"
#include "reset.h"
#include "sleep.h"

#define PMC_SCRATCH41	0x140

#define RESET_DATA(x)	((TEGRA_RESET_##x)*4)

#ifdef CONFIG_PM_SLEEP
/*
 *	tegra_resume
 *
 *	  CPU boot vector when restarting the a CPU following
 *	  an LP2 transition. Also branched to by LP0 and LP1 resume after
 *	  re-enabling sdram.
 */
ENTRY(tegra_resume)
	bl	v7_invalidate_l1

	cpu_id	r0
	cmp	r0, #0				@ CPU0?
 THUMB(	it	ne )
	bne	cpu_resume			@ no

#ifdef CONFIG_ARCH_TEGRA_3x_SOC
	/* Are we on Tegra20? */
	tegra_get_soc_id TEGRA_APB_MISC_BASE, r6
	cmp	r6, #TEGRA20
	beq	1f				@ Yes
	/* Clear the flow controller flags for this CPU. */
	mov32	r2, TEGRA_FLOW_CTRL_BASE + FLOW_CTRL_CPU0_CSR	@ CPU0 CSR
	ldr	r1, [r2]
	/* Clear event & intr flag */
	orr	r1, r1, \
		#FLOW_CTRL_CSR_INTR_FLAG | FLOW_CTRL_CSR_EVENT_FLAG
	movw	r0, #0x0FFD	@ enable, cluster_switch, immed, & bitmaps
	bic	r1, r1, r0
	str	r1, [r2]
1:
#endif

#ifdef CONFIG_HAVE_ARM_SCU
	/* enable SCU */
	mov32	r0, TEGRA_ARM_PERIF_BASE
	ldr	r1, [r0]
	orr	r1, r1, #1
	str	r1, [r0]
#endif

	/* L2 cache resume & re-enable */
	l2_cache_resume r0, r1, r2, l2x0_saved_regs_addr

	b	cpu_resume
ENDPROC(tegra_resume)
#endif

#ifdef CONFIG_CACHE_L2X0
	.globl	l2x0_saved_regs_addr
l2x0_saved_regs_addr:
	.long	0
#endif

	.align L1_CACHE_SHIFT
ENTRY(__tegra_cpu_reset_handler_start)

/*
 * __tegra_cpu_reset_handler:
 *
 * Common handler for all CPU reset events.
 *
 * Register usage within the reset handler:
 *
 *      Others: scratch
 *      R6  = SoC ID
 *      R7  = CPU present (to the OS) mask
 *      R8  = CPU in LP1 state mask
 *      R9  = CPU in LP2 state mask
 *      R10 = CPU number
 *      R11 = CPU mask
 *      R12 = pointer to reset handler data
 *
 * NOTE: This code is copied to IRAM. All code and data accesses
 *       must be position-independent.
 */

	.align L1_CACHE_SHIFT
ENTRY(__tegra_cpu_reset_handler)

	cpsid	aif, 0x13			@ SVC mode, interrupts disabled

	tegra_get_soc_id TEGRA_APB_MISC_BASE, r6
#ifdef CONFIG_ARCH_TEGRA_2x_SOC
t20_check:
	cmp	r6, #TEGRA20
	bne	after_t20_check
t20_errata:
	# Tegra20 is a Cortex-A9 r1p1
	mrc	p15, 0, r0, c1, c0, 0   @ read system control register
	orr	r0, r0, #1 << 14        @ erratum 716044
	mcr	p15, 0, r0, c1, c0, 0   @ write system control register
	mrc	p15, 0, r0, c15, c0, 1  @ read diagnostic register
	orr	r0, r0, #1 << 4         @ erratum 742230
	orr	r0, r0, #1 << 11        @ erratum 751472
	mcr	p15, 0, r0, c15, c0, 1  @ write diagnostic register
	b	after_errata
after_t20_check:
#endif
#ifdef CONFIG_ARCH_TEGRA_3x_SOC
t30_check:
	cmp	r6, #TEGRA30
	bne	after_t30_check
t30_errata:
	# Tegra30 is a Cortex-A9 r2p9
	mrc	p15, 0, r0, c15, c0, 1  @ read diagnostic register
	orr	r0, r0, #1 << 6         @ erratum 743622
	orr	r0, r0, #1 << 11        @ erratum 751472
	mcr	p15, 0, r0, c15, c0, 1  @ write diagnostic register
	b	after_errata
after_t30_check:
#endif
after_errata:
	mrc	p15, 0, r10, c0, c0, 5		@ MPIDR
	and	r10, r10, #0x3			@ R10 = CPU number
	mov	r11, #1
	mov	r11, r11, lsl r10  		@ R11 = CPU mask
	adr	r12, __tegra_cpu_reset_handler_data

#ifdef CONFIG_SMP
	/* Does the OS know about this CPU? */
	ldr	r7, [r12, #RESET_DATA(MASK_PRESENT)]
	tst	r7, r11 			@ if !present
	bleq	__die				@ CPU not present (to OS)
#endif

#ifdef CONFIG_ARCH_TEGRA_2x_SOC
	/* Are we on Tegra20? */
	cmp	r6, #TEGRA20
	bne	1f
	/* If not CPU0, don't let CPU0 reset CPU1 now that CPU1 is coming up. */
	mov32	r5, TEGRA_PMC_BASE
	mov	r0, #0
	cmp	r10, #0
	strne	r0, [r5, #PMC_SCRATCH41]
1:
#endif

	/* Waking up from LP2? */
	ldr	r9, [r12, #RESET_DATA(MASK_LP2)]
	tst	r9, r11				@ if in_lp2
	beq	__is_not_lp2
	ldr	lr, [r12, #RESET_DATA(STARTUP_LP2)]
	cmp	lr, #0
	bleq	__die				@ no LP2 startup handler
	bx	lr

__is_not_lp2:

#ifdef CONFIG_SMP
	/*
	 * Can only be secondary boot (initial or hotplug) but CPU 0
	 * cannot be here.
	 */
	cmp	r10, #0
	bleq	__die				@ CPU0 cannot be here
	ldr	lr, [r12, #RESET_DATA(STARTUP_SECONDARY)]
	cmp	lr, #0
	bleq	__die				@ no secondary startup handler
	bx	lr
#endif

/*
 * We don't know why the CPU reset. Just kill it.
 * The LR register will contain the address we died at + 4.
 */

__die:
	sub	lr, lr, #4
	mov32	r7, TEGRA_PMC_BASE
	str	lr, [r7, #PMC_SCRATCH41]

	mov32	r7, TEGRA_CLK_RESET_BASE

	/* Are we on Tegra20? */
	cmp	r6, #TEGRA20
	bne	1f

#ifdef CONFIG_ARCH_TEGRA_2x_SOC
	mov32	r0, 0x1111
	mov	r1, r0, lsl r10
	str	r1, [r7, #0x340]		@ CLK_RST_CPU_CMPLX_SET
#endif
1:
#ifdef CONFIG_ARCH_TEGRA_3x_SOC
	mov32	r6, TEGRA_FLOW_CTRL_BASE

	cmp	r10, #0
	moveq	r1, #FLOW_CTRL_HALT_CPU0_EVENTS
	moveq	r2, #FLOW_CTRL_CPU0_CSR
	movne	r1, r10, lsl #3
	addne	r2, r1, #(FLOW_CTRL_CPU1_CSR-8)
	addne	r1, r1, #(FLOW_CTRL_HALT_CPU1_EVENTS-8)

	/* Clear CPU "event" and "interrupt" flags and power gate
	   it when halting but not before it is in the "WFI" state. */
	ldr	r0, [r6, +r2]
	orr	r0, r0, #FLOW_CTRL_CSR_INTR_FLAG | FLOW_CTRL_CSR_EVENT_FLAG
	orr	r0, r0, #FLOW_CTRL_CSR_ENABLE
	str	r0, [r6, +r2]

	/* Unconditionally halt this CPU */
	mov	r0, #FLOW_CTRL_WAITEVENT
	str	r0, [r6, +r1]
	ldr	r0, [r6, +r1]			@ memory barrier

	dsb
	isb
	wfi					@ CPU should be power gated here

	/* If the CPU didn't power gate above just kill it's clock. */

	mov	r0, r11, lsl #8
	str	r0, [r7, #348]			@ CLK_CPU_CMPLX_SET
#endif

	/* If the CPU still isn't dead, just spin here. */
	b	.
ENDPROC(__tegra_cpu_reset_handler)

	.align L1_CACHE_SHIFT
	.type	__tegra_cpu_reset_handler_data, %object
	.globl	__tegra_cpu_reset_handler_data
__tegra_cpu_reset_handler_data:
	.rept	TEGRA_RESET_DATA_SIZE
	.long	0
	.endr
	.align L1_CACHE_SHIFT

ENTRY(__tegra_cpu_reset_handler_end)
Commit	Line	Data
9e32366f JL	1	/*
	2	* Copyright (c) 2012, NVIDIA Corporation. All rights reserved.
	3	*
	4	* This program is free software; you can redistribute it and/or modify it
	5	* under the terms and conditions of the GNU General Public License,
	6	* version 2, as published by the Free Software Foundation.
	7	*
	8	* This program is distributed in the hope it will be useful, but WITHOUT
	9	* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
	10	* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
	11	* more details.
	12	*
	13	* You should have received a copy of the GNU General Public License
	14	* along with this program. If not, see <http://www.gnu.org/licenses/>.
	15	*/
	16
	17	#include <linux/linkage.h>
	18	#include <linux/init.h>
	19
	20	#include <asm/cache.h>
	21	#include <asm/asm-offsets.h>
	22	#include <asm/hardware/cache-l2x0.h>
	23
	24	#include "flowctrl.h"
4b3e2eda	25	#include "fuse.h"
9e32366f JL	26	#include "iomap.h"
	27	#include "reset.h"
	28	#include "sleep.h"
	29
9e32366f JL	30	#define PMC_SCRATCH41 0x140
	31
	32	#define RESET_DATA(x) ((TEGRA_RESET_##x)*4)
	33
	34	#ifdef CONFIG_PM_SLEEP
	35	/*
	36	* tegra_resume
	37	*
	38	* CPU boot vector when restarting the a CPU following
	39	* an LP2 transition. Also branched to by LP0 and LP1 resume after
	40	* re-enabling sdram.
	41	*/
	42	ENTRY(tegra_resume)
	43	bl v7_invalidate_l1
9e32366f JL	44
	45	cpu_id r0
	46	cmp r0, #0 @ CPU0?
a65dc10f	47	THUMB( it ne )
9e32366f JL	48	bne cpu_resume @ no
	49
	50	#ifdef CONFIG_ARCH_TEGRA_3x_SOC
	51	/* Are we on Tegra20? */
4b3e2eda JL	52	tegra_get_soc_id TEGRA_APB_MISC_BASE, r6
4b3e2eda JL	53	cmp r6, #TEGRA20
9e32366f JL	54	beq 1f @ Yes
	55	/* Clear the flow controller flags for this CPU. */
	56	mov32 r2, TEGRA_FLOW_CTRL_BASE + FLOW_CTRL_CPU0_CSR @ CPU0 CSR
	57	ldr r1, [r2]
	58	/* Clear event & intr flag */
	59	orr r1, r1, \
	60	#FLOW_CTRL_CSR_INTR_FLAG \| FLOW_CTRL_CSR_EVENT_FLAG
	61	movw r0, #0x0FFD @ enable, cluster_switch, immed, & bitmaps
	62	bic r1, r1, r0
	63	str r1, [r2]
	64	1:
	65	#endif
	66
	67	#ifdef CONFIG_HAVE_ARM_SCU
	68	/* enable SCU */
	69	mov32 r0, TEGRA_ARM_PERIF_BASE
	70	ldr r1, [r0]
	71	orr r1, r1, #1
	72	str r1, [r0]
	73	#endif
	74
	75	/* L2 cache resume & re-enable */
	76	l2_cache_resume r0, r1, r2, l2x0_saved_regs_addr
	77
	78	b cpu_resume
	79	ENDPROC(tegra_resume)
	80	#endif
	81
	82	#ifdef CONFIG_CACHE_L2X0
	83	.globl l2x0_saved_regs_addr
	84	l2x0_saved_regs_addr:
	85	.long 0
	86	#endif
	87
	88	.align L1_CACHE_SHIFT
	89	ENTRY(__tegra_cpu_reset_handler_start)
	90
	91	/*
	92	* __tegra_cpu_reset_handler:
	93	*
	94	* Common handler for all CPU reset events.
	95	*
	96	* Register usage within the reset handler:
	97	*
c34f30e5	98	* Others: scratch
4b3e2eda	99	* R6 = SoC ID
9e32366f JL	100	* R7 = CPU present (to the OS) mask
	101	* R8 = CPU in LP1 state mask
	102	* R9 = CPU in LP2 state mask
	103	* R10 = CPU number
	104	* R11 = CPU mask
	105	* R12 = pointer to reset handler data
	106	*
	107	* NOTE: This code is copied to IRAM. All code and data accesses
	108	* must be position-independent.
	109	*/
	110
	111	.align L1_CACHE_SHIFT
	112	ENTRY(__tegra_cpu_reset_handler)
	113
	114	cpsid aif, 0x13 @ SVC mode, interrupts disabled
c34f30e5	115
4b3e2eda	116	tegra_get_soc_id TEGRA_APB_MISC_BASE, r6
c34f30e5 SW	117	#ifdef CONFIG_ARCH_TEGRA_2x_SOC
c34f30e5 SW	118	t20_check:
4b3e2eda	119	cmp r6, #TEGRA20
c34f30e5 SW	120	bne after_t20_check
	121	t20_errata:
	122	# Tegra20 is a Cortex-A9 r1p1
	123	mrc p15, 0, r0, c1, c0, 0 @ read system control register
	124	orr r0, r0, #1 << 14 @ erratum 716044
	125	mcr p15, 0, r0, c1, c0, 0 @ write system control register
	126	mrc p15, 0, r0, c15, c0, 1 @ read diagnostic register
	127	orr r0, r0, #1 << 4 @ erratum 742230
	128	orr r0, r0, #1 << 11 @ erratum 751472
	129	mcr p15, 0, r0, c15, c0, 1 @ write diagnostic register
	130	b after_errata
	131	after_t20_check:
	132	#endif
	133	#ifdef CONFIG_ARCH_TEGRA_3x_SOC
	134	t30_check:
4b3e2eda	135	cmp r6, #TEGRA30
c34f30e5 SW	136	bne after_t30_check
	137	t30_errata:
	138	# Tegra30 is a Cortex-A9 r2p9
	139	mrc p15, 0, r0, c15, c0, 1 @ read diagnostic register
	140	orr r0, r0, #1 << 6 @ erratum 743622
	141	orr r0, r0, #1 << 11 @ erratum 751472
	142	mcr p15, 0, r0, c15, c0, 1 @ write diagnostic register
	143	b after_errata
	144	after_t30_check:
	145	#endif
	146	after_errata:
9e32366f JL	147	mrc p15, 0, r10, c0, c0, 5 @ MPIDR
	148	and r10, r10, #0x3 @ R10 = CPU number
	149	mov r11, #1
	150	mov r11, r11, lsl r10 @ R11 = CPU mask
	151	adr r12, __tegra_cpu_reset_handler_data
	152
	153	#ifdef CONFIG_SMP
	154	/* Does the OS know about this CPU? */
	155	ldr r7, [r12, #RESET_DATA(MASK_PRESENT)]
	156	tst r7, r11 @ if !present
	157	bleq __die @ CPU not present (to OS)
	158	#endif
	159
	160	#ifdef CONFIG_ARCH_TEGRA_2x_SOC
	161	/* Are we on Tegra20? */
4b3e2eda	162	cmp r6, #TEGRA20
9e32366f JL	163	bne 1f
9e32366f JL	164	/* If not CPU0, don't let CPU0 reset CPU1 now that CPU1 is coming up. */
c34f30e5	165	mov32 r5, TEGRA_PMC_BASE
9e32366f JL	166	mov r0, #0
9e32366f JL	167	cmp r10, #0
c34f30e5	168	strne r0, [r5, #PMC_SCRATCH41]
9e32366f JL	169	1:
	170	#endif
	171
	172	/* Waking up from LP2? */
	173	ldr r9, [r12, #RESET_DATA(MASK_LP2)]
	174	tst r9, r11 @ if in_lp2
	175	beq __is_not_lp2
	176	ldr lr, [r12, #RESET_DATA(STARTUP_LP2)]
	177	cmp lr, #0
	178	bleq __die @ no LP2 startup handler
	179	bx lr
	180
	181	__is_not_lp2:
	182
	183	#ifdef CONFIG_SMP
	184	/*
	185	* Can only be secondary boot (initial or hotplug) but CPU 0
	186	* cannot be here.
	187	*/
	188	cmp r10, #0
	189	bleq __die @ CPU0 cannot be here
	190	ldr lr, [r12, #RESET_DATA(STARTUP_SECONDARY)]
	191	cmp lr, #0
	192	bleq __die @ no secondary startup handler
	193	bx lr
	194	#endif
	195
	196	/*
	197	* We don't know why the CPU reset. Just kill it.
	198	* The LR register will contain the address we died at + 4.
	199	*/
	200
	201	__die:
	202	sub lr, lr, #4
	203	mov32 r7, TEGRA_PMC_BASE
	204	str lr, [r7, #PMC_SCRATCH41]
	205
	206	mov32 r7, TEGRA_CLK_RESET_BASE
	207
	208	/* Are we on Tegra20? */
4b3e2eda	209	cmp r6, #TEGRA20
9e32366f JL	210	bne 1f
	211
	212	#ifdef CONFIG_ARCH_TEGRA_2x_SOC
	213	mov32 r0, 0x1111
	214	mov r1, r0, lsl r10
	215	str r1, [r7, #0x340] @ CLK_RST_CPU_CMPLX_SET
	216	#endif
	217	1:
	218	#ifdef CONFIG_ARCH_TEGRA_3x_SOC
	219	mov32 r6, TEGRA_FLOW_CTRL_BASE
	220
	221	cmp r10, #0
	222	moveq r1, #FLOW_CTRL_HALT_CPU0_EVENTS
	223	moveq r2, #FLOW_CTRL_CPU0_CSR
	224	movne r1, r10, lsl #3
	225	addne r2, r1, #(FLOW_CTRL_CPU1_CSR-8)
	226	addne r1, r1, #(FLOW_CTRL_HALT_CPU1_EVENTS-8)
	227
	228	/* Clear CPU "event" and "interrupt" flags and power gate
	229	it when halting but not before it is in the "WFI" state. */
	230	ldr r0, [r6, +r2]
	231	orr r0, r0, #FLOW_CTRL_CSR_INTR_FLAG \| FLOW_CTRL_CSR_EVENT_FLAG
	232	orr r0, r0, #FLOW_CTRL_CSR_ENABLE
	233	str r0, [r6, +r2]
	234
	235	/* Unconditionally halt this CPU */
	236	mov r0, #FLOW_CTRL_WAITEVENT
	237	str r0, [r6, +r1]
	238	ldr r0, [r6, +r1] @ memory barrier
	239
	240	dsb
	241	isb
	242	wfi @ CPU should be power gated here
	243
	244	/* If the CPU didn't power gate above just kill it's clock. */
	245
	246	mov r0, r11, lsl #8
	247	str r0, [r7, #348] @ CLK_CPU_CMPLX_SET
	248	#endif
	249
	250	/* If the CPU still isn't dead, just spin here. */
	251	b .
	252	ENDPROC(__tegra_cpu_reset_handler)
	253
	254	.align L1_CACHE_SHIFT
	255	.type __tegra_cpu_reset_handler_data, %object
	256	.globl __tegra_cpu_reset_handler_data
	257	__tegra_cpu_reset_handler_data:
	258	.rept TEGRA_RESET_DATA_SIZE
	259	.long 0
	260	.endr
	261	.align L1_CACHE_SHIFT
	262
	263	ENTRY(__tegra_cpu_reset_handler_end)