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b36ab975 PDS |
1 | /* |
2 | * arch/arm/mach-tegra/reset.c | |
3 | * | |
4 | * Copyright (C) 2011,2012 NVIDIA Corporation. | |
5 | * | |
6 | * This software is licensed under the terms of the GNU General Public | |
7 | * License version 2, as published by the Free Software Foundation, and | |
8 | * may be copied, distributed, and modified under those terms. | |
9 | * | |
10 | * This program is distributed in the hope that it will be useful, | |
11 | * but WITHOUT ANY WARRANTY; without even the implied warranty of | |
12 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
13 | * GNU General Public License for more details. | |
14 | * | |
15 | */ | |
16 | ||
17 | #include <linux/init.h> | |
18 | #include <linux/io.h> | |
19 | #include <linux/cpumask.h> | |
20 | #include <linux/bitops.h> | |
21 | ||
22 | #include <asm/cacheflush.h> | |
23 | #include <asm/hardware/cache-l2x0.h> | |
265c89c9 | 24 | #include <asm/firmware.h> |
b36ab975 | 25 | |
2be39c07 | 26 | #include "iomap.h" |
bb1de887 | 27 | #include "irammap.h" |
b36ab975 | 28 | #include "reset.h" |
d3f29365 | 29 | #include "sleep.h" |
b36ab975 PDS |
30 | #include "fuse.h" |
31 | ||
32 | #define TEGRA_IRAM_RESET_BASE (TEGRA_IRAM_BASE + \ | |
33 | TEGRA_IRAM_RESET_HANDLER_OFFSET) | |
34 | ||
35 | static bool is_enabled; | |
36 | ||
ad14ecee | 37 | static void __init tegra_cpu_reset_handler_set(const u32 reset_address) |
b36ab975 | 38 | { |
b36ab975 PDS |
39 | void __iomem *evp_cpu_reset = |
40 | IO_ADDRESS(TEGRA_EXCEPTION_VECTORS_BASE + 0x100); | |
41 | void __iomem *sb_ctrl = IO_ADDRESS(TEGRA_SB_BASE); | |
42 | u32 reg; | |
43 | ||
b36ab975 PDS |
44 | /* |
45 | * NOTE: This must be the one and only write to the EVP CPU reset | |
46 | * vector in the entire system. | |
47 | */ | |
ad14ecee | 48 | writel(reset_address, evp_cpu_reset); |
b36ab975 PDS |
49 | wmb(); |
50 | reg = readl(evp_cpu_reset); | |
51 | ||
52 | /* | |
53 | * Prevent further modifications to the physical reset vector. | |
54 | * NOTE: Has no effect on chips prior to Tegra30. | |
55 | */ | |
56 | if (tegra_chip_id != TEGRA20) { | |
57 | reg = readl(sb_ctrl); | |
58 | reg |= 2; | |
59 | writel(reg, sb_ctrl); | |
60 | wmb(); | |
61 | } | |
ad14ecee AC |
62 | } |
63 | ||
64 | static void __init tegra_cpu_reset_handler_enable(void) | |
65 | { | |
66 | void __iomem *iram_base = IO_ADDRESS(TEGRA_IRAM_RESET_BASE); | |
67 | const u32 reset_address = TEGRA_IRAM_RESET_BASE + | |
68 | tegra_cpu_reset_handler_offset; | |
265c89c9 | 69 | int err; |
ad14ecee AC |
70 | |
71 | BUG_ON(is_enabled); | |
72 | BUG_ON(tegra_cpu_reset_handler_size > TEGRA_IRAM_RESET_HANDLER_SIZE); | |
73 | ||
74 | memcpy(iram_base, (void *)__tegra_cpu_reset_handler_start, | |
75 | tegra_cpu_reset_handler_size); | |
76 | ||
265c89c9 AC |
77 | err = call_firmware_op(set_cpu_boot_addr, 0, reset_address); |
78 | switch (err) { | |
79 | case -ENOSYS: | |
80 | tegra_cpu_reset_handler_set(reset_address); | |
81 | /* pass-through */ | |
82 | case 0: | |
83 | is_enabled = true; | |
84 | break; | |
85 | default: | |
86 | pr_crit("Cannot set CPU reset handler: %d\n", err); | |
87 | BUG(); | |
88 | } | |
b36ab975 PDS |
89 | } |
90 | ||
91 | void __init tegra_cpu_reset_handler_init(void) | |
92 | { | |
93 | ||
94 | #ifdef CONFIG_SMP | |
95 | __tegra_cpu_reset_handler_data[TEGRA_RESET_MASK_PRESENT] = | |
9e32366f | 96 | *((u32 *)cpu_possible_mask); |
b36ab975 PDS |
97 | __tegra_cpu_reset_handler_data[TEGRA_RESET_STARTUP_SECONDARY] = |
98 | virt_to_phys((void *)tegra_secondary_startup); | |
99 | #endif | |
100 | ||
d3f29365 | 101 | #ifdef CONFIG_PM_SLEEP |
5b795d05 | 102 | __tegra_cpu_reset_handler_data[TEGRA_RESET_STARTUP_LP1] = |
fddb770d | 103 | TEGRA_IRAM_LPx_RESUME_AREA; |
d3f29365 JL |
104 | __tegra_cpu_reset_handler_data[TEGRA_RESET_STARTUP_LP2] = |
105 | virt_to_phys((void *)tegra_resume); | |
106 | #endif | |
107 | ||
b36ab975 PDS |
108 | tegra_cpu_reset_handler_enable(); |
109 | } |