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59b0f682 JL |
1 | /* |
2 | * Copyright (c) 2012, NVIDIA Corporation. All rights reserved. | |
3 | * | |
4 | * This program is free software; you can redistribute it and/or modify it | |
5 | * under the terms and conditions of the GNU General Public License, | |
6 | * version 2, as published by the Free Software Foundation. | |
7 | * | |
8 | * This program is distributed in the hope it will be useful, but WITHOUT | |
9 | * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or | |
10 | * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for | |
11 | * more details. | |
12 | * | |
13 | * You should have received a copy of the GNU General Public License | |
14 | * along with this program. If not, see <http://www.gnu.org/licenses/>. | |
15 | */ | |
16 | ||
17 | #include <linux/linkage.h> | |
18 | ||
304664ea TR |
19 | #include <soc/tegra/fuse.h> |
20 | ||
d457ef35 | 21 | #include <asm/asm-offsets.h> |
a0524acc | 22 | #include <asm/assembler.h> |
e7a932b1 | 23 | #include <asm/cache.h> |
59b0f682 | 24 | |
a0524acc | 25 | #include "flowctrl.h" |
fddb770d | 26 | #include "irammap.h" |
59b0f682 | 27 | #include "sleep.h" |
59b0f682 | 28 | |
e7a932b1 JL |
29 | #define EMC_CFG 0xc |
30 | #define EMC_ADR_CFG 0x10 | |
31 | #define EMC_TIMING_CONTROL 0x28 | |
32 | #define EMC_REFRESH 0x70 | |
33 | #define EMC_NOP 0xdc | |
34 | #define EMC_SELF_REF 0xe0 | |
35 | #define EMC_MRW 0xe8 | |
36 | #define EMC_FBIO_CFG5 0x104 | |
37 | #define EMC_AUTO_CAL_CONFIG 0x2a4 | |
38 | #define EMC_AUTO_CAL_INTERVAL 0x2a8 | |
39 | #define EMC_AUTO_CAL_STATUS 0x2ac | |
40 | #define EMC_REQ_CTRL 0x2b0 | |
41 | #define EMC_CFG_DIG_DLL 0x2bc | |
42 | #define EMC_EMC_STATUS 0x2b4 | |
43 | #define EMC_ZCAL_INTERVAL 0x2e0 | |
44 | #define EMC_ZQ_CAL 0x2ec | |
45 | #define EMC_XM2VTTGENPADCTRL 0x310 | |
46 | #define EMC_XM2VTTGENPADCTRL2 0x314 | |
47 | ||
48 | #define PMC_CTRL 0x0 | |
49 | #define PMC_CTRL_SIDE_EFFECT_LP0 (1 << 14) /* enter LP0 when CPU pwr gated */ | |
50 | ||
51 | #define PMC_PLLP_WB0_OVERRIDE 0xf8 | |
52 | #define PMC_IO_DPD_REQ 0x1b8 | |
53 | #define PMC_IO_DPD_STATUS 0x1bc | |
54 | ||
55 | #define CLK_RESET_CCLK_BURST 0x20 | |
56 | #define CLK_RESET_CCLK_DIVIDER 0x24 | |
57 | #define CLK_RESET_SCLK_BURST 0x28 | |
58 | #define CLK_RESET_SCLK_DIVIDER 0x2c | |
59 | ||
60 | #define CLK_RESET_PLLC_BASE 0x80 | |
61 | #define CLK_RESET_PLLC_MISC 0x8c | |
62 | #define CLK_RESET_PLLM_BASE 0x90 | |
63 | #define CLK_RESET_PLLM_MISC 0x9c | |
64 | #define CLK_RESET_PLLP_BASE 0xa0 | |
65 | #define CLK_RESET_PLLP_MISC 0xac | |
66 | #define CLK_RESET_PLLA_BASE 0xb0 | |
67 | #define CLK_RESET_PLLA_MISC 0xbc | |
68 | #define CLK_RESET_PLLX_BASE 0xe0 | |
69 | #define CLK_RESET_PLLX_MISC 0xe4 | |
e9f62449 JL |
70 | #define CLK_RESET_PLLX_MISC3 0x518 |
71 | #define CLK_RESET_PLLX_MISC3_IDDQ 3 | |
72 | #define CLK_RESET_PLLM_MISC_IDDQ 5 | |
73 | #define CLK_RESET_PLLC_MISC_IDDQ 26 | |
e7a932b1 JL |
74 | |
75 | #define CLK_RESET_CLK_SOURCE_MSELECT 0x3b4 | |
76 | ||
77 | #define MSELECT_CLKM (0x3 << 30) | |
78 | ||
79 | #define LOCK_DELAY 50 /* safety delay after lock is detected */ | |
80 | ||
59b0f682 JL |
81 | #define TEGRA30_POWER_HOTPLUG_SHUTDOWN (1 << 27) /* Hotplug shutdown */ |
82 | ||
e7a932b1 JL |
83 | .macro emc_device_mask, rd, base |
84 | ldr \rd, [\base, #EMC_ADR_CFG] | |
85 | tst \rd, #0x1 | |
86 | moveq \rd, #(0x1 << 8) @ just 1 device | |
87 | movne \rd, #(0x3 << 8) @ 2 devices | |
88 | .endm | |
89 | ||
90 | .macro emc_timing_update, rd, base | |
91 | mov \rd, #1 | |
92 | str \rd, [\base, #EMC_TIMING_CONTROL] | |
93 | 1001: | |
94 | ldr \rd, [\base, #EMC_EMC_STATUS] | |
95 | tst \rd, #(0x1<<23) @ wait EMC_STATUS_TIMING_UPDATE_STALLED is clear | |
96 | bne 1001b | |
97 | .endm | |
98 | ||
99 | .macro pll_enable, rd, r_car_base, pll_base, pll_misc | |
100 | ldr \rd, [\r_car_base, #\pll_base] | |
101 | tst \rd, #(1 << 30) | |
102 | orreq \rd, \rd, #(1 << 30) | |
103 | streq \rd, [\r_car_base, #\pll_base] | |
104 | /* Enable lock detector */ | |
105 | .if \pll_misc | |
106 | ldr \rd, [\r_car_base, #\pll_misc] | |
107 | bic \rd, \rd, #(1 << 18) | |
108 | str \rd, [\r_car_base, #\pll_misc] | |
109 | ldr \rd, [\r_car_base, #\pll_misc] | |
110 | ldr \rd, [\r_car_base, #\pll_misc] | |
111 | orr \rd, \rd, #(1 << 18) | |
112 | str \rd, [\r_car_base, #\pll_misc] | |
113 | .endif | |
114 | .endm | |
115 | ||
116 | .macro pll_locked, rd, r_car_base, pll_base | |
117 | 1: | |
118 | ldr \rd, [\r_car_base, #\pll_base] | |
119 | tst \rd, #(1 << 27) | |
120 | beq 1b | |
121 | .endm | |
122 | ||
e9f62449 JL |
123 | .macro pll_iddq_exit, rd, car, iddq, iddq_bit |
124 | ldr \rd, [\car, #\iddq] | |
125 | bic \rd, \rd, #(1<<\iddq_bit) | |
126 | str \rd, [\car, #\iddq] | |
127 | .endm | |
128 | ||
129 | .macro pll_iddq_entry, rd, car, iddq, iddq_bit | |
130 | ldr \rd, [\car, #\iddq] | |
131 | orr \rd, \rd, #(1<<\iddq_bit) | |
132 | str \rd, [\car, #\iddq] | |
133 | .endm | |
134 | ||
59b0f682 JL |
135 | #if defined(CONFIG_HOTPLUG_CPU) || defined(CONFIG_PM_SLEEP) |
136 | /* | |
137 | * tegra30_hotplug_shutdown(void) | |
138 | * | |
139 | * Powergates the current CPU. | |
140 | * Should never return. | |
141 | */ | |
142 | ENTRY(tegra30_hotplug_shutdown) | |
59b0f682 JL |
143 | /* Powergate this CPU */ |
144 | mov r0, #TEGRA30_POWER_HOTPLUG_SHUTDOWN | |
145 | bl tegra30_cpu_shutdown | |
6ebbf2ce | 146 | ret lr @ should never get here |
59b0f682 JL |
147 | ENDPROC(tegra30_hotplug_shutdown) |
148 | ||
149 | /* | |
150 | * tegra30_cpu_shutdown(unsigned long flags) | |
151 | * | |
152 | * Puts the current CPU in wait-for-event mode on the flow controller | |
153 | * and powergates it -- flags (in R0) indicate the request type. | |
59b0f682 | 154 | * |
33d5c019 JL |
155 | * r10 = SoC ID |
156 | * corrupts r0-r4, r10-r12 | |
59b0f682 JL |
157 | */ |
158 | ENTRY(tegra30_cpu_shutdown) | |
159 | cpu_id r3 | |
33d5c019 JL |
160 | tegra_get_soc_id TEGRA_APB_MISC_VIRT, r10 |
161 | cmp r10, #TEGRA30 | |
162 | bne _no_cpu0_chk @ It's not Tegra30 | |
163 | ||
59b0f682 | 164 | cmp r3, #0 |
6ebbf2ce | 165 | reteq lr @ Must never be called for CPU 0 |
33d5c019 | 166 | _no_cpu0_chk: |
59b0f682 JL |
167 | |
168 | ldr r12, =TEGRA_FLOW_CTRL_VIRT | |
169 | cpu_to_csr_reg r1, r3 | |
170 | add r1, r1, r12 @ virtual CSR address for this CPU | |
171 | cpu_to_halt_reg r2, r3 | |
172 | add r2, r2, r12 @ virtual HALT_EVENTS address for this CPU | |
173 | ||
174 | /* | |
175 | * Clear this CPU's "event" and "interrupt" flags and power gate | |
176 | * it when halting but not before it is in the "WFE" state. | |
177 | */ | |
178 | movw r12, \ | |
179 | FLOW_CTRL_CSR_INTR_FLAG | FLOW_CTRL_CSR_EVENT_FLAG | \ | |
180 | FLOW_CTRL_CSR_ENABLE | |
33d5c019 JL |
181 | cmp r10, #TEGRA30 |
182 | moveq r4, #(1 << 4) @ wfe bitmap | |
183 | movne r4, #(1 << 8) @ wfi bitmap | |
5777b4b5 JL |
184 | ARM( orr r12, r12, r4, lsl r3 ) |
185 | THUMB( lsl r4, r4, r3 ) | |
186 | THUMB( orr r12, r12, r4 ) | |
59b0f682 JL |
187 | str r12, [r1] |
188 | ||
189 | /* Halt this CPU. */ | |
190 | mov r3, #0x400 | |
191 | delay_1: | |
192 | subs r3, r3, #1 @ delay as a part of wfe war. | |
193 | bge delay_1; | |
194 | cpsid a @ disable imprecise aborts. | |
195 | ldr r3, [r1] @ read CSR | |
196 | str r3, [r1] @ clear CSR | |
33d5c019 | 197 | |
59b0f682 | 198 | tst r0, #TEGRA30_POWER_HOTPLUG_SHUTDOWN |
33d5c019 JL |
199 | beq flow_ctrl_setting_for_lp2 |
200 | ||
201 | /* flow controller set up for hotplug */ | |
202 | mov r3, #FLOW_CTRL_WAITEVENT @ For hotplug | |
203 | b flow_ctrl_done | |
204 | flow_ctrl_setting_for_lp2: | |
205 | /* flow controller set up for LP2 */ | |
206 | cmp r10, #TEGRA30 | |
d457ef35 | 207 | moveq r3, #FLOW_CTRL_WAIT_FOR_INTERRUPT @ For LP2 |
33d5c019 | 208 | movne r3, #FLOW_CTRL_WAITEVENT |
1b9e6b27 JL |
209 | orrne r3, r3, #FLOW_CTRL_HALT_GIC_IRQ |
210 | orrne r3, r3, #FLOW_CTRL_HALT_GIC_FIQ | |
33d5c019 JL |
211 | flow_ctrl_done: |
212 | cmp r10, #TEGRA30 | |
59b0f682 JL |
213 | str r3, [r2] |
214 | ldr r0, [r2] | |
215 | b wfe_war | |
216 | ||
217 | __cpu_reset_again: | |
218 | dsb | |
219 | .align 5 | |
33d5c019 JL |
220 | wfeeq @ CPU should be power gated here |
221 | wfine | |
59b0f682 JL |
222 | wfe_war: |
223 | b __cpu_reset_again | |
224 | ||
225 | /* | |
85aa5047 | 226 | * 38 nop's, which fills rest of wfe cache line and |
59b0f682 JL |
227 | * 4 more cachelines with nop |
228 | */ | |
229 | .rept 38 | |
230 | nop | |
231 | .endr | |
232 | b . @ should never get here | |
233 | ||
234 | ENDPROC(tegra30_cpu_shutdown) | |
235 | #endif | |
d457ef35 JL |
236 | |
237 | #ifdef CONFIG_PM_SLEEP | |
e7a932b1 JL |
238 | /* |
239 | * tegra30_sleep_core_finish(unsigned long v2p) | |
240 | * | |
241 | * Enters suspend in LP0 or LP1 by turning off the MMU and jumping to | |
242 | * tegra30_tear_down_core in IRAM | |
243 | */ | |
244 | ENTRY(tegra30_sleep_core_finish) | |
245 | /* Flush, disable the L1 data cache and exit SMP */ | |
246 | bl tegra_disable_clean_inv_dcache | |
247 | ||
248 | /* | |
249 | * Preload all the address literals that are needed for the | |
250 | * CPU power-gating process, to avoid loading from SDRAM which | |
251 | * are not supported once SDRAM is put into self-refresh. | |
252 | * LP0 / LP1 use physical address, since the MMU needs to be | |
253 | * disabled before putting SDRAM into self-refresh to avoid | |
254 | * memory access due to page table walks. | |
255 | */ | |
256 | mov32 r4, TEGRA_PMC_BASE | |
257 | mov32 r5, TEGRA_CLK_RESET_BASE | |
258 | mov32 r6, TEGRA_FLOW_CTRL_BASE | |
259 | mov32 r7, TEGRA_TMRUS_BASE | |
260 | ||
261 | mov32 r3, tegra_shut_off_mmu | |
262 | add r3, r3, r0 | |
263 | ||
264 | mov32 r0, tegra30_tear_down_core | |
265 | mov32 r1, tegra30_iram_start | |
266 | sub r0, r0, r1 | |
fddb770d | 267 | mov32 r1, TEGRA_IRAM_LPx_RESUME_AREA |
e7a932b1 JL |
268 | add r0, r0, r1 |
269 | ||
6ebbf2ce | 270 | ret r3 |
e7a932b1 JL |
271 | ENDPROC(tegra30_sleep_core_finish) |
272 | ||
d457ef35 JL |
273 | /* |
274 | * tegra30_sleep_cpu_secondary_finish(unsigned long v2p) | |
275 | * | |
276 | * Enters LP2 on secondary CPU by exiting coherency and powergating the CPU. | |
277 | */ | |
278 | ENTRY(tegra30_sleep_cpu_secondary_finish) | |
279 | mov r7, lr | |
280 | ||
281 | /* Flush and disable the L1 data cache */ | |
ac2527bf | 282 | mov r0, #TEGRA_FLUSH_CACHE_LOUIS |
d457ef35 JL |
283 | bl tegra_disable_clean_inv_dcache |
284 | ||
285 | /* Powergate this CPU. */ | |
286 | mov r0, #0 @ power mode flags (!hotplug) | |
287 | bl tegra30_cpu_shutdown | |
288 | mov r0, #1 @ never return here | |
6ebbf2ce | 289 | ret r7 |
d457ef35 | 290 | ENDPROC(tegra30_sleep_cpu_secondary_finish) |
d552920a JL |
291 | |
292 | /* | |
293 | * tegra30_tear_down_cpu | |
294 | * | |
295 | * Switches the CPU to enter sleep. | |
296 | */ | |
297 | ENTRY(tegra30_tear_down_cpu) | |
298 | mov32 r6, TEGRA_FLOW_CTRL_BASE | |
299 | ||
300 | b tegra30_enter_sleep | |
301 | ENDPROC(tegra30_tear_down_cpu) | |
302 | ||
e7a932b1 JL |
303 | /* START OF ROUTINES COPIED TO IRAM */ |
304 | .align L1_CACHE_SHIFT | |
305 | .globl tegra30_iram_start | |
306 | tegra30_iram_start: | |
307 | ||
308 | /* | |
309 | * tegra30_lp1_reset | |
310 | * | |
311 | * reset vector for LP1 restore; copied into IRAM during suspend. | |
312 | * Brings the system back up to a safe staring point (SDRAM out of | |
313 | * self-refresh, PLLC, PLLM and PLLP reenabled, CPU running on PLLX, | |
314 | * system clock running on the same PLL that it suspended at), and | |
315 | * jumps to tegra_resume to restore virtual addressing. | |
316 | * The physical address of tegra_resume expected to be stored in | |
317 | * PMC_SCRATCH41. | |
318 | * | |
fddb770d | 319 | * NOTE: THIS *MUST* BE RELOCATED TO TEGRA_IRAM_LPx_RESUME_AREA. |
e7a932b1 JL |
320 | */ |
321 | ENTRY(tegra30_lp1_reset) | |
322 | /* | |
323 | * The CPU and system bus are running at 32KHz and executing from | |
324 | * IRAM when this code is executed; immediately switch to CLKM and | |
325 | * enable PLLP, PLLM, PLLC, PLLA and PLLX. | |
326 | */ | |
327 | mov32 r0, TEGRA_CLK_RESET_BASE | |
328 | ||
329 | mov r1, #(1 << 28) | |
330 | str r1, [r0, #CLK_RESET_SCLK_BURST] | |
331 | str r1, [r0, #CLK_RESET_CCLK_BURST] | |
332 | mov r1, #0 | |
333 | str r1, [r0, #CLK_RESET_CCLK_DIVIDER] | |
334 | str r1, [r0, #CLK_RESET_SCLK_DIVIDER] | |
335 | ||
e9f62449 JL |
336 | tegra_get_soc_id TEGRA_APB_MISC_BASE, r10 |
337 | cmp r10, #TEGRA30 | |
338 | beq _no_pll_iddq_exit | |
339 | ||
340 | pll_iddq_exit r1, r0, CLK_RESET_PLLM_MISC, CLK_RESET_PLLM_MISC_IDDQ | |
341 | pll_iddq_exit r1, r0, CLK_RESET_PLLC_MISC, CLK_RESET_PLLC_MISC_IDDQ | |
342 | pll_iddq_exit r1, r0, CLK_RESET_PLLX_MISC3, CLK_RESET_PLLX_MISC3_IDDQ | |
343 | ||
344 | mov32 r7, TEGRA_TMRUS_BASE | |
345 | ldr r1, [r7] | |
346 | add r1, r1, #2 | |
347 | wait_until r1, r7, r3 | |
348 | ||
349 | /* enable PLLM via PMC */ | |
350 | mov32 r2, TEGRA_PMC_BASE | |
351 | ldr r1, [r2, #PMC_PLLP_WB0_OVERRIDE] | |
352 | orr r1, r1, #(1 << 12) | |
353 | str r1, [r2, #PMC_PLLP_WB0_OVERRIDE] | |
354 | ||
355 | pll_enable r1, r0, CLK_RESET_PLLM_BASE, 0 | |
356 | pll_enable r1, r0, CLK_RESET_PLLC_BASE, 0 | |
357 | pll_enable r1, r0, CLK_RESET_PLLX_BASE, 0 | |
358 | ||
359 | b _pll_m_c_x_done | |
360 | ||
361 | _no_pll_iddq_exit: | |
e7a932b1 JL |
362 | /* enable PLLM via PMC */ |
363 | mov32 r2, TEGRA_PMC_BASE | |
364 | ldr r1, [r2, #PMC_PLLP_WB0_OVERRIDE] | |
365 | orr r1, r1, #(1 << 12) | |
366 | str r1, [r2, #PMC_PLLP_WB0_OVERRIDE] | |
367 | ||
368 | pll_enable r1, r0, CLK_RESET_PLLM_BASE, CLK_RESET_PLLM_MISC | |
e7a932b1 JL |
369 | pll_enable r1, r0, CLK_RESET_PLLC_BASE, CLK_RESET_PLLC_MISC |
370 | pll_enable r1, r0, CLK_RESET_PLLX_BASE, CLK_RESET_PLLX_MISC | |
371 | ||
e9f62449 JL |
372 | _pll_m_c_x_done: |
373 | pll_enable r1, r0, CLK_RESET_PLLP_BASE, CLK_RESET_PLLP_MISC | |
374 | pll_enable r1, r0, CLK_RESET_PLLA_BASE, CLK_RESET_PLLA_MISC | |
375 | ||
e7a932b1 JL |
376 | pll_locked r1, r0, CLK_RESET_PLLM_BASE |
377 | pll_locked r1, r0, CLK_RESET_PLLP_BASE | |
378 | pll_locked r1, r0, CLK_RESET_PLLA_BASE | |
379 | pll_locked r1, r0, CLK_RESET_PLLC_BASE | |
380 | pll_locked r1, r0, CLK_RESET_PLLX_BASE | |
381 | ||
382 | mov32 r7, TEGRA_TMRUS_BASE | |
383 | ldr r1, [r7] | |
384 | add r1, r1, #LOCK_DELAY | |
385 | wait_until r1, r7, r3 | |
386 | ||
92e94fe1 | 387 | adr r5, tegra_sdram_pad_save |
e7a932b1 JL |
388 | |
389 | ldr r4, [r5, #0x18] @ restore CLK_SOURCE_MSELECT | |
390 | str r4, [r0, #CLK_RESET_CLK_SOURCE_MSELECT] | |
391 | ||
392 | ldr r4, [r5, #0x1C] @ restore SCLK_BURST | |
393 | str r4, [r0, #CLK_RESET_SCLK_BURST] | |
394 | ||
e9f62449 JL |
395 | cmp r10, #TEGRA30 |
396 | movweq r4, #:lower16:((1 << 28) | (0x8)) @ burst policy is PLLX | |
397 | movteq r4, #:upper16:((1 << 28) | (0x8)) | |
398 | movwne r4, #:lower16:((1 << 28) | (0xe)) | |
399 | movtne r4, #:upper16:((1 << 28) | (0xe)) | |
e7a932b1 JL |
400 | str r4, [r0, #CLK_RESET_CCLK_BURST] |
401 | ||
402 | /* Restore pad power state to normal */ | |
403 | ldr r1, [r5, #0x14] @ PMC_IO_DPD_STATUS | |
404 | mvn r1, r1 | |
405 | bic r1, r1, #(1 << 31) | |
406 | orr r1, r1, #(1 << 30) | |
407 | str r1, [r2, #PMC_IO_DPD_REQ] @ DPD_OFF | |
408 | ||
e9f62449 JL |
409 | cmp r10, #TEGRA30 |
410 | movweq r0, #:lower16:TEGRA_EMC_BASE @ r0 reserved for emc base | |
411 | movteq r0, #:upper16:TEGRA_EMC_BASE | |
f0c4ac13 JL |
412 | cmp r10, #TEGRA114 |
413 | movweq r0, #:lower16:TEGRA_EMC0_BASE | |
414 | movteq r0, #:upper16:TEGRA_EMC0_BASE | |
415 | cmp r10, #TEGRA124 | |
416 | movweq r0, #:lower16:TEGRA124_EMC_BASE | |
417 | movteq r0, #:upper16:TEGRA124_EMC_BASE | |
e7a932b1 | 418 | |
e9f62449 | 419 | exit_self_refresh: |
e7a932b1 JL |
420 | ldr r1, [r5, #0xC] @ restore EMC_XM2VTTGENPADCTRL |
421 | str r1, [r0, #EMC_XM2VTTGENPADCTRL] | |
422 | ldr r1, [r5, #0x10] @ restore EMC_XM2VTTGENPADCTRL2 | |
423 | str r1, [r0, #EMC_XM2VTTGENPADCTRL2] | |
424 | ldr r1, [r5, #0x8] @ restore EMC_AUTO_CAL_INTERVAL | |
425 | str r1, [r0, #EMC_AUTO_CAL_INTERVAL] | |
426 | ||
427 | /* Relock DLL */ | |
428 | ldr r1, [r0, #EMC_CFG_DIG_DLL] | |
429 | orr r1, r1, #(1 << 30) @ set DLL_RESET | |
430 | str r1, [r0, #EMC_CFG_DIG_DLL] | |
431 | ||
432 | emc_timing_update r1, r0 | |
433 | ||
e9f62449 JL |
434 | cmp r10, #TEGRA114 |
435 | movweq r1, #:lower16:TEGRA_EMC1_BASE | |
436 | movteq r1, #:upper16:TEGRA_EMC1_BASE | |
437 | cmpeq r0, r1 | |
438 | ||
e7a932b1 JL |
439 | ldr r1, [r0, #EMC_AUTO_CAL_CONFIG] |
440 | orr r1, r1, #(1 << 31) @ set AUTO_CAL_ACTIVE | |
e9f62449 | 441 | orreq r1, r1, #(1 << 27) @ set slave mode for channel 1 |
e7a932b1 JL |
442 | str r1, [r0, #EMC_AUTO_CAL_CONFIG] |
443 | ||
444 | emc_wait_auto_cal_onetime: | |
445 | ldr r1, [r0, #EMC_AUTO_CAL_STATUS] | |
446 | tst r1, #(1 << 31) @ wait until AUTO_CAL_ACTIVE is cleared | |
447 | bne emc_wait_auto_cal_onetime | |
448 | ||
449 | ldr r1, [r0, #EMC_CFG] | |
450 | bic r1, r1, #(1 << 31) @ disable DRAM_CLK_STOP_PD | |
451 | str r1, [r0, #EMC_CFG] | |
452 | ||
453 | mov r1, #0 | |
454 | str r1, [r0, #EMC_SELF_REF] @ take DRAM out of self refresh | |
455 | mov r1, #1 | |
e9f62449 JL |
456 | cmp r10, #TEGRA30 |
457 | streq r1, [r0, #EMC_NOP] | |
458 | streq r1, [r0, #EMC_NOP] | |
459 | streq r1, [r0, #EMC_REFRESH] | |
e7a932b1 JL |
460 | |
461 | emc_device_mask r1, r0 | |
462 | ||
463 | exit_selfrefresh_loop: | |
464 | ldr r2, [r0, #EMC_EMC_STATUS] | |
465 | ands r2, r2, r1 | |
466 | bne exit_selfrefresh_loop | |
467 | ||
468 | lsr r1, r1, #8 @ devSel, bit0:dev0, bit1:dev1 | |
469 | ||
470 | mov32 r7, TEGRA_TMRUS_BASE | |
471 | ldr r2, [r0, #EMC_FBIO_CFG5] | |
472 | ||
473 | and r2, r2, #3 @ check DRAM_TYPE | |
474 | cmp r2, #2 | |
475 | beq emc_lpddr2 | |
476 | ||
477 | /* Issue a ZQ_CAL for dev0 - DDR3 */ | |
478 | mov32 r2, 0x80000011 @ DEV_SELECTION=2, LENGTH=LONG, CMD=1 | |
479 | str r2, [r0, #EMC_ZQ_CAL] | |
480 | ldr r2, [r7] | |
481 | add r2, r2, #10 | |
482 | wait_until r2, r7, r3 | |
483 | ||
484 | tst r1, #2 | |
485 | beq zcal_done | |
486 | ||
487 | /* Issue a ZQ_CAL for dev1 - DDR3 */ | |
488 | mov32 r2, 0x40000011 @ DEV_SELECTION=1, LENGTH=LONG, CMD=1 | |
489 | str r2, [r0, #EMC_ZQ_CAL] | |
490 | ldr r2, [r7] | |
491 | add r2, r2, #10 | |
492 | wait_until r2, r7, r3 | |
493 | b zcal_done | |
494 | ||
495 | emc_lpddr2: | |
496 | /* Issue a ZQ_CAL for dev0 - LPDDR2 */ | |
497 | mov32 r2, 0x800A00AB @ DEV_SELECTION=2, MA=10, OP=0xAB | |
498 | str r2, [r0, #EMC_MRW] | |
499 | ldr r2, [r7] | |
500 | add r2, r2, #1 | |
501 | wait_until r2, r7, r3 | |
502 | ||
503 | tst r1, #2 | |
504 | beq zcal_done | |
505 | ||
506 | /* Issue a ZQ_CAL for dev0 - LPDDR2 */ | |
507 | mov32 r2, 0x400A00AB @ DEV_SELECTION=1, MA=10, OP=0xAB | |
508 | str r2, [r0, #EMC_MRW] | |
509 | ldr r2, [r7] | |
510 | add r2, r2, #1 | |
511 | wait_until r2, r7, r3 | |
512 | ||
513 | zcal_done: | |
514 | mov r1, #0 @ unstall all transactions | |
515 | str r1, [r0, #EMC_REQ_CTRL] | |
516 | ldr r1, [r5, #0x4] @ restore EMC_ZCAL_INTERVAL | |
517 | str r1, [r0, #EMC_ZCAL_INTERVAL] | |
518 | ldr r1, [r5, #0x0] @ restore EMC_CFG | |
519 | str r1, [r0, #EMC_CFG] | |
520 | ||
e9f62449 JL |
521 | /* Tegra114 had dual EMC channel, now config the other one */ |
522 | cmp r10, #TEGRA114 | |
523 | bne __no_dual_emc_chanl | |
524 | mov32 r1, TEGRA_EMC1_BASE | |
525 | cmp r0, r1 | |
526 | movne r0, r1 | |
527 | addne r5, r5, #0x20 | |
528 | bne exit_self_refresh | |
529 | __no_dual_emc_chanl: | |
530 | ||
e7a932b1 JL |
531 | mov32 r0, TEGRA_PMC_BASE |
532 | ldr r0, [r0, #PMC_SCRATCH41] | |
6ebbf2ce | 533 | ret r0 @ jump to tegra_resume |
e7a932b1 JL |
534 | ENDPROC(tegra30_lp1_reset) |
535 | ||
536 | .align L1_CACHE_SHIFT | |
537 | tegra30_sdram_pad_address: | |
538 | .word TEGRA_EMC_BASE + EMC_CFG @0x0 | |
539 | .word TEGRA_EMC_BASE + EMC_ZCAL_INTERVAL @0x4 | |
540 | .word TEGRA_EMC_BASE + EMC_AUTO_CAL_INTERVAL @0x8 | |
541 | .word TEGRA_EMC_BASE + EMC_XM2VTTGENPADCTRL @0xc | |
542 | .word TEGRA_EMC_BASE + EMC_XM2VTTGENPADCTRL2 @0x10 | |
543 | .word TEGRA_PMC_BASE + PMC_IO_DPD_STATUS @0x14 | |
544 | .word TEGRA_CLK_RESET_BASE + CLK_RESET_CLK_SOURCE_MSELECT @0x18 | |
545 | .word TEGRA_CLK_RESET_BASE + CLK_RESET_SCLK_BURST @0x1c | |
92e94fe1 | 546 | tegra30_sdram_pad_address_end: |
e7a932b1 | 547 | |
e9f62449 JL |
548 | tegra114_sdram_pad_address: |
549 | .word TEGRA_EMC0_BASE + EMC_CFG @0x0 | |
550 | .word TEGRA_EMC0_BASE + EMC_ZCAL_INTERVAL @0x4 | |
551 | .word TEGRA_EMC0_BASE + EMC_AUTO_CAL_INTERVAL @0x8 | |
552 | .word TEGRA_EMC0_BASE + EMC_XM2VTTGENPADCTRL @0xc | |
553 | .word TEGRA_EMC0_BASE + EMC_XM2VTTGENPADCTRL2 @0x10 | |
554 | .word TEGRA_PMC_BASE + PMC_IO_DPD_STATUS @0x14 | |
555 | .word TEGRA_CLK_RESET_BASE + CLK_RESET_CLK_SOURCE_MSELECT @0x18 | |
556 | .word TEGRA_CLK_RESET_BASE + CLK_RESET_SCLK_BURST @0x1c | |
557 | .word TEGRA_EMC1_BASE + EMC_CFG @0x20 | |
558 | .word TEGRA_EMC1_BASE + EMC_ZCAL_INTERVAL @0x24 | |
559 | .word TEGRA_EMC1_BASE + EMC_AUTO_CAL_INTERVAL @0x28 | |
560 | .word TEGRA_EMC1_BASE + EMC_XM2VTTGENPADCTRL @0x2c | |
561 | .word TEGRA_EMC1_BASE + EMC_XM2VTTGENPADCTRL2 @0x30 | |
92e94fe1 | 562 | tegra114_sdram_pad_adress_end: |
e9f62449 | 563 | |
f0c4ac13 JL |
564 | tegra124_sdram_pad_address: |
565 | .word TEGRA124_EMC_BASE + EMC_CFG @0x0 | |
566 | .word TEGRA124_EMC_BASE + EMC_ZCAL_INTERVAL @0x4 | |
567 | .word TEGRA124_EMC_BASE + EMC_AUTO_CAL_INTERVAL @0x8 | |
568 | .word TEGRA124_EMC_BASE + EMC_XM2VTTGENPADCTRL @0xc | |
569 | .word TEGRA124_EMC_BASE + EMC_XM2VTTGENPADCTRL2 @0x10 | |
570 | .word TEGRA_PMC_BASE + PMC_IO_DPD_STATUS @0x14 | |
571 | .word TEGRA_CLK_RESET_BASE + CLK_RESET_CLK_SOURCE_MSELECT @0x18 | |
572 | .word TEGRA_CLK_RESET_BASE + CLK_RESET_SCLK_BURST @0x1c | |
573 | tegra124_sdram_pad_address_end: | |
574 | ||
e7a932b1 | 575 | tegra30_sdram_pad_size: |
92e94fe1 | 576 | .word tegra30_sdram_pad_address_end - tegra30_sdram_pad_address |
e9f62449 JL |
577 | |
578 | tegra114_sdram_pad_size: | |
92e94fe1 | 579 | .word tegra114_sdram_pad_adress_end - tegra114_sdram_pad_address |
e7a932b1 | 580 | |
92e94fe1 JL |
581 | .type tegra_sdram_pad_save, %object |
582 | tegra_sdram_pad_save: | |
583 | .rept (tegra114_sdram_pad_adress_end - tegra114_sdram_pad_address) / 4 | |
e7a932b1 JL |
584 | .long 0 |
585 | .endr | |
586 | ||
587 | /* | |
588 | * tegra30_tear_down_core | |
589 | * | |
590 | * copied into and executed from IRAM | |
591 | * puts memory in self-refresh for LP0 and LP1 | |
592 | */ | |
593 | tegra30_tear_down_core: | |
594 | bl tegra30_sdram_self_refresh | |
595 | bl tegra30_switch_cpu_to_clk32k | |
596 | b tegra30_enter_sleep | |
597 | ||
598 | /* | |
599 | * tegra30_switch_cpu_to_clk32k | |
600 | * | |
601 | * In LP0 and LP1 all PLLs will be turned off. Switching the CPU and System CLK | |
602 | * to the 32KHz clock. | |
603 | * r4 = TEGRA_PMC_BASE | |
604 | * r5 = TEGRA_CLK_RESET_BASE | |
605 | * r6 = TEGRA_FLOW_CTRL_BASE | |
606 | * r7 = TEGRA_TMRUS_BASE | |
e9f62449 | 607 | * r10= SoC ID |
e7a932b1 JL |
608 | */ |
609 | tegra30_switch_cpu_to_clk32k: | |
610 | /* | |
611 | * start by jumping to CLKM to safely disable PLLs, then jump to | |
612 | * CLKS. | |
613 | */ | |
614 | mov r0, #(1 << 28) | |
615 | str r0, [r5, #CLK_RESET_SCLK_BURST] | |
616 | /* 2uS delay delay between changing SCLK and CCLK */ | |
617 | ldr r1, [r7] | |
618 | add r1, r1, #2 | |
619 | wait_until r1, r7, r9 | |
620 | str r0, [r5, #CLK_RESET_CCLK_BURST] | |
621 | mov r0, #0 | |
622 | str r0, [r5, #CLK_RESET_CCLK_DIVIDER] | |
623 | str r0, [r5, #CLK_RESET_SCLK_DIVIDER] | |
624 | ||
625 | /* switch the clock source of mselect to be CLK_M */ | |
626 | ldr r0, [r5, #CLK_RESET_CLK_SOURCE_MSELECT] | |
627 | orr r0, r0, #MSELECT_CLKM | |
628 | str r0, [r5, #CLK_RESET_CLK_SOURCE_MSELECT] | |
629 | ||
630 | /* 2uS delay delay between changing SCLK and disabling PLLs */ | |
631 | ldr r1, [r7] | |
632 | add r1, r1, #2 | |
633 | wait_until r1, r7, r9 | |
634 | ||
635 | /* disable PLLM via PMC in LP1 */ | |
636 | ldr r0, [r4, #PMC_PLLP_WB0_OVERRIDE] | |
637 | bic r0, r0, #(1 << 12) | |
638 | str r0, [r4, #PMC_PLLP_WB0_OVERRIDE] | |
639 | ||
640 | /* disable PLLP, PLLA, PLLC and PLLX */ | |
641 | ldr r0, [r5, #CLK_RESET_PLLP_BASE] | |
642 | bic r0, r0, #(1 << 30) | |
643 | str r0, [r5, #CLK_RESET_PLLP_BASE] | |
644 | ldr r0, [r5, #CLK_RESET_PLLA_BASE] | |
645 | bic r0, r0, #(1 << 30) | |
646 | str r0, [r5, #CLK_RESET_PLLA_BASE] | |
647 | ldr r0, [r5, #CLK_RESET_PLLC_BASE] | |
648 | bic r0, r0, #(1 << 30) | |
649 | str r0, [r5, #CLK_RESET_PLLC_BASE] | |
650 | ldr r0, [r5, #CLK_RESET_PLLX_BASE] | |
651 | bic r0, r0, #(1 << 30) | |
652 | str r0, [r5, #CLK_RESET_PLLX_BASE] | |
653 | ||
e9f62449 JL |
654 | cmp r10, #TEGRA30 |
655 | beq _no_pll_in_iddq | |
656 | pll_iddq_entry r1, r5, CLK_RESET_PLLX_MISC3, CLK_RESET_PLLX_MISC3_IDDQ | |
657 | _no_pll_in_iddq: | |
658 | ||
e7a932b1 JL |
659 | /* switch to CLKS */ |
660 | mov r0, #0 /* brust policy = 32KHz */ | |
661 | str r0, [r5, #CLK_RESET_SCLK_BURST] | |
662 | ||
6ebbf2ce | 663 | ret lr |
e7a932b1 | 664 | |
d552920a JL |
665 | /* |
666 | * tegra30_enter_sleep | |
667 | * | |
668 | * uses flow controller to enter sleep state | |
669 | * executes from IRAM with SDRAM in selfrefresh when target state is LP0 or LP1 | |
670 | * executes from SDRAM with target state is LP2 | |
671 | * r6 = TEGRA_FLOW_CTRL_BASE | |
672 | */ | |
673 | tegra30_enter_sleep: | |
674 | cpu_id r1 | |
675 | ||
676 | cpu_to_csr_reg r2, r1 | |
677 | ldr r0, [r6, r2] | |
678 | orr r0, r0, #FLOW_CTRL_CSR_INTR_FLAG | FLOW_CTRL_CSR_EVENT_FLAG | |
679 | orr r0, r0, #FLOW_CTRL_CSR_ENABLE | |
680 | str r0, [r6, r2] | |
681 | ||
ccea4bc6 JL |
682 | tegra_get_soc_id TEGRA_APB_MISC_BASE, r10 |
683 | cmp r10, #TEGRA30 | |
d552920a | 684 | mov r0, #FLOW_CTRL_WAIT_FOR_INTERRUPT |
ccea4bc6 JL |
685 | orreq r0, r0, #FLOW_CTRL_HALT_CPU_IRQ | FLOW_CTRL_HALT_CPU_FIQ |
686 | orrne r0, r0, #FLOW_CTRL_HALT_LIC_IRQ | FLOW_CTRL_HALT_LIC_FIQ | |
687 | ||
d552920a JL |
688 | cpu_to_halt_reg r2, r1 |
689 | str r0, [r6, r2] | |
690 | dsb | |
691 | ldr r0, [r6, r2] /* memory barrier */ | |
692 | ||
693 | halted: | |
694 | isb | |
695 | dsb | |
696 | wfi /* CPU should be power gated here */ | |
697 | ||
698 | /* !!!FIXME!!! Implement halt failure handler */ | |
699 | b halted | |
700 | ||
e7a932b1 JL |
701 | /* |
702 | * tegra30_sdram_self_refresh | |
703 | * | |
704 | * called with MMU off and caches disabled | |
705 | * must be executed from IRAM | |
706 | * r4 = TEGRA_PMC_BASE | |
707 | * r5 = TEGRA_CLK_RESET_BASE | |
708 | * r6 = TEGRA_FLOW_CTRL_BASE | |
709 | * r7 = TEGRA_TMRUS_BASE | |
e9f62449 | 710 | * r10= SoC ID |
e7a932b1 JL |
711 | */ |
712 | tegra30_sdram_self_refresh: | |
713 | ||
92e94fe1 | 714 | adr r8, tegra_sdram_pad_save |
e9f62449 JL |
715 | tegra_get_soc_id TEGRA_APB_MISC_BASE, r10 |
716 | cmp r10, #TEGRA30 | |
717 | adreq r2, tegra30_sdram_pad_address | |
718 | ldreq r3, tegra30_sdram_pad_size | |
f0c4ac13 JL |
719 | cmp r10, #TEGRA114 |
720 | adreq r2, tegra114_sdram_pad_address | |
721 | ldreq r3, tegra114_sdram_pad_size | |
722 | cmp r10, #TEGRA124 | |
723 | adreq r2, tegra124_sdram_pad_address | |
724 | ldreq r3, tegra30_sdram_pad_size | |
725 | ||
e7a932b1 JL |
726 | mov r9, #0 |
727 | ||
e7a932b1 JL |
728 | padsave: |
729 | ldr r0, [r2, r9] @ r0 is the addr in the pad_address | |
730 | ||
731 | ldr r1, [r0] | |
732 | str r1, [r8, r9] @ save the content of the addr | |
733 | ||
734 | add r9, r9, #4 | |
735 | cmp r3, r9 | |
736 | bne padsave | |
737 | padsave_done: | |
738 | ||
739 | dsb | |
740 | ||
e9f62449 JL |
741 | cmp r10, #TEGRA30 |
742 | ldreq r0, =TEGRA_EMC_BASE @ r0 reserved for emc base addr | |
f0c4ac13 JL |
743 | cmp r10, #TEGRA114 |
744 | ldreq r0, =TEGRA_EMC0_BASE | |
745 | cmp r10, #TEGRA124 | |
746 | ldreq r0, =TEGRA124_EMC_BASE | |
e7a932b1 | 747 | |
e9f62449 JL |
748 | enter_self_refresh: |
749 | cmp r10, #TEGRA30 | |
e7a932b1 JL |
750 | mov r1, #0 |
751 | str r1, [r0, #EMC_ZCAL_INTERVAL] | |
752 | str r1, [r0, #EMC_AUTO_CAL_INTERVAL] | |
753 | ldr r1, [r0, #EMC_CFG] | |
754 | bic r1, r1, #(1 << 28) | |
e9f62449 | 755 | bicne r1, r1, #(1 << 29) |
e7a932b1 JL |
756 | str r1, [r0, #EMC_CFG] @ disable DYN_SELF_REF |
757 | ||
758 | emc_timing_update r1, r0 | |
759 | ||
760 | ldr r1, [r7] | |
761 | add r1, r1, #5 | |
762 | wait_until r1, r7, r2 | |
763 | ||
764 | emc_wait_auto_cal: | |
765 | ldr r1, [r0, #EMC_AUTO_CAL_STATUS] | |
766 | tst r1, #(1 << 31) @ wait until AUTO_CAL_ACTIVE is cleared | |
767 | bne emc_wait_auto_cal | |
768 | ||
769 | mov r1, #3 | |
770 | str r1, [r0, #EMC_REQ_CTRL] @ stall incoming DRAM requests | |
771 | ||
772 | emcidle: | |
773 | ldr r1, [r0, #EMC_EMC_STATUS] | |
774 | tst r1, #4 | |
775 | beq emcidle | |
776 | ||
777 | mov r1, #1 | |
778 | str r1, [r0, #EMC_SELF_REF] | |
779 | ||
780 | emc_device_mask r1, r0 | |
781 | ||
782 | emcself: | |
783 | ldr r2, [r0, #EMC_EMC_STATUS] | |
784 | and r2, r2, r1 | |
785 | cmp r2, r1 | |
786 | bne emcself @ loop until DDR in self-refresh | |
787 | ||
788 | /* Put VTTGEN in the lowest power mode */ | |
789 | ldr r1, [r0, #EMC_XM2VTTGENPADCTRL] | |
790 | mov32 r2, 0xF8F8FFFF @ clear XM2VTTGEN_DRVUP and XM2VTTGEN_DRVDN | |
791 | and r1, r1, r2 | |
792 | str r1, [r0, #EMC_XM2VTTGENPADCTRL] | |
793 | ldr r1, [r0, #EMC_XM2VTTGENPADCTRL2] | |
e9f62449 JL |
794 | cmp r10, #TEGRA30 |
795 | orreq r1, r1, #7 @ set E_NO_VTTGEN | |
796 | orrne r1, r1, #0x3f | |
e7a932b1 JL |
797 | str r1, [r0, #EMC_XM2VTTGENPADCTRL2] |
798 | ||
799 | emc_timing_update r1, r0 | |
800 | ||
e9f62449 JL |
801 | /* Tegra114 had dual EMC channel, now config the other one */ |
802 | cmp r10, #TEGRA114 | |
803 | bne no_dual_emc_chanl | |
804 | mov32 r1, TEGRA_EMC1_BASE | |
805 | cmp r0, r1 | |
806 | movne r0, r1 | |
807 | bne enter_self_refresh | |
808 | no_dual_emc_chanl: | |
809 | ||
e7a932b1 JL |
810 | ldr r1, [r4, #PMC_CTRL] |
811 | tst r1, #PMC_CTRL_SIDE_EFFECT_LP0 | |
812 | bne pmc_io_dpd_skip | |
813 | /* | |
814 | * Put DDR_DATA, DISC_ADDR_CMD, DDR_ADDR_CMD, POP_ADDR_CMD, POP_CLK | |
815 | * and COMP in the lowest power mode when LP1. | |
816 | */ | |
817 | mov32 r1, 0x8EC00000 | |
818 | str r1, [r4, #PMC_IO_DPD_REQ] | |
819 | pmc_io_dpd_skip: | |
820 | ||
821 | dsb | |
822 | ||
6ebbf2ce | 823 | ret lr |
e7a932b1 JL |
824 | |
825 | .ltorg | |
826 | /* dummy symbol for end of IRAM */ | |
827 | .align L1_CACHE_SHIFT | |
828 | .global tegra30_iram_end | |
829 | tegra30_iram_end: | |
830 | b . | |
d457ef35 | 831 | #endif |