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1 | /* |
2 | * Copyright (c) 2010-2012, NVIDIA Corporation. All rights reserved. | |
3 | * | |
4 | * This program is free software; you can redistribute it and/or modify it | |
5 | * under the terms and conditions of the GNU General Public License, | |
6 | * version 2, as published by the Free Software Foundation. | |
7 | * | |
8 | * This program is distributed in the hope it will be useful, but WITHOUT | |
9 | * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or | |
10 | * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for | |
11 | * more details. | |
12 | * | |
13 | * You should have received a copy of the GNU General Public License | |
14 | * along with this program. If not, see <http://www.gnu.org/licenses/>. | |
15 | */ | |
16 | ||
17 | #ifndef __MACH_TEGRA_SLEEP_H | |
18 | #define __MACH_TEGRA_SLEEP_H | |
19 | ||
2be39c07 | 20 | #include "iomap.h" |
c2be5bfc | 21 | |
59b0f682 JL |
22 | #define TEGRA_ARM_PERIF_VIRT (TEGRA_ARM_PERIF_BASE - IO_CPU_PHYS \ |
23 | + IO_CPU_VIRT) | |
c2be5bfc JL |
24 | #define TEGRA_FLOW_CTRL_VIRT (TEGRA_FLOW_CTRL_BASE - IO_PPSB_PHYS \ |
25 | + IO_PPSB_VIRT) | |
453689e4 JL |
26 | #define TEGRA_CLK_RESET_VIRT (TEGRA_CLK_RESET_BASE - IO_PPSB_PHYS \ |
27 | + IO_PPSB_VIRT) | |
c2be5bfc JL |
28 | |
29 | #ifdef __ASSEMBLY__ | |
30 | /* returns the offset of the flow controller halt register for a cpu */ | |
31 | .macro cpu_to_halt_reg rd, rcpu | |
32 | cmp \rcpu, #0 | |
33 | subne \rd, \rcpu, #1 | |
34 | movne \rd, \rd, lsl #3 | |
35 | addne \rd, \rd, #0x14 | |
36 | moveq \rd, #0 | |
37 | .endm | |
38 | ||
39 | /* returns the offset of the flow controller csr register for a cpu */ | |
40 | .macro cpu_to_csr_reg rd, rcpu | |
41 | cmp \rcpu, #0 | |
42 | subne \rd, \rcpu, #1 | |
43 | movne \rd, \rd, lsl #3 | |
44 | addne \rd, \rd, #0x18 | |
45 | moveq \rd, #8 | |
46 | .endm | |
47 | ||
48 | /* returns the ID of the current processor */ | |
49 | .macro cpu_id, rd | |
50 | mrc p15, 0, \rd, c0, c0, 5 | |
51 | and \rd, \rd, #0xF | |
52 | .endm | |
53 | ||
54 | /* loads a 32-bit value into a register without a data access */ | |
55 | .macro mov32, reg, val | |
56 | movw \reg, #:lower16:\val | |
57 | movt \reg, #:upper16:\val | |
58 | .endm | |
59b0f682 JL |
59 | |
60 | /* Macro to exit SMP coherency. */ | |
61 | .macro exit_smp, tmp1, tmp2 | |
62 | mrc p15, 0, \tmp1, c1, c0, 1 @ ACTLR | |
63 | bic \tmp1, \tmp1, #(1<<6) | (1<<0) @ clear ACTLR.SMP | ACTLR.FW | |
64 | mcr p15, 0, \tmp1, c1, c0, 1 @ ACTLR | |
65 | isb | |
66 | cpu_id \tmp1 | |
67 | mov \tmp1, \tmp1, lsl #2 | |
68 | mov \tmp2, #0xf | |
69 | mov \tmp2, \tmp2, lsl \tmp1 | |
70 | mov32 \tmp1, TEGRA_ARM_PERIF_VIRT + 0xC | |
71 | str \tmp2, [\tmp1] @ invalidate SCU tags for CPU | |
72 | dsb | |
73 | .endm | |
74 | #else | |
d3f29365 | 75 | void tegra_resume(void); |
59b0f682 JL |
76 | |
77 | #ifdef CONFIG_HOTPLUG_CPU | |
453689e4 | 78 | void tegra20_hotplug_init(void); |
59b0f682 JL |
79 | void tegra30_hotplug_init(void); |
80 | #else | |
453689e4 | 81 | static inline void tegra20_hotplug_init(void) {} |
59b0f682 JL |
82 | static inline void tegra30_hotplug_init(void) {} |
83 | #endif | |
84 | ||
d457ef35 JL |
85 | int tegra30_sleep_cpu_secondary_finish(unsigned long); |
86 | ||
c2be5bfc JL |
87 | #endif |
88 | #endif |